RTEMS 6.1-rc6
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fsl_enet.h
1/*
2 * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc.
3 * Copyright 2016-2022 NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8#ifndef _FSL_ENET_H_
9#define _FSL_ENET_H_
10
11#include "fsl_common.h"
12#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET
13#include "fsl_memory.h"
14#endif
20/*******************************************************************************
21 * Definitions
22 ******************************************************************************/
23
27#define FSL_ENET_DRIVER_VERSION (MAKE_VERSION(2, 6, 3))
33#ifndef FSL_FEATURE_ENET_QUEUE
34#define FSL_FEATURE_ENET_QUEUE 1 /* Singal queue for previous IP. */
35#endif
40#define ENET_BUFFDESCRIPTOR_RX_EMPTY_MASK 0x8000U
41#define ENET_BUFFDESCRIPTOR_RX_SOFTOWNER1_MASK 0x4000U
42#define ENET_BUFFDESCRIPTOR_RX_WRAP_MASK 0x2000U
43#define ENET_BUFFDESCRIPTOR_RX_SOFTOWNER2_Mask 0x1000U
44#define ENET_BUFFDESCRIPTOR_RX_LAST_MASK 0x0800U
45#define ENET_BUFFDESCRIPTOR_RX_MISS_MASK 0x0100U
46#define ENET_BUFFDESCRIPTOR_RX_BROADCAST_MASK 0x0080U
47#define ENET_BUFFDESCRIPTOR_RX_MULTICAST_MASK 0x0040U
48#define ENET_BUFFDESCRIPTOR_RX_LENVLIOLATE_MASK 0x0020U
49#define ENET_BUFFDESCRIPTOR_RX_NOOCTET_MASK 0x0010U
50#define ENET_BUFFDESCRIPTOR_RX_CRC_MASK 0x0004U
51#define ENET_BUFFDESCRIPTOR_RX_OVERRUN_MASK 0x0002U
52#define ENET_BUFFDESCRIPTOR_RX_TRUNC_MASK 0x0001U
54
57#define ENET_BUFFDESCRIPTOR_TX_READY_MASK 0x8000U
58#define ENET_BUFFDESCRIPTOR_TX_SOFTOWENER1_MASK 0x4000U
59#define ENET_BUFFDESCRIPTOR_TX_WRAP_MASK 0x2000U
60#define ENET_BUFFDESCRIPTOR_TX_SOFTOWENER2_MASK 0x1000U
61#define ENET_BUFFDESCRIPTOR_TX_LAST_MASK 0x0800U
62#define ENET_BUFFDESCRIPTOR_TX_TRANMITCRC_MASK 0x0400U
64
65/* Extended control regions for enhanced buffer descriptors. */
66#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE
69#define ENET_BUFFDESCRIPTOR_RX_IPV4_MASK 0x0001U
70#define ENET_BUFFDESCRIPTOR_RX_IPV6_MASK 0x0002U
71#define ENET_BUFFDESCRIPTOR_RX_VLAN_MASK 0x0004U
72#define ENET_BUFFDESCRIPTOR_RX_PROTOCOLCHECKSUM_MASK 0x0010U
73#define ENET_BUFFDESCRIPTOR_RX_IPHEADCHECKSUM_MASK 0x0020U
75
78#define ENET_BUFFDESCRIPTOR_RX_INTERRUPT_MASK 0x0080U
79#define ENET_BUFFDESCRIPTOR_RX_UNICAST_MASK 0x0100U
80#define ENET_BUFFDESCRIPTOR_RX_COLLISION_MASK 0x0200U
81#define ENET_BUFFDESCRIPTOR_RX_PHYERR_MASK 0x0400U
82#define ENET_BUFFDESCRIPTOR_RX_MACERR_MASK 0x8000U
84
87#define ENET_BUFFDESCRIPTOR_TX_ERR_MASK 0x8000U
88#define ENET_BUFFDESCRIPTOR_TX_UNDERFLOWERR_MASK 0x2000U
89#define ENET_BUFFDESCRIPTOR_TX_EXCCOLLISIONERR_MASK 0x1000U
90#define ENET_BUFFDESCRIPTOR_TX_FRAMEERR_MASK 0x0800U
91#define ENET_BUFFDESCRIPTOR_TX_LATECOLLISIONERR_MASK 0x0400U
92#define ENET_BUFFDESCRIPTOR_TX_OVERFLOWERR_MASK 0x0200U
93#define ENET_BUFFDESCRIPTOR_TX_TIMESTAMPERR_MASK 0x0100U
95
98#define ENET_BUFFDESCRIPTOR_TX_INTERRUPT_MASK 0x4000U
99#define ENET_BUFFDESCRIPTOR_TX_TIMESTAMP_MASK 0x2000U
100#define ENET_BUFFDESCRIPTOR_TX_PROTOCHECKSUM_MASK 0x1000U
101#define ENET_BUFFDESCRIPTOR_TX_IPCHECKSUM_MASK 0x0800U
102#if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB
103#define ENET_BUFFDESCRIPTOR_TX_USETXLAUNCHTIME_MASK 0x0100U
104#define ENET_BUFFDESCRIPTOR_TX_FRAMETYPE_MASK 0x00F0U
105#define ENET_BUFFDESCRIPTOR_TX_FRAMETYPE_SHIFT 4U
106#define ENET_BD_FTYPE(n) \
107 (((uint32_t)(n) << ENET_BUFFDESCRIPTOR_TX_FRAMETYPE_SHIFT) & ENET_BUFFDESCRIPTOR_TX_FRAMETYPE_MASK)
108#endif /* FSL_FEATURE_ENET_HAS_AVB */
110#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */
111
113#define ENET_BUFFDESCRIPTOR_RX_ERR_MASK \
114 (ENET_BUFFDESCRIPTOR_RX_TRUNC_MASK | ENET_BUFFDESCRIPTOR_RX_OVERRUN_MASK | \
115 ENET_BUFFDESCRIPTOR_RX_LENVLIOLATE_MASK | ENET_BUFFDESCRIPTOR_RX_NOOCTET_MASK | ENET_BUFFDESCRIPTOR_RX_CRC_MASK)
116#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE
117#define ENET_BUFFDESCRIPTOR_RX_EXT_ERR_MASK \
118 (ENET_BUFFDESCRIPTOR_RX_MACERR_MASK | ENET_BUFFDESCRIPTOR_RX_PHYERR_MASK | ENET_BUFFDESCRIPTOR_RX_COLLISION_MASK)
119#endif
120
123#define ENET_FRAME_MAX_FRAMELEN 1518U
124#define ENET_FRAME_VLAN_TAGLEN 4U
125#define ENET_FRAME_CRC_LEN 4U
126#define ENET_FRAME_TX_LEN_LIMITATION(x) \
127 ((((x)->RCR & ENET_RCR_MAX_FL_MASK) >> ENET_RCR_MAX_FL_SHIFT) - ENET_FRAME_CRC_LEN)
128
129#define ENET_FIFO_MIN_RX_FULL 5U
130#define ENET_RX_MIN_BUFFERSIZE 256U
131#define ENET_PHY_MAXADDRESS (ENET_MMFR_PA_MASK >> ENET_MMFR_PA_SHIFT)
133#if FSL_FEATURE_ENET_QUEUE > 1
134#define ENET_TX_INTERRUPT \
135 ((uint32_t)kENET_TxFrameInterrupt | (uint32_t)kENET_TxBufferInterrupt | (uint32_t)kENET_TxFrame1Interrupt | \
136 (uint32_t)kENET_TxBuffer1Interrupt | (uint32_t)kENET_TxFrame2Interrupt | \
137 (uint32_t)kENET_TxBuffer2Interrupt)
138#define ENET_RX_INTERRUPT \
139 ((uint32_t)kENET_RxFrameInterrupt | (uint32_t)kENET_RxBufferInterrupt | (uint32_t)kENET_RxFrame1Interrupt | \
140 (uint32_t)kENET_RxBuffer1Interrupt | (uint32_t)kENET_RxFrame2Interrupt | \
141 (uint32_t)kENET_RxBuffer2Interrupt)
142#else
143#define ENET_TX_INTERRUPT \
144 ((uint32_t)kENET_TxFrameInterrupt | (uint32_t)kENET_TxBufferInterrupt)
145#define ENET_RX_INTERRUPT \
146 ((uint32_t)kENET_RxFrameInterrupt | (uint32_t)kENET_RxBufferInterrupt)
147#endif /* FSL_FEATURE_ENET_QUEUE > 1 */
148#define ENET_TS_INTERRUPT \
149 ((uint32_t)kENET_TsTimerInterrupt | (uint32_t)kENET_TsAvailInterrupt)
150#define ENET_ERR_INTERRUPT \
151 ((uint32_t)kENET_BabrInterrupt | (uint32_t)kENET_BabtInterrupt | (uint32_t)kENET_EBusERInterrupt | \
152 (uint32_t)kENET_LateCollisionInterrupt | (uint32_t)kENET_RetryLimitInterrupt | \
153 (uint32_t)kENET_UnderrunInterrupt | (uint32_t)kENET_PayloadRxInterrupt)
155
157enum
158{
168};
169
171typedef enum _enet_mii_mode
172{
175#if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB
176 kENET_RgmiiMode = 2U
177#endif /* FSL_FEATURE_ENET_HAS_AVB */
179
184typedef enum _enet_mii_speed
185{
188#if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB
189 kENET_MiiSpeed1000M = 2U
190#endif /* FSL_FEATURE_ENET_HAS_AVB */
192
195{
199
201typedef enum _enet_mii_write
202{
206
208typedef enum _enet_mii_read
209{
213
214#if defined(FSL_FEATURE_ENET_HAS_EXTEND_MDIO) && FSL_FEATURE_ENET_HAS_EXTEND_MDIO
216typedef enum _enet_mii_extend_opcode
217{
218 kENET_MiiAddrWrite_C45 = 0U,
219 kENET_MiiWriteFrame_C45 = 1U,
220 kENET_MiiReadFrame_C45 = 3U
221} enet_mii_extend_opcode;
222#endif /* FSL_FEATURE_ENET_HAS_EXTEND_MDIO */
223
237{
248#if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB
249 kENET_ControlSVLANEnable = 0x0400U,
250 kENET_ControlVLANUseSecondTag = 0x0800U
251#endif /* FSL_FEATURE_ENET_HAS_AVB */
253
260{
261 kENET_BabrInterrupt = ENET_EIR_BABR_MASK,
262 kENET_BabtInterrupt = ENET_EIR_BABT_MASK,
263 kENET_GraceStopInterrupt = ENET_EIR_GRA_MASK,
264 kENET_TxFrameInterrupt = ENET_EIR_TXF_MASK,
265 kENET_TxBufferInterrupt = ENET_EIR_TXB_MASK,
266 kENET_RxFrameInterrupt = ENET_EIR_RXF_MASK,
267 kENET_RxBufferInterrupt = ENET_EIR_RXB_MASK,
268 kENET_MiiInterrupt = ENET_EIR_MII_MASK,
269 kENET_EBusERInterrupt = ENET_EIR_EBERR_MASK,
270 kENET_LateCollisionInterrupt = ENET_EIR_LC_MASK,
271 kENET_RetryLimitInterrupt = ENET_EIR_RL_MASK,
272 kENET_UnderrunInterrupt = ENET_EIR_UN_MASK,
273 kENET_PayloadRxInterrupt = ENET_EIR_PLR_MASK,
274 kENET_WakeupInterrupt = ENET_EIR_WAKEUP_MASK,
275#if FSL_FEATURE_ENET_QUEUE > 1
276 kENET_RxFlush2Interrupt = ENET_EIR_RXFLUSH_2_MASK,
277 kENET_RxFlush1Interrupt = ENET_EIR_RXFLUSH_1_MASK,
278 kENET_RxFlush0Interrupt = ENET_EIR_RXFLUSH_0_MASK,
279 kENET_TxFrame2Interrupt = ENET_EIR_TXF2_MASK,
280 kENET_TxBuffer2Interrupt = ENET_EIR_TXB2_MASK,
281 kENET_RxFrame2Interrupt = ENET_EIR_RXF2_MASK,
282 kENET_RxBuffer2Interrupt = ENET_EIR_RXB2_MASK,
283 kENET_TxFrame1Interrupt = ENET_EIR_TXF1_MASK,
284 kENET_TxBuffer1Interrupt = ENET_EIR_TXB1_MASK,
285 kENET_RxFrame1Interrupt = ENET_EIR_RXF1_MASK,
286 kENET_RxBuffer1Interrupt = ENET_EIR_RXB1_MASK,
287#endif /* FSL_FEATURE_ENET_QUEUE > 1 */
288 kENET_TsAvailInterrupt = ENET_EIR_TS_AVAIL_MASK,
289 kENET_TsTimerInterrupt = ENET_EIR_TS_TIMER_MASK
291
293typedef enum _enet_event
294{
302
303#if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB
305typedef enum _enet_idle_slope
306{
307 kENET_IdleSlope1 = 1U,
308 kENET_IdleSlope2 = 2U,
309 kENET_IdleSlope4 = 4U,
310 kENET_IdleSlope8 = 8U,
311 kENET_IdleSlope16 = 16U,
312 kENET_IdleSlope32 = 32U,
313 kENET_IdleSlope64 = 64U,
314 kENET_IdleSlope128 = 128U,
315 kENET_IdleSlope256 = 256U,
316 kENET_IdleSlope384 = 384U,
317 kENET_IdleSlope512 = 512U,
318 kENET_IdleSlope640 = 640U,
319 kENET_IdleSlope768 = 768U,
320 kENET_IdleSlope896 = 896U,
321 kENET_IdleSlope1024 = 1024U,
322 kENET_IdleSlope1152 = 1152U,
323 kENET_IdleSlope1280 = 1280U,
324 kENET_IdleSlope1408 = 1408U,
325 kENET_IdleSlope1536 = 1536U
326} enet_idle_slope_t;
327#endif /* FSL_FEATURE_ENET_HAS_AVB */
328
331{
332 kENET_TxAccelIsShift16Enabled = ENET_TACC_SHIFT16_MASK,
333 kENET_TxAccelIpCheckEnabled = ENET_TACC_IPCHK_MASK,
334 kENET_TxAccelProtoCheckEnabled = ENET_TACC_PROCHK_MASK
336
339{
340 kENET_RxAccelPadRemoveEnabled = ENET_RACC_PADREM_MASK,
341 kENET_RxAccelIpCheckEnabled = ENET_RACC_IPDIS_MASK,
342 kENET_RxAccelProtoCheckEnabled = ENET_RACC_PRODIS_MASK,
343 kENET_RxAccelMacCheckEnabled = ENET_RACC_LINEDIS_MASK,
344 kENET_RxAccelisShift16Enabled = ENET_RACC_SHIFT16_MASK
346
347#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE
349typedef enum _enet_ptp_event_type
350{
351 kENET_PtpEventMsgType = 3U,
352 kENET_PtpSrcPortIdLen = 10U,
353 kENET_PtpEventPort = 319U,
354 kENET_PtpGnrlPort = 320U
355} enet_ptp_event_type_t;
356
358typedef enum _enet_ptp_timer_channel
359{
360 kENET_PtpTimerChannel1 = 0U,
361 kENET_PtpTimerChannel2,
362 kENET_PtpTimerChannel3,
363 kENET_PtpTimerChannel4
364} enet_ptp_timer_channel_t;
365
367typedef enum _enet_ptp_timer_channel_mode
368{
369 kENET_PtpChannelDisable = 0U,
370 kENET_PtpChannelRisingCapture = 1U,
371 kENET_PtpChannelFallingCapture = 2U,
372 kENET_PtpChannelBothCapture = 3U,
373 kENET_PtpChannelSoftCompare = 4U,
374 kENET_PtpChannelToggleCompare = 5U,
375 kENET_PtpChannelClearCompare = 6U,
376 kENET_PtpChannelSetCompare = 7U,
377 kENET_PtpChannelClearCompareSetOverflow = 10U,
378 kENET_PtpChannelSetCompareClearOverflow = 11U,
379 kENET_PtpChannelPulseLowonCompare = 14U,
380 kENET_PtpChannelPulseHighonCompare = 15U
381} enet_ptp_timer_channel_mode_t;
382#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */
383
385typedef struct _enet_rx_bd_struct
386{
387 uint16_t length;
388 uint16_t control;
389 uint32_t buffer;
390#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE
391 uint16_t controlExtend0;
392 uint16_t controlExtend1;
393 uint16_t payloadCheckSum;
394 uint8_t headerLength;
395 uint8_t protocolTyte;
396 uint16_t reserved0;
397 uint16_t controlExtend2;
398 uint32_t timestamp;
399 uint16_t reserved1;
400 uint16_t reserved2;
401 uint16_t reserved3;
402 uint16_t reserved4;
403#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */
405
407typedef struct _enet_tx_bd_struct
408{
409 uint16_t length;
410 uint16_t control;
411 uint32_t buffer;
412#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE
413 uint16_t controlExtend0;
414 uint16_t controlExtend1;
415#if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB
416 uint16_t txLaunchTimeLow;
417 uint16_t txLaunchTimeHigh;
418#else
419 uint16_t reserved0;
420 uint16_t reserved1;
421#endif /* FSL_FEATURE_ENET_HAS_AVB */
422 uint16_t reserved2;
423 uint16_t controlExtend2;
424 uint32_t timestamp;
425 uint16_t reserved3;
426 uint16_t reserved4;
427 uint16_t reserved5;
428 uint16_t reserved6;
429#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */
431
434{
437 uint32_t statsRxFcsErr;
440#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE
441 uint32_t statsRxProtocolChecksumErr;
442 uint32_t statsRxIpHeadChecksumErr;
443 uint32_t statsRxMacErr;
444 uint32_t statsRxPhyErr;
445 uint32_t statsRxCollisionErr;
446 uint32_t statsTxErr;
447 uint32_t statsTxFrameErr;
448 uint32_t statsTxOverFlowErr;
449 uint32_t statsTxLateCollisionErr;
450 uint32_t statsTxExcessCollisionErr;
451 uint32_t statsTxUnderFlowErr;
452 uint32_t statsTxTsErr;
453#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */
455
458{
461 bool statsRxFcsErr : 1;
462 bool : 1;
465 uint32_t : 19;
466#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE
467 bool statsRxCollisionErr : 1;
468 bool statsRxPhyErr : 1;
469 uint8_t : 4;
470 bool statsRxMacErr : 1;
471#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */
473
476{
478 uint32_t statsRxFrameOk;
479 uint32_t statsRxCrcErr;
484 uint32_t statsTxFrameOk;
488
489#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE
491typedef struct _enet_ptp_time
492{
493 uint64_t second;
494 uint32_t nanosecond;
495} enet_ptp_time_t;
496
498typedef struct _enet_ptp_time_data
499{
500 uint8_t version;
501 uint8_t sourcePortId[kENET_PtpSrcPortIdLen];
502 uint16_t sequenceId;
503 uint8_t messageType;
504 enet_ptp_time_t timeStamp;
505} enet_ptp_time_data_t;
506
508typedef struct _enet_ptp_config
509{
510 enet_ptp_timer_channel_t channel;
511 uint32_t ptp1588ClockSrc_Hz;
512} enet_ptp_config_t;
513#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */
514
516typedef struct enet_frame_info
517{
518 void *context;
519#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE
520 bool isTsAvail;
521 enet_ptp_time_t timeStamp;
522#endif
524
527{
529 uint16_t txGenIdx;
530 uint16_t txConsumIdx;
531 uint16_t txRingLen;
532 bool isFull;
534
536typedef void *(*enet_rx_alloc_callback_t)(ENET_Type *base, void *userData, uint8_t ringId);
537
539typedef void (*enet_rx_free_callback_t)(ENET_Type *base, void *buffer, void *userData, uint8_t ringId);
540
557{
558 uint16_t rxBdNumber;
559 uint16_t txBdNumber;
562 volatile enet_rx_bd_struct_t
564 volatile enet_tx_bd_struct_t
566 uint8_t *rxBufferAlign;
567 uint8_t *txBufferAlign;
572
573#if defined(FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE) && FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE
575typedef struct _enet_intcoalesce_config
576{
577 uint8_t txCoalesceFrameCount[FSL_FEATURE_ENET_QUEUE];
578 uint16_t txCoalesceTimeCount[FSL_FEATURE_ENET_QUEUE];
579 uint8_t rxCoalesceFrameCount[FSL_FEATURE_ENET_QUEUE];
580 uint16_t rxCoalesceTimeCount[FSL_FEATURE_ENET_QUEUE];
581} enet_intcoalesce_config_t;
582#endif /* FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE */
583
584#if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB
595typedef struct _enet_avb_config
596{
597 uint16_t rxClassifyMatch[FSL_FEATURE_ENET_QUEUE - 1];
598 enet_idle_slope_t idleSlope[FSL_FEATURE_ENET_QUEUE - 1];
599} enet_avb_config_t;
600#endif /* FSL_FEATURE_ENET_HAS_AVB */
601
602/* Forward declaration of the handle typedef. */
603typedef struct _enet_handle enet_handle_t;
604
606typedef void (*enet_callback_t)(ENET_Type *base,
607 enet_handle_t *handle,
608#if FSL_FEATURE_ENET_QUEUE > 1
609 uint32_t ringId,
610#endif /* FSL_FEATURE_ENET_QUEUE > 1 */
611 enet_event_t event,
612 enet_frame_info_t *frameInfo,
613 void *userData);
614
645typedef struct _enet_config
646{
648 uint32_t interrupt;
649 uint16_t rxMaxFrameLen;
655 uint16_t pauseDuration;
658#if defined(FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD) && FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD
659 uint8_t rxFifoStatEmptyThreshold;
662#endif /* FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD */
667#if defined(FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE) && FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE
668 enet_intcoalesce_config_t *intCoalesceCfg;
670#endif /* FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE */
671 uint8_t ringNum;
675 void *userData;
677
679typedef struct _enet_tx_bd_ring
680{
682 uint16_t txGenIdx;
683 uint16_t txConsumIdx;
684 volatile uint16_t txDescUsed;
685 uint16_t txRingLen;
687
689typedef struct _enet_rx_bd_ring
690{
692 uint16_t rxGenIdx;
693 uint16_t rxRingLen;
695
698{
705 uint8_t ringNum;
707 void *userData;
712#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE
713 volatile enet_tx_bd_struct_t
714 *txBdDirtyStatic[FSL_FEATURE_ENET_QUEUE];
715 uint64_t msTimerSecond;
716#endif
717 uint8_t multicastCount[64];
718#if defined(FSL_FEATURE_ENET_TIMESTAMP_CAPTURE_BIT_INVALID) && FSL_FEATURE_ENET_TIMESTAMP_CAPTURE_BIT_INVALID
719 uint32_t enetClock;
720 uint32_t tsDelayCount;
721#endif
722};
723
725{
726 void *buffer;
727 uint16_t length;
729
731{
733#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE
734 uint32_t timestamp;
735#endif
737
739{
741 uint16_t totLen;
745
746#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE
747typedef struct _enet_tx_config_struct
748{
749 bool intEnable : 1;
750 bool tsEnable : 1;
751 bool autoProtocolChecksum : 1;
752 bool autoIPChecksum : 1;
753 uint8_t AVBFrameType : 4;
754 bool tltEnable : 1;
755 uint16_t tltLow;
756 uint16_t tltHigh;
757} enet_tx_config_struct_t;
758#endif
759
761{
763 uint32_t txBuffNum;
764#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE
765 enet_tx_config_struct_t txConfig;
766#endif
767 void *context;
769
771#if FSL_FEATURE_ENET_QUEUE > 1
772typedef void (*enet_isr_ring_t)(ENET_Type *base, enet_handle_t *handle, uint32_t ringId);
773#endif /* FSL_FEATURE_ENET_QUEUE > 1 */
774typedef void (*enet_isr_t)(ENET_Type *base, enet_handle_t *handle);
775
777#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
778extern const clock_ip_name_t s_enetClock[];
779#if defined(FSL_FEATURE_ENET_HAS_EXTRA_CLOCK_GATE) && FSL_FEATURE_ENET_HAS_EXTRA_CLOCK_GATE
780extern const clock_ip_name_t s_enetExtraClock[];
781#endif
782#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
783
784/*******************************************************************************
785 * API
786 ******************************************************************************/
787
788#if defined(__cplusplus)
789extern "C" {
790#endif
791
798uint32_t ENET_GetInstance(ENET_Type *base);
799
820
851 enet_handle_t *handle,
852 const enet_config_t *config,
853 const enet_buffer_config_t *bufferConfig,
854 uint8_t *macAddr,
855 uint32_t srcClock_Hz);
856
886 enet_handle_t *handle,
887 const enet_config_t *config,
888 const enet_buffer_config_t *bufferConfig,
889 uint8_t *macAddr,
890 uint32_t srcClock_Hz);
891
899void ENET_Down(ENET_Type *base);
900
908void ENET_Deinit(ENET_Type *base);
909
919static inline void ENET_Reset(ENET_Type *base)
920{
921 base->ECR |= ENET_ECR_RESET_MASK;
922}
923
924/* @} */
925
941
951void ENET_SetSMI(ENET_Type *base, uint32_t srcClock_Hz, bool isPreambleDisabled);
952
962static inline bool ENET_GetSMI(ENET_Type *base)
963{
964 return (0U != (base->MSCR & 0x7EU));
965}
966
973static inline uint32_t ENET_ReadSMIData(ENET_Type *base)
974{
975 return (uint32_t)((base->MMFR & ENET_MMFR_DATA_MASK) >> ENET_MMFR_DATA_SHIFT);
976}
977
991static inline void ENET_StartSMIWrite(
992 ENET_Type *base, uint8_t phyAddr, uint8_t regAddr, enet_mii_write_t operation, uint16_t data)
993{
994 base->MMFR = ENET_MMFR_ST(1U) | ENET_MMFR_OP(operation) | ENET_MMFR_PA(phyAddr) | ENET_MMFR_RA(regAddr) |
995 ENET_MMFR_TA(2U) | data;
996}
997
1010static inline void ENET_StartSMIRead(ENET_Type *base, uint8_t phyAddr, uint8_t regAddr, enet_mii_read_t operation)
1011{
1012 base->MMFR =
1013 ENET_MMFR_ST(1U) | ENET_MMFR_OP(operation) | ENET_MMFR_PA(phyAddr) | ENET_MMFR_RA(regAddr) | ENET_MMFR_TA(2U);
1014}
1015
1026status_t ENET_MDIOWrite(ENET_Type *base, uint8_t phyAddr, uint8_t regAddr, uint16_t data);
1027
1038status_t ENET_MDIORead(ENET_Type *base, uint8_t phyAddr, uint8_t regAddr, uint16_t *pData);
1039
1040#if defined(FSL_FEATURE_ENET_HAS_EXTEND_MDIO) && FSL_FEATURE_ENET_HAS_EXTEND_MDIO
1053static inline void ENET_StartExtC45SMIWriteReg(ENET_Type *base, uint8_t portAddr, uint8_t devAddr, uint16_t regAddr)
1054{
1055 base->MMFR = ENET_MMFR_ST(0) | ENET_MMFR_OP(kENET_MiiAddrWrite_C45) | ENET_MMFR_PA(portAddr) |
1056 ENET_MMFR_RA(devAddr) | ENET_MMFR_TA(2) | ENET_MMFR_DATA(regAddr);
1057}
1058
1071static inline void ENET_StartExtC45SMIWriteData(ENET_Type *base, uint8_t portAddr, uint8_t devAddr, uint16_t data)
1072{
1073 base->MMFR = ENET_MMFR_ST(0) | ENET_MMFR_OP(kENET_MiiWriteFrame_C45) | ENET_MMFR_PA(portAddr) |
1074 ENET_MMFR_RA(devAddr) | ENET_MMFR_TA(2) | ENET_MMFR_DATA(data);
1075}
1076
1088static inline void ENET_StartExtC45SMIReadData(ENET_Type *base, uint8_t portAddr, uint8_t devAddr)
1089{
1090 base->MMFR = ENET_MMFR_ST(0) | ENET_MMFR_OP(kENET_MiiReadFrame_C45) | ENET_MMFR_PA(portAddr) |
1091 ENET_MMFR_RA(devAddr) | ENET_MMFR_TA(2);
1092}
1093
1105status_t ENET_MDIOC45Write(ENET_Type *base, uint8_t portAddr, uint8_t devAddr, uint16_t regAddr, uint16_t data);
1106
1118status_t ENET_MDIOC45Read(ENET_Type *base, uint8_t portAddr, uint8_t devAddr, uint16_t regAddr, uint16_t *pData);
1119#endif /* FSL_FEATURE_ENET_HAS_EXTEND_MDIO */
1120
1121#if ((defined(FSL_FEATURE_ENET_HAS_RGMII_TXC_DELAY) && FSL_FEATURE_ENET_HAS_RGMII_TXC_DELAY) || \
1122 (defined(FSL_FEATURE_ENET_HAS_RGMII_RXC_DELAY) && FSL_FEATURE_ENET_HAS_RGMII_RXC_DELAY))
1130static inline void ENET_SetRGMIIClockDelay(ENET_Type *base, bool txEnabled, bool rxEnabled)
1131{
1132 uint32_t ecrReg = base->ECR;
1133
1134#if defined(FSL_FEATURE_ENET_HAS_RGMII_TXC_DELAY) && FSL_FEATURE_ENET_HAS_RGMII_TXC_DELAY
1135 /* Set for transmit clock delay. */
1136 if (txEnabled)
1137 {
1138 ecrReg |= ENET_ECR_TXC_DLY_MASK;
1139 }
1140 else
1141 {
1142 ecrReg &= ~ENET_ECR_TXC_DLY_MASK;
1143 }
1144#endif /* FSL_FEATURE_ENET_HAS_RGMII_TXC_DELAY */
1145
1146#if defined(FSL_FEATURE_ENET_HAS_RGMII_RXC_DELAY) && FSL_FEATURE_ENET_HAS_RGMII_RXC_DELAY
1147 /* Set for receive clock delay. */
1148 if (rxEnabled)
1149 {
1150 ecrReg |= ENET_ECR_RXC_DLY_MASK;
1151 }
1152 else
1153 {
1154 ecrReg &= ~ENET_ECR_RXC_DLY_MASK;
1155 }
1156#endif /* FSL_FEATURE_ENET_HAS_RGMII_RXC_DELAY */
1157 base->ECR = ecrReg;
1158}
1159#endif
1160
1161/* @} */
1162
1175void ENET_SetMacAddr(ENET_Type *base, uint8_t *macAddr);
1176
1184void ENET_GetMacAddr(ENET_Type *base, uint8_t *macAddr);
1185
1192void ENET_AddMulticastGroup(ENET_Type *base, uint8_t *address);
1193
1200void ENET_LeaveMulticastGroup(ENET_Type *base, uint8_t *address);
1201
1202/* @} */
1203
1209#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE
1210#if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB
1226void ENET_AVBConfigure(ENET_Type *base, enet_handle_t *handle, const enet_avb_config_t *config);
1227#endif /* FSL_FEATURE_ENET_HAS_AVB */
1228#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */
1229
1240static inline void ENET_ActiveRead(ENET_Type *base)
1241{
1242 base->RDAR = ENET_RDAR_RDAR_MASK;
1243#if FSL_FEATURE_ENET_QUEUE > 1
1244 if (FSL_FEATURE_ENET_INSTANCE_QUEUEn(base) > 1)
1245 {
1246 base->RDAR1 = ENET_RDAR1_RDAR_MASK;
1247 base->RDAR2 = ENET_RDAR2_RDAR_MASK;
1248 }
1249#endif /* FSL_FEATURE_ENET_QUEUE > 1 */
1250}
1251
1261static inline void ENET_EnableSleepMode(ENET_Type *base, bool enable)
1262{
1263 if (enable)
1264 {
1265 /* When this field is set, MAC enters sleep mode. */
1266 base->ECR |= ENET_ECR_SLEEP_MASK | ENET_ECR_MAGICEN_MASK;
1267 }
1268 else
1269 { /* MAC exits sleep mode. */
1270 base->ECR &= ~(ENET_ECR_SLEEP_MASK | ENET_ECR_MAGICEN_MASK);
1271 }
1272}
1273
1283static inline void ENET_GetAccelFunction(ENET_Type *base, uint32_t *txAccelOption, uint32_t *rxAccelOption)
1284{
1285 assert(txAccelOption != NULL);
1286 assert(txAccelOption != NULL);
1287
1288 *txAccelOption = base->TACC;
1289 *rxAccelOption = base->RACC;
1290}
1291
1292/* @} */
1293
1313static inline void ENET_EnableInterrupts(ENET_Type *base, uint32_t mask)
1314{
1315 base->EIMR |= mask;
1316}
1317
1332static inline void ENET_DisableInterrupts(ENET_Type *base, uint32_t mask)
1333{
1334 base->EIMR &= ~mask;
1335}
1336
1344static inline uint32_t ENET_GetInterruptStatus(ENET_Type *base)
1345{
1346 return base->EIR;
1347}
1348
1363static inline void ENET_ClearInterruptStatus(ENET_Type *base, uint32_t mask)
1364{
1365 base->EIR = mask;
1366}
1367
1368#if FSL_FEATURE_ENET_QUEUE > 1
1375void ENET_SetRxISRHandler(ENET_Type *base, enet_isr_ring_t ISRHandler);
1376
1383void ENET_SetTxISRHandler(ENET_Type *base, enet_isr_ring_t ISRHandler);
1384
1385#else
1392void ENET_SetRxISRHandler(ENET_Type *base, enet_isr_t ISRHandler);
1393
1400void ENET_SetTxISRHandler(ENET_Type *base, enet_isr_t ISRHandler);
1401#endif /* FSL_FEATURE_ENET_QUEUE > 1 */
1402
1409void ENET_SetErrISRHandler(ENET_Type *base, enet_isr_t ISRHandler);
1410
1411#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE
1417void ENET_SetTsISRHandler(ENET_Type *base, enet_isr_t ISRHandler);
1418
1424void ENET_Set1588TimerISRHandler(ENET_Type *base, enet_isr_t ISRHandler);
1425#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */
1426
1427/* @} */
1428
1444void ENET_SetCallback(enet_handle_t *handle, enet_callback_t callback, void *userData);
1445
1467void ENET_GetRxErrBeforeReadFrame(enet_handle_t *handle, enet_data_error_stats_t *eErrorStatic, uint8_t ringId);
1468
1469#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE
1484status_t ENET_GetTxErrAfterSendFrame(enet_handle_t *handle, enet_data_error_stats_t *eErrorStatic, uint8_t ringId);
1485#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */
1486
1493void ENET_GetStatistics(ENET_Type *base, enet_transfer_stats_t *statistics);
1494
1512status_t ENET_GetRxFrameSize(enet_handle_t *handle, uint32_t *length, uint8_t ringId);
1513
1559 ENET_Type *base, enet_handle_t *handle, uint8_t *data, uint32_t length, uint8_t ringId, uint32_t *ts);
1560
1583 enet_handle_t *handle,
1584 const uint8_t *data,
1585 uint32_t length,
1586 uint8_t ringId,
1587 bool tsFlag,
1588 void *context);
1589
1601status_t ENET_SetTxReclaim(enet_handle_t *handle, bool isEnable, uint8_t ringId);
1602
1614void ENET_ReclaimTxDescriptor(ENET_Type *base, enet_handle_t *handle, uint8_t ringId);
1615
1652 enet_handle_t *handle,
1653 void **buffer,
1654 uint32_t *length,
1655 uint8_t ringId,
1656 bool *isLastBuff,
1657 uint32_t *ts);
1658
1674void ENET_ReleaseRxBuffer(ENET_Type *base, enet_handle_t *handle, void *buffer, uint8_t ringId);
1675
1697status_t ENET_GetRxFrame(ENET_Type *base, enet_handle_t *handle, enet_rx_frame_struct_t *rxFrame, uint8_t ringId);
1698
1714status_t ENET_StartTxFrame(ENET_Type *base, enet_handle_t *handle, enet_tx_frame_struct_t *txFrame, uint8_t ringId);
1715
1739 enet_handle_t *handle,
1740 const uint8_t *data,
1741 uint32_t length,
1742 uint8_t ringId,
1743 bool tsFlag,
1744 void *context);
1745
1746#if FSL_FEATURE_ENET_QUEUE > 1
1754void ENET_TransmitIRQHandler(ENET_Type *base, enet_handle_t *handle, uint32_t ringId);
1755
1763void ENET_ReceiveIRQHandler(ENET_Type *base, enet_handle_t *handle, uint32_t ringId);
1764
1772void ENET_CommonFrame1IRQHandler(ENET_Type *base);
1773
1781void ENET_CommonFrame2IRQHandler(ENET_Type *base);
1782#else
1790
1798#endif /* FSL_FEATURE_ENET_QUEUE > 1 */
1799
1806void ENET_ErrorIRQHandler(ENET_Type *base, enet_handle_t *handle);
1807
1816
1825/* @} */
1826
1827#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE
1832void ENET_Ptp1588ConfigureHandler(ENET_Type *base, enet_handle_t *handle, enet_ptp_config_t *ptpConfig);
1833
1850void ENET_Ptp1588Configure(ENET_Type *base, enet_handle_t *handle, enet_ptp_config_t *ptpConfig);
1851
1860void ENET_Ptp1588StartTimer(ENET_Type *base, uint32_t ptpClkSrc);
1861
1868static inline void ENET_Ptp1588StopTimer(ENET_Type *base)
1869{
1870 /* Disable PTP timer and reset the timer. */
1871 base->ATCR &= ~ENET_ATCR_EN_MASK;
1872 base->ATCR |= ENET_ATCR_RESTART_MASK;
1873}
1874
1886void ENET_Ptp1588AdjustTimer(ENET_Type *base, uint32_t corrIncrease, uint32_t corrPeriod);
1887
1896static inline void ENET_Ptp1588SetChannelMode(ENET_Type *base,
1897 enet_ptp_timer_channel_t channel,
1898 enet_ptp_timer_channel_mode_t mode,
1899 bool intEnable)
1900{
1901 uint32_t tcrReg = 0;
1902
1903 tcrReg = ENET_TCSR_TMODE(mode) | (intEnable ? ENET_TCSR_TIE_MASK : 0U);
1904
1905 /* Disable channel mode first. */
1906 base->CHANNEL[channel].TCSR = 0;
1907 base->CHANNEL[channel].TCSR = tcrReg;
1908}
1909
1910#if defined(FSL_FEATURE_ENET_HAS_TIMER_PWCONTROL) && FSL_FEATURE_ENET_HAS_TIMER_PWCONTROL
1932static inline void ENET_Ptp1588SetChannelOutputPulseWidth(
1933 ENET_Type *base, enet_ptp_timer_channel_t channel, bool isOutputLow, uint8_t pulseWidth, bool intEnable)
1934{
1935 uint32_t tcrReg;
1936
1937 tcrReg = ENET_TCSR_TIE(intEnable) | ENET_TCSR_TPWC(pulseWidth);
1938
1939 if (isOutputLow)
1940 {
1941 tcrReg |= ENET_TCSR_TMODE(kENET_PtpChannelPulseLowonCompare);
1942 }
1943 else
1944 {
1945 tcrReg |= ENET_TCSR_TMODE(kENET_PtpChannelPulseHighonCompare);
1946 }
1947
1948 /* Disable channel mode first. */
1949 base->CHANNEL[channel].TCSR = 0;
1950 base->CHANNEL[channel].TCSR = tcrReg;
1951}
1952#endif /* FSL_FEATURE_ENET_HAS_TIMER_PWCONTROL */
1953
1961static inline void ENET_Ptp1588SetChannelCmpValue(ENET_Type *base, enet_ptp_timer_channel_t channel, uint32_t cmpValue)
1962{
1963 base->CHANNEL[channel].TCCR = cmpValue;
1964}
1965
1973static inline bool ENET_Ptp1588GetChannelStatus(ENET_Type *base, enet_ptp_timer_channel_t channel)
1974{
1975 return (0U != (base->CHANNEL[channel].TCSR & ENET_TCSR_TF_MASK));
1976}
1977
1984static inline void ENET_Ptp1588ClearChannelStatus(ENET_Type *base, enet_ptp_timer_channel_t channel)
1985{
1986 base->CHANNEL[channel].TCSR |= ENET_TCSR_TF_MASK;
1987 base->TGSR = (1UL << (uint32_t)channel);
1988}
1989
1995static inline uint32_t ENET_Ptp1588GetGlobalStatus(ENET_Type *base)
1996{
1997 return base->TGSR;
1998}
1999
2008void ENET_Ptp1588GetTimerNoIrqDisable(ENET_Type *base, enet_handle_t *handle, enet_ptp_time_t *ptpTime);
2009
2017void ENET_Ptp1588GetTimer(ENET_Type *base, enet_handle_t *handle, enet_ptp_time_t *ptpTime);
2018
2026void ENET_Ptp1588SetTimer(ENET_Type *base, enet_handle_t *handle, enet_ptp_time_t *ptpTime);
2027
2034void ENET_TimeStampIRQHandler(ENET_Type *base, enet_handle_t *handle);
2035
2036/* @} */
2037
2038#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */
2039
2040#if defined(__cplusplus)
2041}
2042#endif
2043
2046#endif /* _FSL_ENET_H_ */
#define ENET_TCSR_TIE(x)
Definition: MIMXRT1052.h:20304
#define ENET_TCSR_TMODE(x)
Definition: MIMXRT1052.h:20296
#define ENET_MMFR_ST(x)
Definition: MIMXRT1052.h:18980
#define ENET_MMFR_RA(x)
Definition: MIMXRT1052.h:18962
#define ENET_MMFR_DATA(x)
Definition: MIMXRT1052.h:18950
#define ENET_MMFR_PA(x)
Definition: MIMXRT1052.h:18968
#define ENET_MMFR_OP(x)
Definition: MIMXRT1052.h:18974
#define ENET_TCSR_TPWC(x)
Definition: MIMXRT1052.h:20323
#define ENET_MMFR_TA(x)
Definition: MIMXRT1052.h:18956
enum _clock_ip_name clock_ip_name_t
CCM CCGR gate control for each module independently.
struct _enet_config enet_config_t
Defines the basic configuration structure for the ENET device.
void ENET_ReleaseRxBuffer(ENET_Type *base, enet_handle_t *handle, void *buffer, uint8_t ringId)
Release receive buffer descriptor to DMA.
Definition: fsl_enet.c:2252
enet_rx_free_callback_t rxBuffFree
Definition: fsl_enet.h:673
enet_callback_t callback
Definition: fsl_enet.h:706
uint32_t statsTxFifoUnderRunErr
Definition: fsl_enet.h:486
enet_tx_bd_ring_t txBdRing[FSL_FEATURE_ENET_QUEUE]
Definition: fsl_enet.h:700
uint16_t txRingLen
Definition: fsl_enet.h:531
bool txMaintainEnable[FSL_FEATURE_ENET_QUEUE]
Definition: fsl_enet.h:704
void ENET_TransmitIRQHandler(ENET_Type *base, enet_handle_t *handle)
The transmit IRQ handler.
Definition: fsl_enet.c:3447
_enet_special_control_flag
Defines a special configuration for ENET MAC controller.
Definition: fsl_enet.h:237
struct _enet_data_error_stats enet_data_error_stats_t
Defines the ENET data error statistics structure.
_enet_mii_speed
Defines the 10/100/1000 Mbps speed for the MII data interface.
Definition: fsl_enet.h:185
uint16_t length
Definition: fsl_enet.h:387
status_t ENET_GetRxBuffer(ENET_Type *base, enet_handle_t *handle, void **buffer, uint32_t *length, uint8_t ringId, bool *isLastBuff, uint32_t *ts)
Get a receive buffer pointer of the ENET device for specified ring.
Definition: fsl_enet.c:2181
enet_tx_dirty_ring_t txDirtyRing[FSL_FEATURE_ENET_QUEUE]
Definition: fsl_enet.h:708
uint32_t statsTxCrcAlignErr
Definition: fsl_enet.h:485
uint32_t txBuffNum
Definition: fsl_enet.h:763
uint16_t txBuffSizeAlign[FSL_FEATURE_ENET_QUEUE]
Definition: fsl_enet.h:702
uint8_t ringNum
Definition: fsl_enet.h:671
uint32_t statsRxLenGreaterErr
Definition: fsl_enet.h:435
enum _enet_event enet_event_t
Defines the common interrupt event for callback use.
uint16_t txConsumIdx
Definition: fsl_enet.h:530
bool rxMaintainEnable
Definition: fsl_enet.h:568
void ENET_LeaveMulticastGroup(ENET_Type *base, uint8_t *address)
Moves the ENET device from a multicast group.
Definition: fsl_enet.c:3044
uint32_t statsTxFrameOk
Definition: fsl_enet.h:484
_enet_mii_mode
Defines the MII/RMII/RGMII mode for data interface between the MAC and the PHY.
Definition: fsl_enet.h:172
uint16_t txGenIdx
Definition: fsl_enet.h:529
uint32_t statsRxAlignErr
Definition: fsl_enet.h:480
_enet_event
Defines the common interrupt event for callback use.
Definition: fsl_enet.h:294
const clock_ip_name_t s_enetClock[]
Pointers to enet clocks for each instance.
Definition: fsl_enet.c:46
uint16_t length
Definition: fsl_enet.h:727
bool isFull
Definition: fsl_enet.h:532
enet_mii_duplex_t miiDuplex
Definition: fsl_enet.h:652
enet_rx_frame_attribute_t rxAttribute
Definition: fsl_enet.h:742
volatile enet_tx_bd_struct_t * txBdStartAddrAlign
Definition: fsl_enet.h:565
struct _enet_rx_bd_struct enet_rx_bd_struct_t
Defines the receive buffer descriptor structure for the little endian system.
uint16_t totLen
Definition: fsl_enet.h:741
uint16_t control
Definition: fsl_enet.h:388
void ENET_Ptp1588IRQHandler(ENET_Type *base)
the common IRQ handler for the 1588 irq handler.
Definition: fsl_enet.c:3751
status_t ENET_SendFrame(ENET_Type *base, enet_handle_t *handle, const uint8_t *data, uint32_t length, uint8_t ringId, bool tsFlag, void *context)
Transmits an ENET frame for specified ring.
Definition: fsl_enet.c:1866
uint8_t * txBufferAlign
Definition: fsl_enet.h:567
uint32_t interrupt
Definition: fsl_enet.h:648
enet_rx_bd_ring_t rxBdRing[FSL_FEATURE_ENET_QUEUE]
Definition: fsl_enet.h:699
uint32_t statsRxFrameCount
Definition: fsl_enet.h:477
uint16_t rxRingLen
Definition: fsl_enet.h:693
struct _enet_tx_dirty_ring enet_tx_dirty_ring_t
Defines the ENET transmit dirty addresses ring/queue structure.
void ENET_SetSMI(ENET_Type *base, uint32_t srcClock_Hz, bool isPreambleDisabled)
Sets the ENET SMI(serial management interface)- MII management interface.
Definition: fsl_enet.c:1250
_enet_interrupt_enable
List of interrupts supported by the peripheral. This enumeration uses one-bit encoding to allow a log...
Definition: fsl_enet.h:260
enum _enet_mii_speed enet_mii_speed_t
Defines the 10/100/1000 Mbps speed for the MII data interface.
uint32_t buffer
Definition: fsl_enet.h:411
uint32_t ENET_GetInstance(ENET_Type *base)
Get the ENET instance from peripheral base address.
Definition: fsl_enet.c:174
status_t ENET_Up(ENET_Type *base, enet_handle_t *handle, const enet_config_t *config, const enet_buffer_config_t *bufferConfig, uint8_t *macAddr, uint32_t srcClock_Hz)
Initializes the ENET module.
Definition: fsl_enet.c:257
uint32_t statsRxAlignErr
Definition: fsl_enet.h:436
uint16_t pauseDuration
Definition: fsl_enet.h:655
void * userData
Definition: fsl_enet.h:675
uint32_t statsRxCrcErr
Definition: fsl_enet.h:479
void ENET_AddMulticastGroup(ENET_Type *base, uint8_t *address)
Adds the ENET device to a multicast group.
Definition: fsl_enet.c:2991
uint32_t statsTxFrameCount
Definition: fsl_enet.h:483
enum _enet_mii_write enet_mii_write_t
Define the MII opcode for normal MDIO_CLAUSES_22 Frame.
volatile uint16_t txDescUsed
Definition: fsl_enet.h:684
enum _enet_mii_duplex enet_mii_duplex_t
Defines the half or full duplex for the MII data interface.
enet_frame_info_t * txDirtyBase
Definition: fsl_enet.h:528
_enet_mii_read
Defines the read operation for the MII management frame.
Definition: fsl_enet.h:209
uint32_t statsRxFcsErr
Definition: fsl_enet.h:437
void ENET_ErrorIRQHandler(ENET_Type *base, enet_handle_t *handle)
Some special IRQ handler including the error, mii, wakeup irq handler.
Definition: fsl_enet.c:3552
uint8_t txAccelerConfig
Definition: fsl_enet.h:654
enet_rx_free_callback_t rxBuffFree
Definition: fsl_enet.h:711
void(* enet_callback_t)(ENET_Type *base, enet_handle_t *handle, enet_event_t event, enet_frame_info_t *frameInfo, void *userData)
ENET callback function.
Definition: fsl_enet.h:606
uint8_t * rxBufferAlign
Definition: fsl_enet.h:566
bool rxMaintainEnable[FSL_FEATURE_ENET_QUEUE]
Definition: fsl_enet.h:703
uint8_t rxFifoFullThreshold
Definition: fsl_enet.h:663
uint8_t rxAccelerConfig
Definition: fsl_enet.h:653
void ENET_Deinit(ENET_Type *base)
Deinitializes the ENET module.
Definition: fsl_enet.c:378
void * context
Definition: fsl_enet.h:518
enet_callback_t callback
Definition: fsl_enet.h:674
enet_frame_info_t * txFrameInfo
Definition: fsl_enet.h:570
uint8_t txFifoWatermark
Definition: fsl_enet.h:665
uint16_t control
Definition: fsl_enet.h:410
uint32_t statsRxFifoOverflowErr
Definition: fsl_enet.h:482
enet_mii_mode_t miiMode
Definition: fsl_enet.h:650
enum _enet_tx_accelerator enet_tx_accelerator_t
Defines the transmit accelerator configuration.
void(* enet_rx_free_callback_t)(ENET_Type *base, void *buffer, void *userData, uint8_t ringId)
Defines the ENET Rx memory buffer free function pointer.
Definition: fsl_enet.h:539
void ENET_SetTxISRHandler(ENET_Type *base, enet_isr_t ISRHandler)
Set the second level Tx IRQ handler.
Definition: fsl_enet.c:430
uint16_t txBuffSizeAlign
Definition: fsl_enet.h:561
void(* enet_isr_t)(ENET_Type *base, enet_handle_t *handle)
Define interrupt IRQ handler.
Definition: fsl_enet.h:774
struct _enet_rx_frame_error enet_rx_frame_error_t
Defines the Rx frame error structure.
bool statsRxTruncateErr
Definition: fsl_enet.h:459
status_t ENET_MDIORead(ENET_Type *base, uint8_t phyAddr, uint8_t regAddr, uint16_t *pData)
MDIO read with IEEE802.3 Clause 22 format.
Definition: fsl_enet.c:1341
_enet_tx_accelerator
Defines the transmit accelerator configuration.
Definition: fsl_enet.h:331
void ENET_GetMacAddr(ENET_Type *base, uint8_t *macAddr)
Gets the ENET module Mac address.
Definition: fsl_enet.c:1222
struct _enet_buffer_config enet_buffer_config_t
Defines the receive buffer descriptor configuration structure.
void ENET_SetMII(ENET_Type *base, enet_mii_speed_t speed, enet_mii_duplex_t duplex)
Sets the ENET MII speed and duplex.
Definition: fsl_enet.c:1146
void ENET_SetMacAddr(ENET_Type *base, uint8_t *macAddr)
Sets the ENET module Mac address.
Definition: fsl_enet.c:1202
uint16_t rxBuffSizeAlign
Definition: fsl_enet.h:560
void * buffer
Definition: fsl_enet.h:726
enum _enet_mii_mode enet_mii_mode_t
Defines the MII/RMII/RGMII mode for data interface between the MAC and the PHY.
uint16_t rxMaxFrameLen
Definition: fsl_enet.h:649
uint16_t txBdNumber
Definition: fsl_enet.h:559
uint16_t length
Definition: fsl_enet.h:409
volatile enet_rx_bd_struct_t * rxBdBase
Definition: fsl_enet.h:691
bool statsRxOverRunErr
Definition: fsl_enet.h:460
void ENET_ReceiveIRQHandler(ENET_Type *base, enet_handle_t *handle)
The receive IRQ handler.
Definition: fsl_enet.c:3507
uint8_t ringNum
Definition: fsl_enet.h:705
struct enet_frame_info enet_frame_info_t
Defines the frame info structure.
struct _enet_tx_bd_ring enet_tx_bd_ring_t
Defines the ENET transmit buffer descriptor ring/queue structure.
void ENET_CommonFrame0IRQHandler(ENET_Type *base)
the common IRQ handler for the tx/rx/error etc irq handler.
Definition: fsl_enet.c:3649
void ENET_SetErrISRHandler(ENET_Type *base, enet_isr_t ISRHandler)
Set the second level Err IRQ handler.
Definition: fsl_enet.c:439
bool txMaintainEnable
Definition: fsl_enet.h:569
enet_buffer_struct_t * rxBuffArray
Definition: fsl_enet.h:740
status_t ENET_SetTxReclaim(enet_handle_t *handle, bool isEnable, uint8_t ringId)
Enable or disable tx descriptors reclaim mechanism.
Definition: fsl_enet.c:2084
status_t ENET_GetRxFrame(ENET_Type *base, enet_handle_t *handle, enet_rx_frame_struct_t *rxFrame, uint8_t ringId)
Receives one frame in specified BD ring with zero copy.
Definition: fsl_enet.c:2416
void ENET_GetStatistics(ENET_Type *base, enet_transfer_stats_t *statistics)
Gets statistical data in transfer.
Definition: fsl_enet.c:1565
bool txReclaimEnable[FSL_FEATURE_ENET_QUEUE]
Definition: fsl_enet.h:709
uint16_t txRingLen
Definition: fsl_enet.h:685
volatile enet_rx_bd_struct_t * rxBdStartAddrAlign
Definition: fsl_enet.h:563
bool statsRxLenGreaterErr
Definition: fsl_enet.h:464
status_t ENET_GetRxFrameSize(enet_handle_t *handle, uint32_t *length, uint8_t ringId)
Gets the size of the read frame for specified ring.
Definition: fsl_enet.c:1599
uint32_t statsRxOverRunErr
Definition: fsl_enet.h:438
uint32_t statsRxDropInvalidSFD
Definition: fsl_enet.h:481
void *(* enet_rx_alloc_callback_t)(ENET_Type *base, void *userData, uint8_t ringId)
Defines the ENET Rx memory buffer alloc function pointer.
Definition: fsl_enet.h:536
status_t ENET_ReadFrame(ENET_Type *base, enet_handle_t *handle, uint8_t *data, uint32_t length, uint8_t ringId, uint32_t *ts)
Reads a frame from the ENET device. This function reads a frame (both the data and the length) from t...
Definition: fsl_enet.c:1716
bool promiscuous
Definition: fsl_enet.h:732
_enet_mii_write
Define the MII opcode for normal MDIO_CLAUSES_22 Frame.
Definition: fsl_enet.h:202
void ENET_Down(ENET_Type *base)
Stops the ENET module.
Definition: fsl_enet.c:354
void * userData
Definition: fsl_enet.h:707
status_t ENET_SendFrameZeroCopy(ENET_Type *base, enet_handle_t *handle, const uint8_t *data, uint32_t length, uint8_t ringId, bool tsFlag, void *context)
Transmits an ENET frame for specified ring with zero-copy.
Definition: fsl_enet.c:2803
struct _enet_rx_bd_ring enet_rx_bd_ring_t
Defines the ENET receive buffer descriptor ring/queue structure.
enum _enet_rx_accelerator enet_rx_accelerator_t
Defines the receive accelerator configuration.
void ENET_ReclaimTxDescriptor(ENET_Type *base, enet_handle_t *handle, uint8_t ringId)
Reclaim tx descriptors. This function is used to update the tx descriptor status and store the tx tim...
Definition: fsl_enet.c:2125
enet_rx_frame_error_t rxFrameError
Definition: fsl_enet.h:743
struct _enet_tx_bd_struct enet_tx_bd_struct_t
Defines the enhanced transmit buffer descriptor structure for the little endian system.
void ENET_SetRxISRHandler(ENET_Type *base, enet_isr_t ISRHandler)
Set the second level Rx IRQ handler.
Definition: fsl_enet.c:422
enet_rx_alloc_callback_t rxBuffAlloc
Definition: fsl_enet.h:672
_enet_rx_accelerator
Defines the receive accelerator configuration.
Definition: fsl_enet.h:339
#define FSL_FEATURE_ENET_QUEUE
Defines the queue number.
Definition: fsl_enet.h:34
_enet_mii_duplex
Defines the half or full duplex for the MII data interface.
Definition: fsl_enet.h:195
status_t ENET_MDIOWrite(ENET_Type *base, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
MDIO write with IEEE802.3 Clause 22 format.
Definition: fsl_enet.c:1309
uint16_t rxBuffSizeAlign[FSL_FEATURE_ENET_QUEUE]
Definition: fsl_enet.h:701
void * context
Definition: fsl_enet.h:767
uint8_t multicastCount[64]
Definition: fsl_enet.h:717
enet_mii_speed_t miiSpeed
Definition: fsl_enet.h:651
uint32_t buffer
Definition: fsl_enet.h:389
enet_buffer_struct_t * txBuffArray
Definition: fsl_enet.h:762
struct _enet_transfer_stats enet_transfer_stats_t
Defines the ENET transfer statistics structure.
void ENET_SetCallback(enet_handle_t *handle, enet_callback_t callback, void *userData)
Sets the callback function.
Definition: fsl_enet.c:396
enum _enet_interrupt_enable enet_interrupt_enable_t
List of interrupts supported by the peripheral. This enumeration uses one-bit encoding to allow a log...
void ENET_GetRxErrBeforeReadFrame(enet_handle_t *handle, enet_data_error_stats_t *eErrorStatic, uint8_t ringId)
Gets the error statistics of a received frame for ENET specified ring.
Definition: fsl_enet.c:1482
uint32_t macSpecialConfig
Definition: fsl_enet.h:647
uint32_t statsRxFrameOk
Definition: fsl_enet.h:478
uint16_t txConsumIdx
Definition: fsl_enet.h:683
enum _enet_special_control_flag enet_special_control_flag_t
Defines a special configuration for ENET MAC controller.
enum _enet_mii_read enet_mii_read_t
Defines the read operation for the MII management frame.
void ENET_GetDefaultConfig(enet_config_t *config)
Gets the ENET default configuration structure.
Definition: fsl_enet.c:206
status_t ENET_Init(ENET_Type *base, enet_handle_t *handle, const enet_config_t *config, const enet_buffer_config_t *bufferConfig, uint8_t *macAddr, uint32_t srcClock_Hz)
Initializes the ENET module.
Definition: fsl_enet.c:323
status_t ENET_StartTxFrame(ENET_Type *base, enet_handle_t *handle, enet_tx_frame_struct_t *txFrame, uint8_t ringId)
Sends one frame in specified BD ring with zero copy.
Definition: fsl_enet.c:2666
volatile enet_tx_bd_struct_t * txBdBase
Definition: fsl_enet.h:681
enet_rx_alloc_callback_t rxBuffAlloc
Definition: fsl_enet.h:710
bool statsRxAlignErr
Definition: fsl_enet.h:463
uint8_t rxFifoEmptyThreshold
Definition: fsl_enet.h:656
uint16_t txGenIdx
Definition: fsl_enet.h:682
bool statsRxFcsErr
Definition: fsl_enet.h:461
uint16_t rxGenIdx
Definition: fsl_enet.h:692
uint32_t statsRxTruncateErr
Definition: fsl_enet.h:439
uint16_t rxBdNumber
Definition: fsl_enet.h:558
@ kENET_ControlFlowControlEnable
Definition: fsl_enet.h:238
@ kENET_ControlVLANTagEnable
Definition: fsl_enet.h:247
@ kENET_ControlPromiscuousEnable
Definition: fsl_enet.h:245
@ kENET_ControlMIILoopEnable
Definition: fsl_enet.h:246
@ kENET_ControlSMIPreambleDisable
Definition: fsl_enet.h:244
@ kENET_ControlRxPayloadCheckEnable
Definition: fsl_enet.h:239
@ kENET_ControlRxPadRemoveEnable
Definition: fsl_enet.h:240
@ kENET_ControlStoreAndFwdDisable
Definition: fsl_enet.h:243
@ kENET_ControlMacAddrInsert
Definition: fsl_enet.h:242
@ kENET_ControlRxBroadCastRejectEnable
Definition: fsl_enet.h:241
@ kENET_MiiSpeed100M
Definition: fsl_enet.h:187
@ kENET_MiiSpeed10M
Definition: fsl_enet.h:186
@ kENET_MiiMode
Definition: fsl_enet.h:173
@ kENET_RmiiMode
Definition: fsl_enet.h:174
@ kENET_RxEvent
Definition: fsl_enet.h:295
@ kENET_ErrEvent
Definition: fsl_enet.h:297
@ kENET_TimeStampEvent
Definition: fsl_enet.h:299
@ kENET_TimeStampAvailEvent
Definition: fsl_enet.h:300
@ kENET_WakeUpEvent
Definition: fsl_enet.h:298
@ kENET_TxEvent
Definition: fsl_enet.h:296
@ kENET_BabtInterrupt
Definition: fsl_enet.h:262
@ kENET_LateCollisionInterrupt
Definition: fsl_enet.h:270
@ kENET_GraceStopInterrupt
Definition: fsl_enet.h:263
@ kENET_UnderrunInterrupt
Definition: fsl_enet.h:272
@ kENET_WakeupInterrupt
Definition: fsl_enet.h:274
@ kENET_BabrInterrupt
Definition: fsl_enet.h:261
@ kENET_RxFrameInterrupt
Definition: fsl_enet.h:266
@ kENET_RetryLimitInterrupt
Definition: fsl_enet.h:271
@ kENET_TxFrameInterrupt
Definition: fsl_enet.h:264
@ kENET_TsTimerInterrupt
Definition: fsl_enet.h:289
@ kENET_TsAvailInterrupt
Definition: fsl_enet.h:288
@ kENET_TxBufferInterrupt
Definition: fsl_enet.h:265
@ kENET_EBusERInterrupt
Definition: fsl_enet.h:269
@ kENET_PayloadRxInterrupt
Definition: fsl_enet.h:273
@ kENET_MiiInterrupt
Definition: fsl_enet.h:268
@ kENET_RxBufferInterrupt
Definition: fsl_enet.h:267
@ kStatus_ENET_TxFrameFail
Definition: fsl_enet.h:167
@ kStatus_ENET_RxFrameEmpty
Definition: fsl_enet.h:163
@ kStatus_ENET_RxFrameDrop
Definition: fsl_enet.h:164
@ kStatus_ENET_InitMemoryFail
Definition: fsl_enet.h:159
@ kStatus_ENET_RxFrameFail
Definition: fsl_enet.h:162
@ kStatus_ENET_TxFrameBusy
Definition: fsl_enet.h:166
@ kStatus_ENET_RxFrameError
Definition: fsl_enet.h:161
@ kStatus_ENET_TxFrameOverLen
Definition: fsl_enet.h:165
@ kENET_MiiReadValidFrame
Definition: fsl_enet.h:210
@ kENET_MiiReadNoCompliant
Definition: fsl_enet.h:211
@ kENET_TxAccelIsShift16Enabled
Definition: fsl_enet.h:332
@ kENET_TxAccelProtoCheckEnabled
Definition: fsl_enet.h:334
@ kENET_TxAccelIpCheckEnabled
Definition: fsl_enet.h:333
@ kENET_MiiWriteValidFrame
Definition: fsl_enet.h:204
@ kENET_MiiWriteNoCompliant
Definition: fsl_enet.h:203
@ kENET_RxAccelProtoCheckEnabled
Definition: fsl_enet.h:342
@ kENET_RxAccelMacCheckEnabled
Definition: fsl_enet.h:343
@ kENET_RxAccelIpCheckEnabled
Definition: fsl_enet.h:341
@ kENET_RxAccelPadRemoveEnabled
Definition: fsl_enet.h:340
@ kENET_RxAccelisShift16Enabled
Definition: fsl_enet.h:344
@ kENET_MiiFullDuplex
Definition: fsl_enet.h:197
@ kENET_MiiHalfDuplex
Definition: fsl_enet.h:196
int32_t status_t
Type used for all status and error return values.
Definition: fsl_common.h:225
#define MAKE_STATUS(group, code)
Construct a status code value from a group and code number.
Definition: fsl_common.h:47
@ kStatusGroup_ENET
Definition: fsl_common.h:116
rtems_termios_device_context * context
Definition: console-config.c:62
Definition: MIMXRT1052.h:18504
Defines the receive buffer descriptor configuration structure.
Definition: fsl_enet.h:557
Definition: fsl_enet.h:725
Defines the basic configuration structure for the ENET device.
Definition: fsl_enet.h:646
Defines the ENET data error statistics structure.
Definition: fsl_enet.h:434
Defines the ENET handler structure.
Definition: fsl_enet.h:698
Defines the ENET receive buffer descriptor ring/queue structure.
Definition: fsl_enet.h:690
Defines the receive buffer descriptor structure for the little endian system.
Definition: fsl_enet.h:386
Definition: fsl_enet.h:731
Defines the Rx frame error structure.
Definition: fsl_enet.h:458
Definition: fsl_enet.h:739
Defines the ENET transfer statistics structure.
Definition: fsl_enet.h:476
Defines the ENET transmit buffer descriptor ring/queue structure.
Definition: fsl_enet.h:680
Defines the enhanced transmit buffer descriptor structure for the little endian system.
Definition: fsl_enet.h:408
Defines the ENET transmit dirty addresses ring/queue structure.
Definition: fsl_enet.h:527
Definition: fsl_enet.h:761
Definition: deflate.c:114
Defines the frame info structure.
Definition: fsl_enet.h:517