fsl_dac12.h

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/*
 * Copyright (c) 2016, Freescale Semiconductor, Inc.
 * Copyright 2016-2021 NXP
 * All rights reserved.
 *
 * SPDX-License-Identifier: BSD-3-Clause
 */
 
#ifndef _FSL_DAC12_H_
#define _FSL_DAC12_H_
 
#include "fsl_common.h"
 
/*******************************************************************************
 * Definitions
 ******************************************************************************/
 
#define FSL_DAC12_DRIVER_VERSION (MAKE_VERSION(2, 1, 0))
#define DAC12_CR_W1C_FLAGS_MASK (DAC_CR_OVFF_MASK | DAC_CR_UDFF_MASK)
#define DAC12_CR_ALL_FLAGS_MASK (DAC12_CR_W1C_FLAGS_MASK | DAC_CR_WMF_MASK | DAC_CR_NEMPTF_MASK | DAC_CR_FULLF_MASK)
 
enum _dac12_status_flags
{
    kDAC12_OverflowFlag = DAC_CR_OVFF_MASK,  
    kDAC12_UnderflowFlag = DAC_CR_UDFF_MASK, 
    kDAC12_WatermarkFlag = DAC_CR_WMF_MASK, 
    kDAC12_NearlyEmptyFlag = DAC_CR_NEMPTF_MASK, 
    kDAC12_FullFlag = DAC_CR_FULLF_MASK 
};
 
enum _dac12_interrupt_enable
{
    kDAC12_UnderOrOverflowInterruptEnable = DAC_CR_UVIE_MASK,   
    kDAC12_WatermarkInterruptEnable       = DAC_CR_WTMIE_MASK,  
    kDAC12_NearlyEmptyInterruptEnable     = DAC_CR_EMPTIE_MASK, 
    kDAC12_FullInterruptEnable            = DAC_CR_FULLIE_MASK  
};
 
typedef enum _dac12_fifo_size_info
{
    kDAC12_FIFOSize2   = 0U, 
    kDAC12_FIFOSize4   = 1U, 
    kDAC12_FIFOSize8   = 2U, 
    kDAC12_FIFOSize16  = 3U, 
    kDAC12_FIFOSize32  = 4U, 
    kDAC12_FIFOSize64  = 5U, 
    kDAC12_FIFOSize128 = 6U, 
    kDAC12_FIFOSize256 = 7U, 
} dac12_fifo_size_info_t;
 
typedef enum _dac12_fifo_work_mode
{
    kDAC12_FIFODisabled = 0U, 
    kDAC12_FIFOWorkAsNormalMode = 1U, 
    kDAC12_FIFOWorkAsSwingMode  = 2U  
} dac12_fifo_work_mode_t;
 
typedef enum _dac12_reference_voltage_source
{
    kDAC12_ReferenceVoltageSourceAlt1 = 0U, 
    kDAC12_ReferenceVoltageSourceAlt2 = 1U, 
} dac12_reference_voltage_source_t;
 
typedef enum _dac12_fifo_trigger_mode
{
    kDAC12_FIFOTriggerByHardwareMode = 0U, 
    kDAC12_FIFOTriggerBySoftwareMode = 1U, 
} dac12_fifo_trigger_mode_t;
 
typedef enum _dac12_reference_current_source
{
    kDAC12_ReferenceCurrentSourceDisabled = 0U, 
    kDAC12_ReferenceCurrentSourceAlt0 = 1U, 
    kDAC12_ReferenceCurrentSourceAlt1 = 2U, 
    kDAC12_ReferenceCurrentSourceAlt2 = 3U, 
} dac12_reference_current_source_t;
 
typedef enum _dac12_speed_mode
{
    kDAC12_SpeedLowMode    = 0U, 
    kDAC12_SpeedMiddleMode = 1U, 
    kDAC12_SpeedHighMode   = 2U, 
} dac12_speed_mode_t;
 
typedef struct _dac12_hardware_info
{
    dac12_fifo_size_info_t fifoSizeInfo; 
} dac12_hardware_info_t;
 
typedef struct
{
    uint32_t fifoWatermarkLevel;         
    dac12_fifo_work_mode_t fifoWorkMode; 
    dac12_reference_voltage_source_t referenceVoltageSource; 
    dac12_fifo_trigger_mode_t fifoTriggerMode;               
    /* Analog part configuration. */
    dac12_reference_current_source_t referenceCurrentSource; 
    dac12_speed_mode_t speedMode;                            
    bool enableAnalogBuffer;                                 
#if !(defined(FSL_FEATURE_DAC12_HAS_NO_ITRM_REGISTER) && FSL_FEATURE_DAC12_HAS_NO_ITRM_REGISTER)
    uint32_t currentReferenceInternalTrimValue; 
#endif                                          /* FSL_FEATURE_DAC12_HAS_NO_ITRM_REGISTER */
} dac12_config_t;
 
/*******************************************************************************
 * API
 ******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif
 
void DAC12_GetHardwareInfo(DAC_Type *base, dac12_hardware_info_t *info);
 
void DAC12_Init(DAC_Type *base, const dac12_config_t *config);
 
void DAC12_GetDefaultConfig(dac12_config_t *config);
 
void DAC12_Deinit(DAC_Type *base);
 
static inline void DAC12_Enable(DAC_Type *base, bool enable)
{
    if (enable)
    {
        base->CR = (base->CR & ~DAC12_CR_W1C_FLAGS_MASK) | DAC_CR_DACEN_MASK;
    }
    else
    {
        base->CR &= ~DAC_CR_DACEN_MASK;
    }
}
 
static inline void DAC12_ResetConfig(DAC_Type *base)
{
    base->CR = DAC_CR_SWRST_MASK;
}
 
static inline void DAC12_ResetFIFO(DAC_Type *base)
{
    /* FIFO pointers should only be reset when the module is disabled. */
    base->CR = (base->CR & ~DAC12_CR_W1C_FLAGS_MASK) | DAC_CR_FIFORST_MASK;
}
 
/* @} */
 
static inline uint32_t DAC12_GetStatusFlags(DAC_Type *base)
{
    return (DAC12_CR_ALL_FLAGS_MASK & base->CR);
}
 
static inline void DAC12_ClearStatusFlags(DAC_Type *base, uint32_t flags)
{
    base->CR |= (flags & DAC12_CR_W1C_FLAGS_MASK);
}
 
/* @} */
 
static inline void DAC12_EnableInterrupts(DAC_Type *base, uint32_t mask)
{
    base->CR = (base->CR & ~DAC12_CR_W1C_FLAGS_MASK) | mask;
}
 
static inline void DAC12_DisableInterrupts(DAC_Type *base, uint32_t mask)
{
    base->CR &= ~mask;
}
 
/* @} */
 
static inline void DAC12_EnableDMA(DAC_Type *base, bool enable)
{
    if (enable)
    {
        base->CR = (base->CR & ~DAC12_CR_W1C_FLAGS_MASK) | DAC_CR_DMAEN_MASK;
    }
    else
    {
        base->CR &= ~DAC_CR_DMAEN_MASK;
    }
}
 
/* @} */
 
static inline void DAC12_SetData(DAC_Type *base, uint32_t value)
{
    /* The module is connected internally to a 32-bit interface.
     * For the 8-bit or 16-bit, the write might be ignored. */
    base->DATA = DAC_DATA_DATA0(value);
}
 
static inline void DAC12_DoSoftwareTrigger(DAC_Type *base)
{
    base->CR = (base->CR & ~DAC12_CR_W1C_FLAGS_MASK) | DAC_CR_SWTRG_MASK;
}
 
static inline uint32_t DAC12_GetFIFOReadPointer(DAC_Type *base)
{
    return (DAC_PTR_DACRFP_MASK & base->PTR) >> DAC_PTR_DACRFP_SHIFT;
}
 
static inline uint32_t DAC12_GetFIFOWritePointer(DAC_Type *base)
{
    return (DAC_PTR_DACWFP_MASK & base->PTR) >> DAC_PTR_DACWFP_SHIFT;
}
 
/* @} */
 
#if defined(__cplusplus)
}
#endif
#endif /* _FSL_DAC12_H_ */