69#pragma ANSI_strict off
123 uint32_t PBRIDGE_A_reserved0008[6];
142 uint32_t PBRIDGE_A_reserved0024[7];
239 uint32_t PBRIDGE_A_reserved0050[4076];
295 uint32_t PBRIDGE_B_reserved0008[6];
366 uint32_t PBRIDGE_B_reserved002C[5];
475 uint32_t PBRIDGE_B_reserved0050[4076];
485 uint32_t FMPLL_reserved0000;
487 union FMPLL_SYNSR_tag {
504 union FMPLL_ESYNCR1_tag {
516 union FMPLL_ESYNCR2_tag {
527 uint32_t CLKCFG_DIS:1;
535 uint32_t FMPLL_reserved0010[4092];
544 uint32_t ebi_cs_reserved [2];
595 uint32_t EBI_reserved0004;
619 uint32_t EBI_reserved0030[4];
624 uint32_t EBI_reserved0060[4000];
772 uint32_t FLASH_reserved0028[4086];
779 int32_t SIU_reserved0000 ;
787 uint32_t MAJOR_REV:4;
788 uint32_t MINOR_REV:4;
792 int32_t SIU_reserved0008;
848 union SIU_DIRER_tag {
874 union SIU_DIRSR_tag {
931 union SIU_IREER_tag {
934 uint32_t IREE_NMI8:1;
936 uint32_t IREE_NMI0:1;
957 union SIU_IFEER_tag {
960 uint32_t IFEE_NMI8:1;
962 uint32_t IFEE_NMI0:1;
1029 int32_t SIU_reserved0038[2];
1047 int16_t SIU_reserved0440[224];
1065 uint32_t SIU_reserved0900;
1095 uint32_t TRIGSELA:2;
1099 uint32_t TRIGSELB:2;
1103 uint32_t TRIGSELC:2;
1107 uint32_t TRIGSELD:2;
1111 int32_t SIU_reserved090C;
1117 uint32_t CTSEL5_0:7;
1119 uint32_t CTSEL4_0:7;
1121 uint32_t CTSEL3_0:7;
1123 uint32_t CTSEL2_0:7;
1131 uint32_t CTSEL1_0:7;
1133 uint32_t CTSEL0_0:7;
1142 uint32_t CTSEL5_1:7;
1144 uint32_t CTSEL4_1:7;
1146 uint32_t CTSEL3_1:7;
1148 uint32_t CTSEL2_1:7;
1156 uint32_t CTSEL1_1:7;
1158 uint32_t CTSEL0_1:7;
1218 int32_t SIU_reserved0920[20];
1271 int32_t SIU_reserved0998[2];
1277 uint32_t IPCLKDIV:2;
1280 uint32_t SYSCLKDIV:2;
1345 int32_t SIU_reserved09AC[21];
1347 int32_t SIU_reserved0A00[128];
1767 int32_t SIU_reserved0D20[8];
1834 uint32_t EMIOS0_0:1;
1835 uint32_t EMIOS1_1:1;
1836 uint32_t EMIOS2_2:1;
1837 uint32_t EMIOS3_3:1;
1838 uint32_t EMIOS4_4:1;
1839 uint32_t EMIOS5_5:1;
1840 uint32_t EMIOS6_6:1;
1841 uint32_t EMIOS7_7:1;
1858 uint32_t DSPIAH10:1;
1859 uint32_t DSPIAH11:1;
1860 uint32_t DSPIAH12:1;
1861 uint32_t DSPIAH13:1;
1862 uint32_t DSPIAH14:1;
1863 uint32_t DSPIAH15:1;
1864 uint32_t DSPIAL16:1;
1865 uint32_t DSPIAL17:1;
1866 uint32_t DSPIAL18:1;
1867 uint32_t DSPIAL19:1;
1868 uint32_t DSPIAL20:1;
1869 uint32_t DSPIAL21:1;
1870 uint32_t DSPIAL22:1;
1871 uint32_t DSPIAL23:1;
1872 uint32_t DSPIAL24:1;
1873 uint32_t DSPIAL25:1;
1874 uint32_t DSPIAL26:1;
1875 uint32_t DSPIAL27:1;
1876 uint32_t DSPIAL28:1;
1877 uint32_t DSPIAL29:1;
1878 uint32_t DSPIAL30:1;
1879 uint32_t DSPIAL31:1;
1883 int32_t SIU_reserved0D4C;
1942 uint32_t EMIOS23_23:1;
1943 uint32_t EMIOS15_15:1;
1944 uint32_t EMIOS14_14:1;
1945 uint32_t EMIOS13_13:1;
1946 uint32_t EMIOS12_12:1;
1947 uint32_t EMIOS11_11:1;
1948 uint32_t EMIOS10_10:1;
1949 uint32_t EMIOS9_9:1;
1950 uint32_t EMIOS8_8:1;
1951 uint32_t EMIOS6_6:1;
1952 uint32_t EMIOS5_5:1;
1953 uint32_t EMIOS4_4:1;
1954 uint32_t EMIOS3_3:1;
1955 uint32_t EMIOS2_2:1;
1956 uint32_t EMIOS1_1:1;
1957 uint32_t EMIOS0_0:1;
1974 uint32_t DSPIBH10:1;
1975 uint32_t DSPIBH11:1;
1976 uint32_t DSPIBH12:1;
1977 uint32_t DSPIBH13:1;
1978 uint32_t DSPIBH14:1;
1979 uint32_t DSPIBH15:1;
1980 uint32_t DSPIBL16:1;
1981 uint32_t DSPIBL17:1;
1982 uint32_t DSPIBL18:1;
1983 uint32_t DSPIBL19:1;
1984 uint32_t DSPIBL20:1;
1985 uint32_t DSPIBL21:1;
1986 uint32_t DSPIBL22:1;
1987 uint32_t DSPIBL23:1;
1988 uint32_t DSPIBL24:1;
1989 uint32_t DSPIBL25:1;
1990 uint32_t DSPIBL26:1;
1991 uint32_t DSPIBL27:1;
1992 uint32_t DSPIBL28:1;
1993 uint32_t DSPIBL29:1;
1994 uint32_t DSPIBL30:1;
1995 uint32_t DSPIBL31:1;
1999 int32_t SIU_reserved0D5C;
2058 uint32_t EMIOS23_23:1;
2090 uint32_t DSPICH10:1;
2091 uint32_t DSPICH11:1;
2092 uint32_t DSPICH12:1;
2093 uint32_t DSPICH13:1;
2094 uint32_t DSPICH14:1;
2095 uint32_t DSPICH15:1;
2096 uint32_t DSPICL16:1;
2097 uint32_t DSPICL17:1;
2098 uint32_t DSPICL18:1;
2099 uint32_t DSPICL19:1;
2100 uint32_t DSPICL20:1;
2101 uint32_t DSPICL21:1;
2102 uint32_t DSPICL22:1;
2103 uint32_t DSPICL23:1;
2104 uint32_t DSPICL24:1;
2105 uint32_t DSPICL25:1;
2106 uint32_t DSPICL26:1;
2107 uint32_t DSPICL27:1;
2108 uint32_t DSPICL28:1;
2109 uint32_t DSPICL29:1;
2110 uint32_t DSPICL30:1;
2111 uint32_t DSPICL31:1;
2115 int32_t SIU_reserved0D6C;
2156 int32_t SIU_reserved0D7C;
2158 int32_t SIU_reserved0D80[32];
2168 uint32_t SIU_reserved1000[3072];
2177 union EMIOS_MCR_tag {
2269 uint32_t eMIOS_reserved000C[5];
2271 struct EMIOS_CH_tag {
2284 union EMIOS_CCR_tag {
2308 union EMIOS_CSR_tag {
2325 uint32_t eMIOS_channel_reserved0018[2];
2329 uint32_t eMIOS_reserved0420[3832];
2366 uint32_t LVDATRIM:4;
2367 uint32_t LVDREGTRIM:4;
2368 uint32_t VDD33TRIM:4;
2369 uint32_t LVD33TRIM:4;
2370 uint32_t VDDCTRIM:4;
2371 uint32_t LVDCTRIM:4;
2383 uint32_t LVFCSTBY:1;
2402 uint32_t PMC_reserved000C[4093];
2428 uint32_t SCMMISEN:1;
2449 uint32_t eTPU_reserved0008;
2454 uint32_t ETPUMISCCMP:32;
2461 uint32_t ETPUSCMOFFDATA:32;
2507 uint32_t eTPU_reserved001C;
2546 uint32_t SERVER_ID1:4;
2552 uint32_t SERVER_ID2:4;
2558 uint32_t eTPU_reserved0030[4];
2597 uint32_t SERVER_ID1:4;
2603 uint32_t SERVER_ID2:4;
2609 uint32_t eTPU_reserved0050[4];
2620 uint32_t eTPU_reserved0064;
2625 uint32_t IDLE_CNT:31;
2631 uint32_t eTPU_reserved006C;
2642 uint32_t eTPU_reserved0074;
2647 uint32_t IDLE_CNT:31;
2652 uint32_t eTPU_reserved007C;
2654 uint32_t eTPU_reserved0080[96];
2734 uint32_t eTPU_reserved0208[2];
2812 uint32_t eTPU_reserved0218[2];
2890 uint32_t eTPU_reserved0228[2];
2968 uint32_t eTPU_reserved0238[2];
3046 uint32_t eTPU_reserved0248[2];
3124 uint32_t eTPU_reserved0258[2];
3202 uint32_t eTPU_reserved0268[6];
3280 uint32_t eTPU_reserved0288[2];
3358 uint32_t eTPU_reserved0298[2];
3360 uint32_t eTPU_reserved02A0[88];
3409 uint32_t eTPU_ch_reserved00C;
3413 uint32_t eTPU_reserved1000[7168];
3426 uint32_t MDIS_RTI:1;
3432 uint32_t PIT_reserved0004[59];
3494 uint32_t PIT_reserved00140[4016];
3525 uint32_t XBAR_reserved0004[3];
3540 uint32_t XBAR_reserved0014[59];
3564 uint32_t XBAR_reserved0104[3];
3579 uint32_t XBAR_reserved0114[59];
3603 uint32_t XBAR_reserved0204[3];
3618 uint32_t XBAR_reserved0214[59];
3620 uint32_t XBAR_reserved0300[64];
3622 uint32_t XBAR_reserved0400[64];
3624 uint32_t XBAR_reserved0500[64];
3648 uint32_t XBAR_reserved604[3];
3663 uint32_t XBAR_reserved0614[59];
3687 uint32_t XBAR_reserved704[3];
3702 uint32_t XBAR_reserved0714[59];
3704 uint32_t XBAR_reserved0800[3584];
3726 uint32_t MPU_reserved0004[3];
3748 uint32_t MPU_reserved0028[246];
3754 uint32_t SRTADDR:27;
3762 uint32_t ENDADDR:27;
3796 uint32_t MPU_reserved0500[192];
3819 uint32_t MPU_reserved0840[3568];
3899 uint32_t SWT_reserved001C[4089];
3924 uint32_t STM_reserved0008[2];
3947 uint32_t STM_reserved2[1];
3970 uint32_t STM_reserved3[1];
3993 uint32_t STM_reserved4[1];
4016 uint32_t STM_reserved0050[4076];
4034 uint32_t ECSM_reserved0004;
4040 uint8_t ECSM_reserved000C[3];
4052 uint8_t ECSM_reserved0010[51];
4066 uint8_t ECSM_reserved0044[3];
4080 uint16_t ECSM_reserved0048;
4096 uint32_t ECSM_reserved004C;
4105 uint16_t ECSM_reserved0054;
4148 uint16_t ECSM_reserved0064;
4184 uint32_t ECSM_reserved0070[4068];
4204 uint32_t INTC_reserved0004;
4214 uint32_t INTC_reserved000C;
4225 uint32_t INTC_reserved0014;
4234 uint32_t INTC_reserved001C;
4245 uint32_t INTC_reserved0028[6];
4255 uint16_t INTC_reserved0220[7920];
4278 uint32_t eQADC_reserved0004;
4303 uint32_t eQADC_reserved0028[2];
4313 uint32_t eQADC_reserved0048[2];
4329 uint32_t eQADC_reserved005C;
4331 union EQADC_IDCR_tag {
4350 uint32_t eQADC_reserved006C;
4370 uint32_t POPNXTPTR:4;
4374 uint32_t eQADC_reserved0088[2];
4384 uint32_t eQADC_reserved009C[1];
4397 uint32_t TC_LCFTCB0:11;
4412 uint32_t TC_LCFTCB1:11;
4428 uint32_t TC_LCFTSSI:11;
4445 uint32_t eQADC_reserved00B0;
4466 uint32_t eQADC_reserved00BC[17];
4472 uint32_t CFIFO_DATA:32;
4476 uint32_t eQADC_cf_reserved010[12];
4480 uint32_t eQADC_reserved0280[32];
4486 uint32_t RFIFO_DATA:32;
4490 uint32_t eQADC_rf_reserved010[12];
4494 uint32_t eQADC_reserved0480[3808];
4523 uint32_t DEC_RATE:4;
4540 uint32_t DEC_COUNTER:4;
4632 uint32_t DFILT_reserved0018[2];
4642 uint32_t DFILT_reserved0044[13];
4652 uint32_t DFILT_reserved0098[14];
4658 uint32_t SAMP_DATA:16;
4662 uint32_t DFILT_reserved00D4[459];
4676 uint32_t CONT_SCKE:1;
4702 uint32_t DSPI_reserved0004;
4747 uint32_t TXNXTPTR:4;
4749 uint32_t POPNXTPTR:4;
4762 uint32_t TFFFDIRS:1;
4767 uint32_t RFDFDIRS:1;
4808 uint32_t DSPI_reserved004C[12];
4818 uint32_t DSPI_reserved008C[12];
4849 uint32_t SER_DATA:32;
4856 uint32_t ASER_DATA:32;
4863 uint32_t COMP_DATA:32;
4870 uint32_t DESER_DATA:32;
4890 uint32_t DSPI_reserved00D4[4043];
4899 union ESCI_CR1_tag {
4923 union ESCI_CR2_tag {
5017 uint8_t eSCI_reserved0011[3];
5026 uint8_t eSCI_reserved0015[3];
5048 uint32_t eSCI_reserved001C;
5050 uint32_t eSCI_reserved0020[4088];
5079 uint32_t LPRIO_EN:1;
5115 int32_t FLEXCAN_reserved000C;
5417 uint32_t FLEXCAN_reserved0034[19];
5430 uint32_t TIMESTAMP:16;
5452 int32_t FLEXCAN_reserved0480[256];
5492 int32_t FLEXCAN_reserved0980[3488];
5500 typedef union uMVR {
5508 typedef union uMCR {
5519 uint16_t PRESCALE:3;
5550 uint16_t MBSEG2DS:7;
5552 uint16_t MBSEG1DS:7;
5560 uint16_t LAST_MB_SEG1:7;
5562 uint16_t LAST_MB_UTIL:7;
5566 typedef union uPOCR {
5709 typedef union uPSR0 {
5713 uint16_t SLOTMODE:2;
5715 uint16_t PROTSTATE:3;
5716 uint16_t SUBSTATE:4;
5718 uint16_t WAKEUPSTATUS:3;
5725 typedef union uPSR1 {
5738 typedef union uPSR2 {
5753 uint16_t CLKCORRFAILCNT:4;
5756 typedef union uPSR3 {
5819 uint16_t SYNFRID:10;
5846 uint16_t TI1CYCVAL:6;
5848 uint16_t TI1CYCMSK:6;
5853 typedef union uSSSR {
5860 uint16_t SLOTNUMBER:11;
5877 uint16_t STATUSMASK:4;
5880 typedef union uSSR {
5906 uint16_t CYCCNTMSK:6;
5908 uint16_t CYCCNTVAL:6;
5924 uint16_t FIFODEPTH:8;
5926 uint16_t ENTRYSIZE:7;
5956 typedef union uPCR0 {
5959 uint16_t ACTION_POINT_OFFSET:6;
5960 uint16_t STATIC_SLOT_LENGTH:10;
5964 typedef union uPCR1 {
5968 uint16_t MACRO_AFTER_FIRST_STATIC_SLOT:14;
5972 typedef union uPCR2 {
5975 uint16_t MINISLOT_AFTER_ACTION_POINT:6;
5976 uint16_t NUMBER_OF_STATIC_SLOTS:10;
5980 typedef union uPCR3 {
5983 uint16_t WAKEUP_SYMBOL_RX_LOW:6;
5984 uint16_t MINISLOT_ACTION_POINT_OFFSET:5;
5985 uint16_t COLDSTART_ATTEMPTS:5;
5989 typedef union uPCR4 {
5992 uint16_t CAS_RX_LOW_MAX:7;
5993 uint16_t WAKEUP_SYMBOL_RX_WINDOW:9;
5997 typedef union uPCR5 {
6000 uint16_t TSS_TRANSMITTER:4;
6001 uint16_t WAKEUP_SYMBOL_TX_LOW:6;
6002 uint16_t WAKEUP_SYMBOL_RX_IDLE:6;
6006 typedef union uPCR6 {
6010 uint16_t SYMBOL_WINDOW_AFTER_ACTION_POINT:8;
6011 uint16_t MACRO_INITIAL_OFFSET_A:7;
6015 typedef union uPCR7 {
6018 uint16_t DECODING_CORRECTION_B:9;
6019 uint16_t MICRO_PER_MACRO_NOM_HALF:7;
6023 typedef union uPCR8 {
6026 uint16_t MAX_WITHOUT_CLOCK_CORRECTION_FATAL:4;
6027 uint16_t MAX_WITHOUT_CLOCK_CORRECTION_PASSIVE:4;
6028 uint16_t WAKEUP_SYMBOL_TX_IDLE:8;
6032 typedef union uPCR9 {
6035 uint16_t MINISLOT_EXISTS:1;
6036 uint16_t SYMBOL_WINDOW_EXISTS:1;
6037 uint16_t OFFSET_CORRECTION_OUT:14;
6044 uint16_t SINGLE_SLOT_ENABLED:1;
6045 uint16_t WAKEUP_CHANNEL:1;
6046 uint16_t MACRO_PER_CYCLE:14;
6053 uint16_t KEY_SLOT_USED_FOR_STARTUP:1;
6054 uint16_t KEY_SLOT_USED_FOR_SYNC:1;
6055 uint16_t OFFSET_CORRECTION_START:14;
6062 uint16_t ALLOW_PASSIVE_TO_ACTIVE:5;
6063 uint16_t KEY_SLOT_HEADER_CRC:11;
6070 uint16_t FIRST_MINISLOT_ACTION_POINT_OFFSET:6;
6071 uint16_t STATIC_SLOT_AFTER_ACTION_POINT:10;
6078 uint16_t RATE_CORRECTION_OUT:11;
6079 uint16_t LISTEN_TIMEOUT_H:5;
6086 uint16_t LISTEN_TIMEOUT_L:16;
6093 uint16_t MACRO_INITIAL_OFFSET_B:7;
6094 uint16_t NOISE_LISTEN_TIMEOUT_H:9;
6101 uint16_t NOISE_LISTEN_TIMEOUT_L:16;
6108 uint16_t WAKEUP_PATTERN:6;
6109 uint16_t KEY_SLOT_ID:10;
6116 uint16_t DECODING_CORRECTION_A:9;
6117 uint16_t PAYLOAD_LENGTH_STATIC:7;
6124 uint16_t MICRO_INITIAL_OFFSET_B:8;
6125 uint16_t MICRO_INITIAL_OFFSET_A:8;
6132 uint16_t EXTERN_RATE_CORRECTION:3;
6133 uint16_t LATEST_TX:13;
6141 uint16_t COMP_ACCEPTED_STARTUP_RANGE_A:11;
6142 uint16_t MICRO_PER_CYCLE_H:4;
6149 uint16_t micro_per_cycle_l:16;
6156 uint16_t CLUSTER_DRIFT_DAMPING:5;
6157 uint16_t MAX_PAYLOAD_LENGTH_DYNAMIC:7;
6158 uint16_t MICRO_PER_CYCLE_MIN_H:4;
6165 uint16_t MICRO_PER_CYCLE_MIN_L:16;
6172 uint16_t ALLOW_HALT_DUE_TO_CLOCK:1;
6173 uint16_t COMP_ACCEPTED_STARTUP_RANGE_B:11;
6174 uint16_t MICRO_PER_CYCLE_MAX_H:4;
6181 uint16_t MICRO_PER_CYCLE_MAX_L:16;
6188 uint16_t DYNAMIC_SLOT_IDLE_PHASE:2;
6189 uint16_t MACRO_AFTER_OFFSET_CORRECTION:14;
6196 uint16_t EXTERN_OFFSET_CORRECTION:3;
6197 uint16_t MINISLOTS_MAX:13;
6205 uint16_t SYNC_NODE_MAX:4;
6261 typedef union uPDAR {
6297 typedef union uNMVR {
6312 typedef union uSSCR {
6315 typedef union uRFSR {
6355 uint16_t reserved3a[1];
6378 uint16_t reserved3[1];
6394 volatile SSR_t SSR[8];
6443 uint16_t reserved2[17];
6509 uint16_t DATA_OFFSET;
6515#define SRAM_START 0x40000000
6516#define SRAM_SIZE 0x40000
6517#define SRAM_END 0x4003FFFF
6519#define FLASH_START 0x00000000
6520#define FLASH_SIZE 0x400000
6521#define FLASH_END 0x003FFFFF
6524#define PBRIDGE_A (*( volatile struct PBRIDGE_A_tag *) 0xC3F00000)
6525#define FMPLL (*( volatile struct FMPLL_tag *) 0xC3F80000)
6526#define EBI (*( volatile struct EBI_tag *) 0xC3F84000)
6527#define FLASH_A (*( volatile struct FLASH_tag *) 0xC3F88000)
6528#define FLASH FLASH_A
6529#define FLASH_B (*( volatile struct FLASH_tag *) 0xC3F8C000)
6530#define SIU (*( volatile struct SIU_tag *) 0xC3F90000)
6532#define EMIOS (*( volatile struct EMIOS_tag *) 0xC3FA0000)
6533#define PMC (*( volatile struct PMC_tag *) 0xC3FBC000)
6535#define ETPU (*( volatile struct ETPU_tag *) 0xC3FC0000)
6536#define ETPU_DATA_RAM (*( uint32_t *) 0xC3FC8000)
6537#define ETPU_DATA_RAM_END 0xC3FC8FFC
6538#define ETPU_DATA_RAM_EXT (*( uint32_t *) 0xC3FCC000)
6539#define CODE_RAM (*( uint32_t *) 0xC3FD0000)
6540#define ETPU_CODE_RAM (*( uint32_t *) 0xC3FD0000)
6542#define PIT (*( volatile struct PIT_tag *) 0xC3FF0000)
6544#define PBRIDGE_B (*( volatile struct PBRIDGE_B_tag *) 0xFFF00000)
6545#define XBAR (*( volatile struct XBAR_tag *) 0xFFF04000)
6546#define MPU (*( volatile struct MPU_tag *) 0xFFF10000)
6547#define SWT (*( volatile struct SWT_tag *) 0xFFF38000)
6548#define STM (*( volatile struct STM_tag *) 0xFFF3C000)
6549#define ECSM (*( volatile struct ECSM_tag *) 0xFFF40000)
6550#define EDMA_A (*( volatile struct EDMA_tag *) 0xFFF44000)
6552#define INTC (*( volatile struct INTC_tag *) 0xFFF48000)
6553#define EDMA_B (*( volatile struct EDMA_tag *) 0xFFF54000)
6555#define EQADC_A (*( volatile struct EQADC_tag *) 0xFFF80000)
6556#define EQADC EQADC_A
6557#define EQADC_B (*( volatile struct EQADC_tag *) 0xFFF84000)
6559#define DECFIL_A (*( volatile struct DECFIL_tag *) 0xFFF88000)
6560#define DECFIL_B (*( volatile struct DECFIL_tag *) 0xFFF88800)
6561#define DECFIL_C (*( volatile struct DECFIL_tag *) 0xFFF89000)
6562#define DECFIL_D (*( volatile struct DECFIL_tag *) 0xFFF89800)
6563#define DECFIL_E (*( volatile struct DECFIL_tag *) 0xFFF8A000)
6564#define DECFIL_F (*( volatile struct DECFIL_tag *) 0xFFF8A800)
6565#define DECFIL_G (*( volatile struct DECFIL_tag *) 0xFFF8B000)
6566#define DECFIL_H (*( volatile struct DECFIL_tag *) 0xFFF8B800)
6568#define DSPI_A (*( volatile struct DSPI_tag *) 0xFFF90000)
6569#define DSPI_B (*( volatile struct DSPI_tag *) 0xFFF94000)
6570#define DSPI_C (*( volatile struct DSPI_tag *) 0xFFF98000)
6571#define DSPI_D (*( volatile struct DSPI_tag *) 0xFFF9C000)
6573#define ESCI_A (*( volatile struct ESCI_tag *) 0xFFFB0000)
6574#define ESCI_B (*( volatile struct ESCI_tag *) 0xFFFB4000)
6575#define ESCI_C (*( volatile struct ESCI_tag *) 0xFFFB8000)
6576#define ESCI_D (*( volatile struct ESCI_tag *) 0xFFFBC000)
6578#define CAN_A (*( volatile struct FLEXCAN2_tag *) 0xFFFC0000)
6579#define CAN_B (*( volatile struct FLEXCAN2_tag *) 0xFFFC4000)
6580#define CAN_C (*( volatile struct FLEXCAN2_tag *) 0xFFFC8000)
6581#define CAN_D (*( volatile struct FLEXCAN2_tag *) 0xFFFCC000)
6583#define FR (*( volatile struct FR_tag *) 0xFFFE0000)
6584#define TSENS (*( volatile struct TSENS_tag *) 0xFFFEC000)
Definition: fsl-mpc567x.h:4501
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