RTEMS 6.1-rc6
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fsl-mpc556x.h
1/*
2 * Modifications of the original file provided by Freescale are:
3 *
4 * Copyright (c) 2011 embedded brains GmbH & Co. KG
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 */
27
28/**************************************************************************/
29/* FILE NAME: mpc5567.h COPYRIGHT (c) Freescale 2007 */
30/* VERSION: 1.5 All Rights Reserved */
31/* */
32/* DESCRIPTION: */
33/* This file contain all of the register and bit field definitions for */
34/* MPC5567. */
35/*========================================================================*/
36/* UPDATE HISTORY */
37/* REV AUTHOR DATE DESCRIPTION OF CHANGE */
38/* --- ----------- --------- --------------------- */
39/* 1.0 G. Emerson 03/Jan/06 Initial version. */
40/* 1.1 G. Emerson 27/Mar/06 Fix issue with Flexcan BCC field. */
41/* 1.2 S. Mathieson 28/Jul/06 Change Flexcan BCC bit to MBFEN */
42/* Add Flexcan bits WRNEN, SRXDIS, */
43/* TWRNMSK, RWRNMSK,TWRNINT,RWRNINT */
44/* 1.3 S. Mathieson 30/Aug/06 SPR: L1SCR0, updated bit name from DPP */
45/* to DPB to align with documentation. */
46/* 1.4 S. Mathieson 26/Feb/07 eDMA TCD format updated to include */
47/* alternate configuration. */
48/* INTC, correction to the number of PSR */
49/* registers. */
50/* Updates to bitfield sizes in MBSSUTR, */
51/* MBIVEC, MBIDX & RSBIR. RSBIR, SELEC */
52/* changed to SEL & RFRFCFR, FNUM changed */
53/* to SEL to align with documentation. */
54/* Various register/ bitfield updates to */
55/* correct errors (MCR, TMODE bit removed.*/
56/* PADR register removed. PIER1, DRDIE bit*/
57/* removed & PIFR1, DRDIF removed. PCR1, */
58/* Filter bypass bit removed). */
59/* 1.5 S. Mathieson 25/Apr/07 SRAM size changed from 64K to 80K. */
60/* */
61/**************************************************************************/
62/*>>>>NOTE! this file is auto-generated please do not edit it!<<<<*/
63
64#ifndef _MPC5567_H_
65#define _MPC5567_H_
66
67#ifndef ASM
68
69#include <stdint.h>
70
71#include <mpc55xx/regs-edma.h>
72
73#ifdef __cplusplus
74extern "C" {
75#endif
76
77#ifdef __MWERKS__
78#pragma push
79#pragma ANSI_strict off
80#endif
81
82/****************************************************************************/
83/* MODULE : PBRIDGE_A Peripheral Bridge */
84/****************************************************************************/
85 struct PBRIDGE_A_tag {
86 union {
87 uint32_t R;
88 struct {
89 uint32_t MBW0:1;
90 uint32_t MTR0:1;
91 uint32_t MTW0:1;
92 uint32_t MPL0:1;
93 uint32_t MBW1:1;
94 uint32_t MTR1:1;
95 uint32_t MTW1:1;
96 uint32_t MPL1:1;
97 uint32_t MBW2:1;
98 uint32_t MTR2:1;
99 uint32_t MTW2:1;
100 uint32_t MPL2:1;
101 uint32_t MBW3:1;
102 uint32_t MTR3:1;
103 uint32_t MTW3:1;
104 uint32_t MPL3:1;
105
106 uint32_t MBW4:1; /* FEC */
107 uint32_t MTR4:1;
108 uint32_t MTW4:1;
109 uint32_t MPL4:1;
110
111 uint32_t:4;
112
113 uint32_t MBW6:1; /* FLEXRAY */
114 uint32_t MTR6:1;
115 uint32_t MTW6:1;
116 uint32_t MPL6:1;
117
118 uint32_t:4;
119 } B;
120 } MPCR; /* Master Privilege Control Register */
121
122 uint32_t pbridge_a_reserved2[7];
123
124 union {
125 uint32_t R;
126 struct {
127 uint32_t BW0:1;
128 uint32_t SP0:1;
129 uint32_t WP0:1;
130 uint32_t TP0:1;
131 uint32_t:28;
132 } B;
133 } PACR0;
134
135 uint32_t pbridge_a_reserved3[7];
136
137 union {
138 uint32_t R;
139 struct {
140 uint32_t BW0:1;
141 uint32_t SP0:1;
142 uint32_t WP0:1;
143 uint32_t TP0:1;
144 uint32_t BW1:1;
145 uint32_t SP1:1;
146 uint32_t WP1:1;
147 uint32_t TP1:1;
148 uint32_t BW2:1;
149 uint32_t SP2:1;
150 uint32_t WP2:1;
151 uint32_t TP2:1;
152 uint32_t:4;
153 uint32_t BW4:1;
154 uint32_t SP4:1;
155 uint32_t WP4:1;
156 uint32_t TP4:1;
157 uint32_t:12;
158 } B;
159 } OPACR0;
160
161 union {
162 uint32_t R;
163 struct {
164
165 uint32_t BW0:1; /* EMIOS */
166 uint32_t SP0:1;
167 uint32_t WP0:1;
168 uint32_t TP0:1;
169
170 uint32_t:28;
171 } B;
172 } OPACR1;
173
174 union {
175 uint32_t R;
176 struct {
177 uint32_t BW0:1;
178 uint32_t SP0:1;
179 uint32_t WP0:1;
180 uint32_t TP0:1;
181 uint32_t:4;
182 uint32_t BW2:1;
183 uint32_t SP2:1;
184 uint32_t WP2:1;
185 uint32_t TP2:1;
186 uint32_t BW3:1;
187 uint32_t SP3:1;
188 uint32_t WP3:1;
189 uint32_t TP3:1;
190 uint32_t BW4:1;
191 uint32_t SP4:1;
192 uint32_t WP4:1;
193 uint32_t TP4:1;
194 uint32_t:12;
195 } B;
196 } OPACR2;
197
198 };
199
200/****************************************************************************/
201/* MODULE : PBRIDGE_B Peripheral Bridge */
202/****************************************************************************/
203 struct PBRIDGE_B_tag {
204 union {
205 uint32_t R;
206 struct {
207 uint32_t MBW0:1;
208 uint32_t MTR0:1;
209 uint32_t MTW0:1;
210 uint32_t MPL0:1;
211 uint32_t MBW1:1;
212 uint32_t MTR1:1;
213 uint32_t MTW1:1;
214 uint32_t MPL1:1;
215 uint32_t MBW2:1;
216 uint32_t MTR2:1;
217 uint32_t MTW2:1;
218 uint32_t MPL2:1;
219 uint32_t MBW3:1;
220 uint32_t MTR3:1;
221 uint32_t MTW3:1;
222 uint32_t MPL3:1;
223
224 uint32_t MBW4:1; /* FEC */
225 uint32_t MTR4:1;
226 uint32_t MTW4:1;
227 uint32_t MPL4:1;
228
229 uint32_t:4;
230
231 uint32_t MBW6:1; /* FLEXRAY */
232 uint32_t MTR6:1;
233 uint32_t MTW6:1;
234 uint32_t MPL6:1;
235
236 uint32_t:4;
237 } B;
238 } MPCR; /* Master Privilege Control Register */
239
240 uint32_t pbridge_b_reserved2[7];
241
242 union {
243 uint32_t R;
244 struct {
245 uint32_t BW0:1;
246 uint32_t SP0:1;
247 uint32_t WP0:1;
248 uint32_t TP0:1;
249 uint32_t BW1:1;
250 uint32_t SP1:1;
251 uint32_t WP1:1;
252 uint32_t TP1:1;
253 uint32_t:24;
254 } B;
255 } PACR0;
256
257 uint32_t pbridge_b_reserved3;
258
259 union {
260 uint32_t R;
261 struct {
262 uint32_t BW0:1;
263 uint32_t SP0:1;
264 uint32_t WP0:1;
265 uint32_t TP0:1;
266 uint32_t BW1:1;
267 uint32_t SP1:1;
268 uint32_t WP1:1;
269 uint32_t TP1:1;
270 uint32_t BW2:1;
271 uint32_t SP2:1;
272 uint32_t WP2:1;
273 uint32_t TP2:1;
274
275 uint32_t BW3:1; /* FEC */
276 uint32_t SP3:1;
277 uint32_t WP3:1;
278 uint32_t TP3:1;
279
280 uint32_t:16;
281
282 } B;
283 } PACR2;
284
285 uint32_t pbridge_b_reserved4[5];
286
287 union {
288 uint32_t R;
289 struct {
290 uint32_t BW0:1;
291 uint32_t SP0:1;
292 uint32_t WP0:1;
293 uint32_t TP0:1;
294 uint32_t:12;
295
296 uint32_t:4;
297
298 uint32_t BW5:1; /* DSPI_B */
299 uint32_t SP5:1;
300 uint32_t WP5:1;
301 uint32_t TP5:1;
302
303 uint32_t BW6:1;
304 uint32_t SP6:1;
305 uint32_t WP6:1;
306 uint32_t TP6:1;
307 uint32_t BW7:1;
308 uint32_t SP7:1;
309 uint32_t WP7:1;
310 uint32_t TP7:1;
311 } B;
312 } OPACR0;
313
314 union {
315 uint32_t R;
316 struct {
317 uint32_t:16;
318 uint32_t BW4:1;
319 uint32_t SP4:1;
320 uint32_t WP4:1;
321 uint32_t TP4:1;
322
323 uint32_t BW5:1; /* ESCI_B */
324 uint32_t SP5:1;
325 uint32_t WP5:1;
326 uint32_t TP5:1;
327
328 uint32_t:8;
329 } B;
330 } OPACR1;
331
332 union {
333 uint32_t R;
334 struct {
335 uint32_t BW0:1;
336 uint32_t SP0:1;
337 uint32_t WP0:1;
338 uint32_t TP0:1;
339
340 uint32_t BW1:1; /* CAN_B */
341 uint32_t SP1:1;
342 uint32_t WP1:1;
343 uint32_t TP1:1;
344
345 uint32_t BW2:1;
346 uint32_t SP2:1;
347 uint32_t WP2:1;
348 uint32_t TP2:1;
349
350 uint32_t BW3:1; /* CAN_D */
351 uint32_t SP3:1;
352 uint32_t WP3:1;
353 uint32_t TP3:1;
354
355 uint32_t BW4:1; /* CAN_E */
356 uint32_t SP4:1;
357 uint32_t WP4:1;
358 uint32_t TP4:1;
359
360 uint32_t:12;
361 } B;
362 } OPACR2;
363
364 union {
365 uint32_t R;
366 struct {
367
368 uint32_t BW0:1; /* FLEXRAY */
369 uint32_t SP0:1;
370 uint32_t WP0:1;
371 uint32_t TP0:1;
372
373 uint32_t:24;
374 uint32_t BW7:1;
375 uint32_t SP7:1;
376 uint32_t WP7:1;
377 uint32_t TP7:1;
378 } B;
379 } OPACR3;
380
381 };
382/****************************************************************************/
383/* MODULE : FMPLL */
384/****************************************************************************/
385 struct FMPLL_tag {
386 union FMPLL_SYNCR_tag {
387 uint32_t R;
388 struct {
389 uint32_t:1;
390 uint32_t PREDIV:3;
391 uint32_t MFD:5;
392 uint32_t:1;
393 uint32_t RFD:3;
394 uint32_t LOCEN:1;
395 uint32_t LOLRE:1;
396 uint32_t LOCRE:1;
397 uint32_t DISCLK:1;
398 uint32_t LOLIRQ:1;
399 uint32_t LOCIRQ:1;
400 uint32_t RATE:1;
401 uint32_t DEPTH:2;
402 uint32_t EXP:10;
403 } B;
404 } SYNCR;
405
406 union FMPLL_SYNSR_tag {
407 uint32_t R;
408 struct {
409 uint32_t:22;
410 uint32_t LOLF:1;
411 uint32_t LOC:1;
412 uint32_t MODE:1;
413 uint32_t PLLSEL:1;
414 uint32_t PLLREF:1;
415 uint32_t LOCKS:1;
416 uint32_t LOCK:1;
417 uint32_t LOCF:1;
418 uint32_t CALDONE:1;
419 uint32_t CALPASS:1;
420 } B;
421 } SYNSR;
422
423 };
424/****************************************************************************/
425/* MODULE : External Bus Interface (EBI) */
426/****************************************************************************/
427 struct EBI_CS_tag {
428 union { /* Base Register Bank */
429 uint32_t R;
430 struct {
431 uint32_t BA:17;
432 uint32_t:3;
433 uint32_t PS:1;
434 uint32_t:4;
435 uint32_t BL:1;
436 uint32_t WEBS:1;
437 uint32_t TBDIP:1;
438 uint32_t:2;
439 uint32_t BI:1;
440 uint32_t V:1;
441 } B;
442 } BR;
443
444 union { /* Option Register Bank */
445 uint32_t R;
446 struct {
447 uint32_t AM:17;
448 uint32_t:7;
449 uint32_t SCY:4;
450 uint32_t:1;
451 uint32_t BSCY:2;
452 uint32_t:1;
453 } B;
454 } OR;
455 };
456
457 struct EBI_CAL_CS_tag {
458 union { /* Calibration Base Register Bank */
459 uint32_t R;
460 struct {
461 uint32_t BA:17;
462 uint32_t:3;
463 uint32_t PS:1;
464 uint32_t:4;
465 uint32_t BL:1;
466 uint32_t WEBS:1;
467 uint32_t TBDIP:1;
468 uint32_t:2;
469 uint32_t BI:1;
470 uint32_t V:1;
471 } B;
472 } BR;
473
474 union { /* Calibration Option Register Bank */
475 uint32_t R;
476 struct {
477 uint32_t AM:17;
478 uint32_t:7;
479 uint32_t SCY:4;
480 uint32_t:1;
481 uint32_t BSCY:2;
482 uint32_t:1;
483 } B;
484 } OR;
485 };
486
487 struct EBI_tag {
488 union EBI_MCR_tag { /* Module Configuration Register */
489 uint32_t R;
490 struct {
491 uint32_t:5;
492 uint32_t SIZEEN:1;
493 uint32_t SIZE:2;
494 uint32_t:8;
495 uint32_t ACGE:1;
496 uint32_t EXTM:1;
497 uint32_t EARB:1;
498 uint32_t EARP:2;
499 uint32_t:4;
500 uint32_t MDIS:1;
501 uint32_t:5;
502 uint32_t DBM:1;
503 } B;
504 } MCR;
505
506 uint32_t EBI_reserved1;
507
508 union { /* Transfer Error Status Register */
509 uint32_t R;
510 struct {
511 uint32_t:30;
512 uint32_t TEAF:1;
513 uint32_t BMTF:1;
514 } B;
515 } TESR;
516
517 union { /* Bus Monitor Control Register */
518 uint32_t R;
519 struct {
520 uint32_t:16;
521 uint32_t BMT:8;
522 uint32_t BME:1;
523 uint32_t:7;
524 } B;
525 } BMCR;
526
527 struct EBI_CS_tag CS[4];
528
529/* Calibration registers */
530 uint32_t EBI_reserved2[4];
531 struct EBI_CAL_CS_tag CAL_CS[4];
532
533 };
534/****************************************************************************/
535/* MODULE : FLASH */
536/****************************************************************************/
537 struct FLASH_tag {
538 union { /* Module Configuration Register */
539 uint32_t R;
540 struct {
541 uint32_t:4;
542 uint32_t SIZE:4;
543 uint32_t:1;
544 uint32_t LAS:3;
545 uint32_t:3;
546 uint32_t MAS:1;
547 uint32_t EER:1;
548 uint32_t RWE:1;
549 uint32_t BBEPE:1;
550 uint32_t EPE:1;
551 uint32_t PEAS:1;
552 uint32_t DONE:1;
553 uint32_t PEG:1;
554
555 uint32_t:2;
556
557 uint32_t STOP:1;
558 uint32_t:1;
559 uint32_t PGM:1;
560 uint32_t PSUS:1;
561 uint32_t ERS:1;
562 uint32_t ESUS:1;
563 uint32_t EHV:1;
564 } B;
565 } MCR;
566
567 union LMLR_tag { /* LML Register */
568 uint32_t R;
569 struct {
570 uint32_t LME:1;
571 uint32_t:10;
572 uint32_t SLOCK:1;
573 uint32_t MLOCK:4;
574 uint32_t LLOCK:16;
575 } B;
576 } LMLR;
577
578 union HLR_tag { /* HL Register */
579 uint32_t R;
580 struct {
581 uint32_t HBE:1;
582 uint32_t:3;
583 uint32_t HBLOCK:28;
584 } B;
585 } HLR;
586
587 union SLMLR_tag { /* SLML Register */
588 uint32_t R;
589 struct {
590 uint32_t SLE:1;
591 uint32_t:10;
592 uint32_t SSLOCK:1;
593 uint32_t SMLOCK:4;
594 uint32_t SLLOCK:16;
595 } B;
596 } SLMLR;
597
598 union { /* LMS Register */
599 uint32_t R;
600 struct {
601 uint32_t:12;
602 uint32_t MSEL:4;
603 uint32_t LSEL:16;
604 } B;
605 } LMSR;
606
607 union {
608 uint32_t R;
609 struct {
610 uint32_t:4;
611 uint32_t HBSEL:28;
612 } B;
613 } HSR;
614
615 union {
616 uint32_t R;
617 struct {
618 uint32_t:10;
619 uint32_t ADDR:19;
620 uint32_t:3;
621 } B;
622 } AR;
623
624 union {
625 uint32_t R;
626 struct {
627
628 uint32_t:9;
629 uint32_t M6PFE:1; /* Flexray */
630 uint32_t:1;
631
632 uint32_t M4PFE:1; /* FEC */
633
634 uint32_t M3PFE:1;
635 uint32_t M2PFE:1;
636 uint32_t M1PFE:1;
637 uint32_t M0PFE:1;
638 uint32_t APC:3;
639 uint32_t WWSC:2;
640 uint32_t RWSC:3;
641
642 uint32_t DPFEN:2;
643 uint32_t IPFEN:2;
644
645 uint32_t PFLIM:3;
646 uint32_t BFEN:1;
647 } B;
648 } BIUCR;
649
650 union {
651 uint32_t R;
652 struct {
653
654 uint32_t:18;
655 uint32_t M6AP:2; /* Flexray */
656 uint32_t:2;
657
658 uint32_t M4AP:2; /* FEC */
659
660 uint32_t M3AP:2;
661 uint32_t M2AP:2;
662 uint32_t M1AP:2;
663 uint32_t M0AP:2;
664 } B;
665 } BIUAPR;
666 };
667/****************************************************************************/
668/* MODULE : SIU */
669/****************************************************************************/
670 struct SIU_tag {
671 int32_t SIU_reserved0;
672
673 union { /* MCU ID Register */
674 uint32_t R;
675 struct {
676 uint32_t PARTNUM:16;
677 uint32_t MASKNUM:16;
678 } B;
679 } MIDR;
680 int32_t SIU_reserved00;
681
682 union { /* Reset Status Register */
683 uint32_t R;
684 struct {
685 uint32_t PORS:1;
686 uint32_t ERS:1;
687 uint32_t LLRS:1;
688 uint32_t LCRS:1;
689 uint32_t WDRS:1;
690 uint32_t CRS:1;
691 uint32_t:8;
692 uint32_t SSRS:1;
693 uint32_t SERF:1;
694 uint32_t WKPCFG:1;
695 uint32_t:12;
696 uint32_t BOOTCFG:2;
697 uint32_t RGF:1;
698 } B;
699 } RSR;
700
701 union { /* System Reset Control Register */
702 uint32_t R;
703 struct {
704 uint32_t SSR:1;
705 uint32_t SER:1;
706 uint32_t:14;
707 uint32_t CRE:1;
708 uint32_t:15;
709 } B;
710 } SRCR;
711
712 union SIU_EISR_tag { /* External Interrupt Status Register */
713 uint32_t R;
714 struct {
715 uint32_t:16;
716 uint32_t EIF15:1;
717 uint32_t EIF14:1;
718 uint32_t EIF13:1;
719 uint32_t EIF12:1;
720 uint32_t EIF11:1;
721 uint32_t EIF10:1;
722 uint32_t EIF9:1;
723 uint32_t EIF8:1;
724 uint32_t EIF7:1;
725 uint32_t EIF6:1;
726 uint32_t EIF5:1;
727 uint32_t EIF4:1;
728 uint32_t EIF3:1;
729 uint32_t EIF2:1;
730 uint32_t EIF1:1;
731 uint32_t EIF0:1;
732 } B;
733 } EISR;
734
735 union SIU_DIRER_tag { /* DMA/Interrupt Request Enable Register */
736 uint32_t R;
737 struct {
738 uint32_t:16;
739 uint32_t EIRE15:1;
740 uint32_t EIRE14:1;
741 uint32_t EIRE13:1;
742 uint32_t EIRE12:1;
743 uint32_t EIRE11:1;
744 uint32_t EIRE10:1;
745 uint32_t EIRE9:1;
746 uint32_t EIRE8:1;
747 uint32_t EIRE7:1;
748 uint32_t EIRE6:1;
749 uint32_t EIRE5:1;
750 uint32_t EIRE4:1;
751 uint32_t EIRE3:1;
752 uint32_t EIRE2:1;
753 uint32_t EIRE1:1;
754 uint32_t EIRE0:1;
755 } B;
756 } DIRER;
757
758 union SIU_DIRSR_tag { /* DMA/Interrupt Select Register */
759 uint32_t R;
760 struct {
761 uint32_t:28;
762 uint32_t DIRS3:1;
763 uint32_t DIRS2:1;
764 uint32_t DIRS1:1;
765 uint32_t DIRS0:1;
766 } B;
767 } DIRSR;
768
769 union { /* Overrun Status Register */
770 uint32_t R;
771 struct {
772 uint32_t:16;
773 uint32_t OVF15:1;
774 uint32_t OVF14:1;
775 uint32_t OVF13:1;
776 uint32_t OVF12:1;
777 uint32_t OVF11:1;
778 uint32_t OVF10:1;
779 uint32_t OVF9:1;
780 uint32_t OVF8:1;
781 uint32_t OVF7:1;
782 uint32_t OVF6:1;
783 uint32_t OVF5:1;
784 uint32_t OVF4:1;
785 uint32_t OVF3:1;
786 uint32_t OVF2:1;
787 uint32_t OVF1:1;
788 uint32_t OVF0:1;
789 } B;
790 } OSR;
791
792 union SIU_ORER_tag { /* Overrun Request Enable Register */
793 uint32_t R;
794 struct {
795 uint32_t:16;
796 uint32_t ORE15:1;
797 uint32_t ORE14:1;
798 uint32_t ORE13:1;
799 uint32_t ORE12:1;
800 uint32_t ORE11:1;
801 uint32_t ORE10:1;
802 uint32_t ORE9:1;
803 uint32_t ORE8:1;
804 uint32_t ORE7:1;
805 uint32_t ORE6:1;
806 uint32_t ORE5:1;
807 uint32_t ORE4:1;
808 uint32_t ORE3:1;
809 uint32_t ORE2:1;
810 uint32_t ORE1:1;
811 uint32_t ORE0:1;
812 } B;
813 } ORER;
814
815 union SIU_IREER_tag { /* External IRQ Rising-Edge Event Enable Register */
816 uint32_t R;
817 struct {
818 uint32_t:16;
819 uint32_t IREE15:1;
820 uint32_t IREE14:1;
821 uint32_t IREE13:1;
822 uint32_t IREE12:1;
823 uint32_t IREE11:1;
824 uint32_t IREE10:1;
825 uint32_t IREE9:1;
826 uint32_t IREE8:1;
827 uint32_t IREE7:1;
828 uint32_t IREE6:1;
829 uint32_t IREE5:1;
830 uint32_t IREE4:1;
831 uint32_t IREE3:1;
832 uint32_t IREE2:1;
833 uint32_t IREE1:1;
834 uint32_t IREE0:1;
835 } B;
836 } IREER;
837
838 union SIU_IFEER_tag { /* External IRQ Falling-Edge Event Enable Register */
839 uint32_t R;
840 struct {
841 uint32_t:16;
842 uint32_t IFEE15:1;
843 uint32_t IFEE14:1;
844 uint32_t IFEE13:1;
845 uint32_t IFEE12:1;
846 uint32_t IFEE11:1;
847 uint32_t IFEE10:1;
848 uint32_t IFEE9:1;
849 uint32_t IFEE8:1;
850 uint32_t IFEE7:1;
851 uint32_t IFEE6:1;
852 uint32_t IFEE5:1;
853 uint32_t IFEE4:1;
854 uint32_t IFEE3:1;
855 uint32_t IFEE2:1;
856 uint32_t IFEE1:1;
857 uint32_t IFEE0:1;
858 } B;
859 } IFEER;
860
861 union SIU_IDFR_tag { /* External IRQ Digital Filter Register */
862 uint32_t R;
863 struct {
864 uint32_t:28;
865 uint32_t DFL:4;
866 } B;
867 } IDFR;
868
869 int32_t SIU_reserved1[3];
870
871 union SIU_PCR_tag { /* Pad Configuration Registers */
872 uint16_t R;
873 struct {
874 uint16_t:3;
875 uint16_t PA:3;
876 uint16_t OBE:1;
877 uint16_t IBE:1;
878 uint16_t DSC:2;
879 uint16_t ODE:1;
880 uint16_t HYS:1;
881 uint16_t SRC:2;
882 uint16_t WPE:1;
883 uint16_t WPS:1;
884 } B;
885 } PCR[512];
886
887 int16_t SIU_reserved_0[224];
888
889 union { /* GPIO Pin Data Output Registers */
890 uint8_t R;
891 struct {
892 uint8_t:7;
893 uint8_t PDO:1;
894 } B;
895 } GPDO[256];
896
897 int32_t SIU_reserved_3[64];
898
899 union { /* GPIO Pin Data Input Registers */
900 uint8_t R;
901 struct {
902 uint8_t:7;
903 uint8_t PDI:1;
904 } B;
905 } GPDI[256];
906
907 union { /* IMUX Register */
908 uint32_t R;
909 struct {
910 uint32_t TSEL5:2;
911 uint32_t TSEL4:2;
912 uint32_t TSEL3:2;
913 uint32_t TSEL2:2;
914 uint32_t TSEL1:2;
915 uint32_t TSEL0:2;
916 uint32_t:20;
917 } B;
918 } ETISR;
919
920 union { /* IMUX Register */
921 uint32_t R;
922 struct {
923 uint32_t ESEL15:2;
924 uint32_t ESEL14:2;
925 uint32_t ESEL13:2;
926 uint32_t ESEL12:2;
927 uint32_t ESEL11:2;
928 uint32_t ESEL10:2;
929 uint32_t ESEL9:2;
930 uint32_t ESEL8:2;
931 uint32_t ESEL7:2;
932 uint32_t ESEL6:2;
933 uint32_t ESEL5:2;
934 uint32_t ESEL4:2;
935 uint32_t ESEL3:2;
936 uint32_t ESEL2:2;
937 uint32_t ESEL1:2;
938 uint32_t ESEL0:2;
939 } B;
940 } EIISR;
941
942 union { /* IMUX Register */
943 uint32_t R;
944 struct {
945 uint32_t SINSELA:2;
946 uint32_t SSSELA:2;
947 uint32_t SCKSELA:2;
948 uint32_t TRIGSELA:2;
949 uint32_t SINSELB:2;
950 uint32_t SSSELB:2;
951 uint32_t SCKSELB:2;
952 uint32_t TRIGSELB:2;
953 uint32_t SINSELC:2;
954 uint32_t SSSELC:2;
955 uint32_t SCKSELC:2;
956 uint32_t TRIGSELC:2;
957 uint32_t SINSELD:2;
958 uint32_t SSSELD:2;
959 uint32_t SCKSELD:2;
960 uint32_t TRIGSELD:2;
961 } B;
962 } DISR;
963
964 int32_t SIU_reserved2[29];
965
966 union { /* Chip Configuration Register Register */
967 uint32_t R;
968 struct {
969 uint32_t:14;
970 uint32_t MATCH:1;
971 uint32_t DISNEX:1;
972 uint32_t:16;
973 } B;
974 } CCR;
975
976 union { /* External Clock Configuration Register Register */
977 uint32_t R;
978 struct {
979 uint32_t:18;
980 uint32_t ENGDIV:6;
981 uint32_t:4;
982 uint32_t EBTS:1;
983 uint32_t:1;
984 uint32_t EBDF:2;
985 } B;
986 } ECCR;
987
988 union {
989 uint32_t R;
990 } CARH;
991
992 union {
993 uint32_t R;
994 } CARL;
995
996 union {
997 uint32_t R;
998 } CBRH;
999
1000 union {
1001 uint32_t R;
1002 } CBRL;
1003
1004 };
1005/****************************************************************************/
1006/* MODULE : EMIOS */
1007/****************************************************************************/
1008 struct EMIOS_tag {
1009 union EMIOS_MCR_tag {
1010 uint32_t R;
1011 struct {
1012 uint32_t:1;
1013 uint32_t MDIS:1;
1014 uint32_t FRZ:1;
1015 uint32_t GTBE:1;
1016 uint32_t ETB:1;
1017 uint32_t GPREN:1;
1018 uint32_t:6;
1019 uint32_t SRV:4;
1020 uint32_t GPRE:8;
1021 uint32_t:8;
1022 } B;
1023 } MCR; /* Module Configuration Register */
1024
1025 union {
1026 uint32_t R;
1027 struct {
1028 uint32_t:8;
1029 uint32_t F23:1;
1030 uint32_t F22:1;
1031 uint32_t F21:1;
1032 uint32_t F20:1;
1033 uint32_t F19:1;
1034 uint32_t F18:1;
1035 uint32_t F17:1;
1036 uint32_t F16:1;
1037 uint32_t F15:1;
1038 uint32_t F14:1;
1039 uint32_t F13:1;
1040 uint32_t F12:1;
1041 uint32_t F11:1;
1042 uint32_t F10:1;
1043 uint32_t F9:1;
1044 uint32_t F8:1;
1045 uint32_t F7:1;
1046 uint32_t F6:1;
1047 uint32_t F5:1;
1048 uint32_t F4:1;
1049 uint32_t F3:1;
1050 uint32_t F2:1;
1051 uint32_t F1:1;
1052 uint32_t F0:1;
1053 } B;
1054 } GFR; /* Global FLAG Register */
1055
1056 union {
1057 uint32_t R;
1058 struct {
1059 uint32_t:8;
1060 uint32_t OU23:1;
1061 uint32_t OU22:1;
1062 uint32_t OU21:1;
1063 uint32_t OU20:1;
1064 uint32_t OU19:1;
1065 uint32_t OU18:1;
1066 uint32_t OU17:1;
1067 uint32_t OU16:1;
1068 uint32_t OU15:1;
1069 uint32_t OU14:1;
1070 uint32_t OU13:1;
1071 uint32_t OU12:1;
1072 uint32_t OU11:1;
1073 uint32_t OU10:1;
1074 uint32_t OU9:1;
1075 uint32_t OU8:1;
1076 uint32_t OU7:1;
1077 uint32_t OU6:1;
1078 uint32_t OU5:1;
1079 uint32_t OU4:1;
1080 uint32_t OU3:1;
1081 uint32_t OU2:1;
1082 uint32_t OU1:1;
1083 uint32_t OU0:1;
1084 } B;
1085 } OUDR; /* Output Update Disable Register */
1086
1087 uint32_t emios_reserved[5];
1088
1089 struct EMIOS_CH_tag {
1090 union {
1091 uint32_t R; /* Channel A Data Register */
1092 } CADR;
1093
1094 union {
1095 uint32_t R; /* Channel B Data Register */
1096 } CBDR;
1097
1098 union {
1099 uint32_t R; /* Channel Counter Register */
1100 } CCNTR;
1101
1102 union EMIOS_CCR_tag {
1103 uint32_t R;
1104 struct {
1105 uint32_t FREN:1;
1106 uint32_t ODIS:1;
1107 uint32_t ODISSL:2;
1108 uint32_t UCPRE:2;
1109 uint32_t UCPREN:1;
1110 uint32_t DMA:1;
1111 uint32_t:1;
1112 uint32_t IF:4;
1113 uint32_t FCK:1;
1114 uint32_t FEN:1;
1115 uint32_t:3;
1116 uint32_t FORCMA:1;
1117 uint32_t FORCMB:1;
1118 uint32_t:1;
1119 uint32_t BSL:2;
1120 uint32_t EDSEL:1;
1121 uint32_t EDPOL:1;
1122 uint32_t MODE:7;
1123 } B;
1124 } CCR; /* Channel Control Register */
1125
1126 union EMIOS_CSR_tag {
1127 uint32_t R;
1128 struct {
1129 uint32_t OVR:1;
1130 uint32_t:15;
1131 uint32_t OVFL:1;
1132 uint32_t:12;
1133 uint32_t UCIN:1;
1134 uint32_t UCOUT:1;
1135 uint32_t FLAG:1;
1136 } B;
1137 } CSR; /* Channel Status Register */
1138
1139 union {
1140 uint32_t R; /* Alternate Channel A Data Register */
1141 } ALTCADR;
1142
1143 uint32_t emios_channel_reserved[2];
1144
1145 } CH[24];
1146
1147 };
1148/****************************************************************************/
1149/* MODULE :ETPU */
1150/****************************************************************************/
1151
1152/***************************Configuration Registers**************************/
1153
1154 struct ETPU_tag {
1155 union { /* MODULE CONFIGURATION REGISTER */
1156 uint32_t R;
1157 struct {
1158 uint32_t GEC:1; /* Global Exception Clear */
1159 uint32_t:3;
1160 uint32_t MGE1:1; /* Microcode Global Exception-ETPU_A */
1161
1162 uint32_t:1; /* For single ETPU implementations */
1163
1164 uint32_t ILF1:1; /* Illegal Instruction Flag-ETPU_A */
1165
1166 uint32_t:1; /* For single ETPU implementations */
1167
1168 uint32_t:3;
1169 uint32_t SCMSIZE:5; /* Shared Code Memory size */
1170 uint32_t:5;
1171 uint32_t SCMMISF:1; /* SCM MISC Flag */
1172 uint32_t SCMMISEN:1; /* SCM MISC Enable */
1173 uint32_t:2;
1174 uint32_t VIS:1; /* SCM Visability */
1175 uint32_t:5;
1176 uint32_t GTBE:1; /* Global Time Base Enable */
1177 } B;
1178 } MCR;
1179
1180 union { /* COHERENT DUAL-PARAMETER CONTROL */
1181 uint32_t R;
1182 struct {
1183 uint32_t STS:1; /* Start Status bit */
1184 uint32_t CTBASE:5; /* Channel Transfer Base */
1185 uint32_t PBASE:10; /* Parameter Buffer Base Address */
1186 uint32_t PWIDTH:1; /* Parameter Width */
1187 uint32_t PARAM0:7; /* Channel Parameter 0 */
1188 uint32_t WR:1;
1189 uint32_t PARAM1:7; /* Channel Parameter 1 */
1190 } B;
1191 } CDCR;
1192
1193 uint32_t etpu_reserved1;
1194
1195 union { /* MISC Compare Register */
1196 uint32_t R;
1197 } MISCCMPR;
1198
1199 union { /* SCM off-range Date Register */
1200 uint32_t R;
1201 } SCMOFFDATAR;
1202
1203 union { /* ETPU_A Configuration Register */
1204 uint32_t R;
1205 struct {
1206 uint32_t FEND:1; /* Force END */
1207 uint32_t MDIS:1; /* Low power Stop */
1208 uint32_t:1;
1209 uint32_t STF:1; /* Stop Flag */
1210 uint32_t:4;
1211 uint32_t HLTF:1; /* Halt Mode Flag */
1212 uint32_t:4;
1213 uint32_t FPSCK:3; /* Filter Prescaler Clock Control */
1214 uint32_t CDFC:2;
1215 uint32_t:9;
1216 uint32_t ETB:5; /* Entry Table Base */
1217 } B;
1218 } ECR_A;
1219 uint32_t etpu_reserved3; /* For single ETPU implementations */
1220
1221 uint32_t etpu_reserved4;
1222
1223 union { /* ETPU_A Timebase Configuration Register */
1224 uint32_t R;
1225 struct {
1226 uint32_t TCR2CTL:3; /* TCR2 Clock/Gate Control */
1227 uint32_t TCRCF:2; /* TCRCLK Signal Filter Control */
1228 uint32_t:1;
1229 uint32_t AM:1; /* Angle Mode */
1230 uint32_t:3;
1231 uint32_t TCR2P:6; /* TCR2 Prescaler Control */
1232 uint32_t TCR1CTL:2; /* TCR1 Clock/Gate Control */
1233 uint32_t:6;
1234 uint32_t TCR1P:8; /* TCR1 Prescaler Control */
1235 } B;
1236 } TBCR_A;
1237
1238 union { /* ETPU_A TCR1 Visibility Register */
1239 uint32_t R;
1240 } TB1R_A;
1241
1242 union { /* ETPU_A TCR2 Visibility Register */
1243 uint32_t R;
1244 } TB2R_A;
1245
1246 union { /* ETPU_A STAC Configuration Register */
1247 uint32_t R;
1248 struct {
1249 uint32_t REN1:1; /* Resource Enable TCR1 */
1250 uint32_t RSC1:1; /* Resource Control TCR1 */
1251 uint32_t:2;
1252 uint32_t SERVER_ID1:4;
1253 uint32_t:4;
1254 uint32_t SRV1:4; /* Resource Server Slot */
1255 uint32_t REN2:1; /* Resource Enable TCR2 */
1256 uint32_t RSC2:1; /* Resource Control TCR2 */
1257 uint32_t:2;
1258 uint32_t SERVER_ID2:4;
1259 uint32_t:4;
1260 uint32_t SRV2:4; /* Resource Server Slot */
1261 } B;
1262 } REDCR_A;
1263
1264 uint32_t etpu_reserved5[4];
1265 uint32_t etpu_reserved6[4]; /* For single ETPU implementations */
1266
1267 uint32_t etpu_reserved7[108];
1268
1269/*****************************Status and Control Registers**************************/
1270
1271 union { /* ETPU_A Channel Interrut Status */
1272 uint32_t R;
1273 struct {
1274 uint32_t CIS31:1; /* Channel 31 Interrut Status */
1275 uint32_t CIS30:1; /* Channel 30 Interrut Status */
1276 uint32_t CIS29:1; /* Channel 29 Interrut Status */
1277 uint32_t CIS28:1; /* Channel 28 Interrut Status */
1278 uint32_t CIS27:1; /* Channel 27 Interrut Status */
1279 uint32_t CIS26:1; /* Channel 26 Interrut Status */
1280 uint32_t CIS25:1; /* Channel 25 Interrut Status */
1281 uint32_t CIS24:1; /* Channel 24 Interrut Status */
1282 uint32_t CIS23:1; /* Channel 23 Interrut Status */
1283 uint32_t CIS22:1; /* Channel 22 Interrut Status */
1284 uint32_t CIS21:1; /* Channel 21 Interrut Status */
1285 uint32_t CIS20:1; /* Channel 20 Interrut Status */
1286 uint32_t CIS19:1; /* Channel 19 Interrut Status */
1287 uint32_t CIS18:1; /* Channel 18 Interrut Status */
1288 uint32_t CIS17:1; /* Channel 17 Interrut Status */
1289 uint32_t CIS16:1; /* Channel 16 Interrut Status */
1290 uint32_t CIS15:1; /* Channel 15 Interrut Status */
1291 uint32_t CIS14:1; /* Channel 14 Interrut Status */
1292 uint32_t CIS13:1; /* Channel 13 Interrut Status */
1293 uint32_t CIS12:1; /* Channel 12 Interrut Status */
1294 uint32_t CIS11:1; /* Channel 11 Interrut Status */
1295 uint32_t CIS10:1; /* Channel 10 Interrut Status */
1296 uint32_t CIS9:1; /* Channel 9 Interrut Status */
1297 uint32_t CIS8:1; /* Channel 8 Interrut Status */
1298 uint32_t CIS7:1; /* Channel 7 Interrut Status */
1299 uint32_t CIS6:1; /* Channel 6 Interrut Status */
1300 uint32_t CIS5:1; /* Channel 5 Interrut Status */
1301 uint32_t CIS4:1; /* Channel 4 Interrut Status */
1302 uint32_t CIS3:1; /* Channel 3 Interrut Status */
1303 uint32_t CIS2:1; /* Channel 2 Interrut Status */
1304 uint32_t CIS1:1; /* Channel 1 Interrut Status */
1305 uint32_t CIS0:1; /* Channel 0 Interrut Status */
1306 } B;
1307 } CISR_A;
1308 uint32_t etpu_reserved8; /* For single ETPU implementations */
1309
1310 uint32_t etpu_reserved9[2];
1311
1312 union { /* ETPU_A Data Transfer Request Status */
1313 uint32_t R;
1314 struct {
1315 uint32_t DTRS31:1; /* Channel 31 Data Transfer Request Status */
1316 uint32_t DTRS30:1; /* Channel 30 Data Transfer Request Status */
1317 uint32_t DTRS29:1; /* Channel 29 Data Transfer Request Status */
1318 uint32_t DTRS28:1; /* Channel 28 Data Transfer Request Status */
1319 uint32_t DTRS27:1; /* Channel 27 Data Transfer Request Status */
1320 uint32_t DTRS26:1; /* Channel 26 Data Transfer Request Status */
1321 uint32_t DTRS25:1; /* Channel 25 Data Transfer Request Status */
1322 uint32_t DTRS24:1; /* Channel 24 Data Transfer Request Status */
1323 uint32_t DTRS23:1; /* Channel 23 Data Transfer Request Status */
1324 uint32_t DTRS22:1; /* Channel 22 Data Transfer Request Status */
1325 uint32_t DTRS21:1; /* Channel 21 Data Transfer Request Status */
1326 uint32_t DTRS20:1; /* Channel 20 Data Transfer Request Status */
1327 uint32_t DTRS19:1; /* Channel 19 Data Transfer Request Status */
1328 uint32_t DTRS18:1; /* Channel 18 Data Transfer Request Status */
1329 uint32_t DTRS17:1; /* Channel 17 Data Transfer Request Status */
1330 uint32_t DTRS16:1; /* Channel 16 Data Transfer Request Status */
1331 uint32_t DTRS15:1; /* Channel 15 Data Transfer Request Status */
1332 uint32_t DTRS14:1; /* Channel 14 Data Transfer Request Status */
1333 uint32_t DTRS13:1; /* Channel 13 Data Transfer Request Status */
1334 uint32_t DTRS12:1; /* Channel 12 Data Transfer Request Status */
1335 uint32_t DTRS11:1; /* Channel 11 Data Transfer Request Status */
1336 uint32_t DTRS10:1; /* Channel 10 Data Transfer Request Status */
1337 uint32_t DTRS9:1; /* Channel 9 Data Transfer Request Status */
1338 uint32_t DTRS8:1; /* Channel 8 Data Transfer Request Status */
1339 uint32_t DTRS7:1; /* Channel 7 Data Transfer Request Status */
1340 uint32_t DTRS6:1; /* Channel 6 Data Transfer Request Status */
1341 uint32_t DTRS5:1; /* Channel 5 Data Transfer Request Status */
1342 uint32_t DTRS4:1; /* Channel 4 Data Transfer Request Status */
1343 uint32_t DTRS3:1; /* Channel 3 Data Transfer Request Status */
1344 uint32_t DTRS2:1; /* Channel 2 Data Transfer Request Status */
1345 uint32_t DTRS1:1; /* Channel 1 Data Transfer Request Status */
1346 uint32_t DTRS0:1; /* Channel 0 Data Transfer Request Status */
1347 } B;
1348 } CDTRSR_A;
1349 uint32_t etpu_reserved10; /* For single ETPU implementations */
1350
1351 uint32_t etpu_reserved11[2];
1352
1353 union { /* ETPU_A Interruput Overflow Status */
1354 uint32_t R;
1355 struct {
1356 uint32_t CIOS31:1; /* Channel 31 Interruput Overflow Status */
1357 uint32_t CIOS30:1; /* Channel 30 Interruput Overflow Status */
1358 uint32_t CIOS29:1; /* Channel 29 Interruput Overflow Status */
1359 uint32_t CIOS28:1; /* Channel 28 Interruput Overflow Status */
1360 uint32_t CIOS27:1; /* Channel 27 Interruput Overflow Status */
1361 uint32_t CIOS26:1; /* Channel 26 Interruput Overflow Status */
1362 uint32_t CIOS25:1; /* Channel 25 Interruput Overflow Status */
1363 uint32_t CIOS24:1; /* Channel 24 Interruput Overflow Status */
1364 uint32_t CIOS23:1; /* Channel 23 Interruput Overflow Status */
1365 uint32_t CIOS22:1; /* Channel 22 Interruput Overflow Status */
1366 uint32_t CIOS21:1; /* Channel 21 Interruput Overflow Status */
1367 uint32_t CIOS20:1; /* Channel 20 Interruput Overflow Status */
1368 uint32_t CIOS19:1; /* Channel 19 Interruput Overflow Status */
1369 uint32_t CIOS18:1; /* Channel 18 Interruput Overflow Status */
1370 uint32_t CIOS17:1; /* Channel 17 Interruput Overflow Status */
1371 uint32_t CIOS16:1; /* Channel 16 Interruput Overflow Status */
1372 uint32_t CIOS15:1; /* Channel 15 Interruput Overflow Status */
1373 uint32_t CIOS14:1; /* Channel 14 Interruput Overflow Status */
1374 uint32_t CIOS13:1; /* Channel 13 Interruput Overflow Status */
1375 uint32_t CIOS12:1; /* Channel 12 Interruput Overflow Status */
1376 uint32_t CIOS11:1; /* Channel 11 Interruput Overflow Status */
1377 uint32_t CIOS10:1; /* Channel 10 Interruput Overflow Status */
1378 uint32_t CIOS9:1; /* Channel 9 Interruput Overflow Status */
1379 uint32_t CIOS8:1; /* Channel 8 Interruput Overflow Status */
1380 uint32_t CIOS7:1; /* Channel 7 Interruput Overflow Status */
1381 uint32_t CIOS6:1; /* Channel 6 Interruput Overflow Status */
1382 uint32_t CIOS5:1; /* Channel 5 Interruput Overflow Status */
1383 uint32_t CIOS4:1; /* Channel 4 Interruput Overflow Status */
1384 uint32_t CIOS3:1; /* Channel 3 Interruput Overflow Status */
1385 uint32_t CIOS2:1; /* Channel 2 Interruput Overflow Status */
1386 uint32_t CIOS1:1; /* Channel 1 Interruput Overflow Status */
1387 uint32_t CIOS0:1; /* Channel 0 Interruput Overflow Status */
1388 } B;
1389 } CIOSR_A;
1390 uint32_t etpu_reserved12; /* For single ETPU implementations */
1391
1392 uint32_t etpu_reserved13[2];
1393
1394 union { /* ETPU_A Data Transfer Overflow Status */
1395 uint32_t R;
1396 struct {
1397 uint32_t DTROS31:1; /* Channel 31 Data Transfer Overflow Status */
1398 uint32_t DTROS30:1; /* Channel 30 Data Transfer Overflow Status */
1399 uint32_t DTROS29:1; /* Channel 29 Data Transfer Overflow Status */
1400 uint32_t DTROS28:1; /* Channel 28 Data Transfer Overflow Status */
1401 uint32_t DTROS27:1; /* Channel 27 Data Transfer Overflow Status */
1402 uint32_t DTROS26:1; /* Channel 26 Data Transfer Overflow Status */
1403 uint32_t DTROS25:1; /* Channel 25 Data Transfer Overflow Status */
1404 uint32_t DTROS24:1; /* Channel 24 Data Transfer Overflow Status */
1405 uint32_t DTROS23:1; /* Channel 23 Data Transfer Overflow Status */
1406 uint32_t DTROS22:1; /* Channel 22 Data Transfer Overflow Status */
1407 uint32_t DTROS21:1; /* Channel 21 Data Transfer Overflow Status */
1408 uint32_t DTROS20:1; /* Channel 20 Data Transfer Overflow Status */
1409 uint32_t DTROS19:1; /* Channel 19 Data Transfer Overflow Status */
1410 uint32_t DTROS18:1; /* Channel 18 Data Transfer Overflow Status */
1411 uint32_t DTROS17:1; /* Channel 17 Data Transfer Overflow Status */
1412 uint32_t DTROS16:1; /* Channel 16 Data Transfer Overflow Status */
1413 uint32_t DTROS15:1; /* Channel 15 Data Transfer Overflow Status */
1414 uint32_t DTROS14:1; /* Channel 14 Data Transfer Overflow Status */
1415 uint32_t DTROS13:1; /* Channel 13 Data Transfer Overflow Status */
1416 uint32_t DTROS12:1; /* Channel 12 Data Transfer Overflow Status */
1417 uint32_t DTROS11:1; /* Channel 11 Data Transfer Overflow Status */
1418 uint32_t DTROS10:1; /* Channel 10 Data Transfer Overflow Status */
1419 uint32_t DTROS9:1; /* Channel 9 Data Transfer Overflow Status */
1420 uint32_t DTROS8:1; /* Channel 8 Data Transfer Overflow Status */
1421 uint32_t DTROS7:1; /* Channel 7 Data Transfer Overflow Status */
1422 uint32_t DTROS6:1; /* Channel 6 Data Transfer Overflow Status */
1423 uint32_t DTROS5:1; /* Channel 5 Data Transfer Overflow Status */
1424 uint32_t DTROS4:1; /* Channel 4 Data Transfer Overflow Status */
1425 uint32_t DTROS3:1; /* Channel 3 Data Transfer Overflow Status */
1426 uint32_t DTROS2:1; /* Channel 2 Data Transfer Overflow Status */
1427 uint32_t DTROS1:1; /* Channel 1 Data Transfer Overflow Status */
1428 uint32_t DTROS0:1; /* Channel 0 Data Transfer Overflow Status */
1429 } B;
1430 } CDTROSR_A;
1431 uint32_t etpu_reserved14; /* For single ETPU implementations */
1432
1433 uint32_t etpu_reserved15[2];
1434
1435 union { /* ETPU_A Channel Interruput Enable */
1436 uint32_t R;
1437 struct {
1438 uint32_t CIE31:1; /* Channel 31 Interruput Enable */
1439 uint32_t CIE30:1; /* Channel 30 Interruput Enable */
1440 uint32_t CIE29:1; /* Channel 29 Interruput Enable */
1441 uint32_t CIE28:1; /* Channel 28 Interruput Enable */
1442 uint32_t CIE27:1; /* Channel 27 Interruput Enable */
1443 uint32_t CIE26:1; /* Channel 26 Interruput Enable */
1444 uint32_t CIE25:1; /* Channel 25 Interruput Enable */
1445 uint32_t CIE24:1; /* Channel 24 Interruput Enable */
1446 uint32_t CIE23:1; /* Channel 23 Interruput Enable */
1447 uint32_t CIE22:1; /* Channel 22 Interruput Enable */
1448 uint32_t CIE21:1; /* Channel 21 Interruput Enable */
1449 uint32_t CIE20:1; /* Channel 20 Interruput Enable */
1450 uint32_t CIE19:1; /* Channel 19 Interruput Enable */
1451 uint32_t CIE18:1; /* Channel 18 Interruput Enable */
1452 uint32_t CIE17:1; /* Channel 17 Interruput Enable */
1453 uint32_t CIE16:1; /* Channel 16 Interruput Enable */
1454 uint32_t CIE15:1; /* Channel 15 Interruput Enable */
1455 uint32_t CIE14:1; /* Channel 14 Interruput Enable */
1456 uint32_t CIE13:1; /* Channel 13 Interruput Enable */
1457 uint32_t CIE12:1; /* Channel 12 Interruput Enable */
1458 uint32_t CIE11:1; /* Channel 11 Interruput Enable */
1459 uint32_t CIE10:1; /* Channel 10 Interruput Enable */
1460 uint32_t CIE9:1; /* Channel 9 Interruput Enable */
1461 uint32_t CIE8:1; /* Channel 8 Interruput Enable */
1462 uint32_t CIE7:1; /* Channel 7 Interruput Enable */
1463 uint32_t CIE6:1; /* Channel 6 Interruput Enable */
1464 uint32_t CIE5:1; /* Channel 5 Interruput Enable */
1465 uint32_t CIE4:1; /* Channel 4 Interruput Enable */
1466 uint32_t CIE3:1; /* Channel 3 Interruput Enable */
1467 uint32_t CIE2:1; /* Channel 2 Interruput Enable */
1468 uint32_t CIE1:1; /* Channel 1 Interruput Enable */
1469 uint32_t CIE0:1; /* Channel 0 Interruput Enable */
1470 } B;
1471 } CIER_A;
1472 uint32_t etpu_reserved16; /* For single ETPU implementations */
1473
1474 uint32_t etpu_reserved17[2];
1475
1476 union { /* ETPU_A Channel Data Transfer Request Enable */
1477 uint32_t R;
1478 struct {
1479 uint32_t DTRE31:1; /* Channel 31 Data Transfer Request Enable */
1480 uint32_t DTRE30:1; /* Channel 30 Data Transfer Request Enable */
1481 uint32_t DTRE29:1; /* Channel 29 Data Transfer Request Enable */
1482 uint32_t DTRE28:1; /* Channel 28 Data Transfer Request Enable */
1483 uint32_t DTRE27:1; /* Channel 27 Data Transfer Request Enable */
1484 uint32_t DTRE26:1; /* Channel 26 Data Transfer Request Enable */
1485 uint32_t DTRE25:1; /* Channel 25 Data Transfer Request Enable */
1486 uint32_t DTRE24:1; /* Channel 24 Data Transfer Request Enable */
1487 uint32_t DTRE23:1; /* Channel 23 Data Transfer Request Enable */
1488 uint32_t DTRE22:1; /* Channel 22 Data Transfer Request Enable */
1489 uint32_t DTRE21:1; /* Channel 21 Data Transfer Request Enable */
1490 uint32_t DTRE20:1; /* Channel 20 Data Transfer Request Enable */
1491 uint32_t DTRE19:1; /* Channel 19 Data Transfer Request Enable */
1492 uint32_t DTRE18:1; /* Channel 18 Data Transfer Request Enable */
1493 uint32_t DTRE17:1; /* Channel 17 Data Transfer Request Enable */
1494 uint32_t DTRE16:1; /* Channel 16 Data Transfer Request Enable */
1495 uint32_t DTRE15:1; /* Channel 15 Data Transfer Request Enable */
1496 uint32_t DTRE14:1; /* Channel 14 Data Transfer Request Enable */
1497 uint32_t DTRE13:1; /* Channel 13 Data Transfer Request Enable */
1498 uint32_t DTRE12:1; /* Channel 12 Data Transfer Request Enable */
1499 uint32_t DTRE11:1; /* Channel 11 Data Transfer Request Enable */
1500 uint32_t DTRE10:1; /* Channel 10 Data Transfer Request Enable */
1501 uint32_t DTRE9:1; /* Channel 9 Data Transfer Request Enable */
1502 uint32_t DTRE8:1; /* Channel 8 Data Transfer Request Enable */
1503 uint32_t DTRE7:1; /* Channel 7 Data Transfer Request Enable */
1504 uint32_t DTRE6:1; /* Channel 6 Data Transfer Request Enable */
1505 uint32_t DTRE5:1; /* Channel 5 Data Transfer Request Enable */
1506 uint32_t DTRE4:1; /* Channel 4 Data Transfer Request Enable */
1507 uint32_t DTRE3:1; /* Channel 3 Data Transfer Request Enable */
1508 uint32_t DTRE2:1; /* Channel 2 Data Transfer Request Enable */
1509 uint32_t DTRE1:1; /* Channel 1 Data Transfer Request Enable */
1510 uint32_t DTRE0:1; /* Channel 0 Data Transfer Request Enable */
1511 } B;
1512 } CDTRER_A;
1513 uint32_t etpu_reserved19; /* For single ETPU implementations */
1514
1515 uint32_t etpu_reserved20[10];
1516 union { /* ETPU_A Channel Pending Service Status */
1517 uint32_t R;
1518 struct {
1519 uint32_t SR31:1; /* Channel 31 Pending Service Status */
1520 uint32_t SR30:1; /* Channel 30 Pending Service Status */
1521 uint32_t SR29:1; /* Channel 29 Pending Service Status */
1522 uint32_t SR28:1; /* Channel 28 Pending Service Status */
1523 uint32_t SR27:1; /* Channel 27 Pending Service Status */
1524 uint32_t SR26:1; /* Channel 26 Pending Service Status */
1525 uint32_t SR25:1; /* Channel 25 Pending Service Status */
1526 uint32_t SR24:1; /* Channel 24 Pending Service Status */
1527 uint32_t SR23:1; /* Channel 23 Pending Service Status */
1528 uint32_t SR22:1; /* Channel 22 Pending Service Status */
1529 uint32_t SR21:1; /* Channel 21 Pending Service Status */
1530 uint32_t SR20:1; /* Channel 20 Pending Service Status */
1531 uint32_t SR19:1; /* Channel 19 Pending Service Status */
1532 uint32_t SR18:1; /* Channel 18 Pending Service Status */
1533 uint32_t SR17:1; /* Channel 17 Pending Service Status */
1534 uint32_t SR16:1; /* Channel 16 Pending Service Status */
1535 uint32_t SR15:1; /* Channel 15 Pending Service Status */
1536 uint32_t SR14:1; /* Channel 14 Pending Service Status */
1537 uint32_t SR13:1; /* Channel 13 Pending Service Status */
1538 uint32_t SR12:1; /* Channel 12 Pending Service Status */
1539 uint32_t SR11:1; /* Channel 11 Pending Service Status */
1540 uint32_t SR10:1; /* Channel 10 Pending Service Status */
1541 uint32_t SR9:1; /* Channel 9 Pending Service Status */
1542 uint32_t SR8:1; /* Channel 8 Pending Service Status */
1543 uint32_t SR7:1; /* Channel 7 Pending Service Status */
1544 uint32_t SR6:1; /* Channel 6 Pending Service Status */
1545 uint32_t SR5:1; /* Channel 5 Pending Service Status */
1546 uint32_t SR4:1; /* Channel 4 Pending Service Status */
1547 uint32_t SR3:1; /* Channel 3 Pending Service Status */
1548 uint32_t SR2:1; /* Channel 2 Pending Service Status */
1549 uint32_t SR1:1; /* Channel 1 Pending Service Status */
1550 uint32_t SR0:1; /* Channel 0 Pending Service Status */
1551 } B;
1552 } CPSSR_A;
1553 uint32_t etpu_reserved22; /* For single ETPU implementations */
1554
1555 uint32_t etpu_reserved20a[2];
1556
1557 union { /* ETPU_A Channel Service Status */
1558 uint32_t R;
1559 struct {
1560 uint32_t SS31:1; /* Channel 31 Service Status */
1561 uint32_t SS30:1; /* Channel 30 Service Status */
1562 uint32_t SS29:1; /* Channel 29 Service Status */
1563 uint32_t SS28:1; /* Channel 28 Service Status */
1564 uint32_t SS27:1; /* Channel 27 Service Status */
1565 uint32_t SS26:1; /* Channel 26 Service Status */
1566 uint32_t SS25:1; /* Channel 25 Service Status */
1567 uint32_t SS24:1; /* Channel 24 Service Status */
1568 uint32_t SS23:1; /* Channel 23 Service Status */
1569 uint32_t SS22:1; /* Channel 22 Service Status */
1570 uint32_t SS21:1; /* Channel 21 Service Status */
1571 uint32_t SS20:1; /* Channel 20 Service Status */
1572 uint32_t SS19:1; /* Channel 19 Service Status */
1573 uint32_t SS18:1; /* Channel 18 Service Status */
1574 uint32_t SS17:1; /* Channel 17 Service Status */
1575 uint32_t SS16:1; /* Channel 16 Service Status */
1576 uint32_t SS15:1; /* Channel 15 Service Status */
1577 uint32_t SS14:1; /* Channel 14 Service Status */
1578 uint32_t SS13:1; /* Channel 13 Service Status */
1579 uint32_t SS12:1; /* Channel 12 Service Status */
1580 uint32_t SS11:1; /* Channel 11 Service Status */
1581 uint32_t SS10:1; /* Channel 10 Service Status */
1582 uint32_t SS9:1; /* Channel 9 Service Status */
1583 uint32_t SS8:1; /* Channel 8 Service Status */
1584 uint32_t SS7:1; /* Channel 7 Service Status */
1585 uint32_t SS6:1; /* Channel 6 Service Status */
1586 uint32_t SS5:1; /* Channel 5 Service Status */
1587 uint32_t SS4:1; /* Channel 4 Service Status */
1588 uint32_t SS3:1; /* Channel 3 Service Status */
1589 uint32_t SS2:1; /* Channel 2 Service Status */
1590 uint32_t SS1:1; /* Channel 1 Service Status */
1591 uint32_t SS0:1; /* Channel 0 Service Status */
1592 } B;
1593 } CSSR_A;
1594 uint32_t etpu_reserved22a; /* For single ETPU implementations */
1595
1596 uint32_t etpu_reserved23[90];
1597
1598/*****************************Channels********************************/
1599
1600 struct {
1601 union {
1602 uint32_t R; /* Channel Configuration Register */
1603 struct {
1604 uint32_t CIE:1; /* Channel Interruput Enable */
1605 uint32_t DTRE:1; /* Data Transfer Request Enable */
1606 uint32_t CPR:2; /* Channel Priority */
1607 uint32_t:3;
1608 uint32_t ETCS:1; /* Entry Table Condition Select */
1609 uint32_t:3;
1610 uint32_t CFS:5; /* Channel Function Select */
1611 uint32_t ODIS:1; /* Output disable */
1612 uint32_t OPOL:1; /* output polarity */
1613 uint32_t:3;
1614 uint32_t CPBA:11; /* Channel Parameter Base Address */
1615 } B;
1616 } CR;
1617 union {
1618 uint32_t R; /* Channel Status Control Register */
1619 struct {
1620 uint32_t CIS:1; /* Channel Interruput Status */
1621 uint32_t CIOS:1; /* Channel Interruput Overflow Status */
1622 uint32_t:6;
1623 uint32_t DTRS:1; /* Data Transfer Status */
1624 uint32_t DTROS:1; /* Data Transfer Overflow Status */
1625 uint32_t:6;
1626 uint32_t IPS:1; /* Input Pin State */
1627 uint32_t OPS:1; /* Output Pin State */
1628 uint32_t OBE:1; /* Output Buffer Enable */
1629 uint32_t:11;
1630 uint32_t FM1:1; /* Function mode */
1631 uint32_t FM0:1; /* Function mode */
1632 } B;
1633 } SCR;
1634 union {
1635 uint32_t R; /* Channel Host Service Request Register */
1636 struct {
1637 uint32_t:29; /* Host Service Request */
1638 uint32_t HSR:3;
1639 } B;
1640 } HSRR;
1641 uint32_t etpu_reserved23;
1642 } CHAN[127];
1643
1644 };
1645/****************************************************************************/
1646/* MODULE : XBAR CrossBar */
1647/****************************************************************************/
1648 struct XBAR_tag {
1649 union {
1650 uint32_t R;
1651 struct {
1652 uint32_t:4;
1653
1654 uint32_t:1;
1655 uint32_t MSTR6:3; /* FLEXRAY */
1656
1657 uint32_t:4;
1658
1659 uint32_t:4;
1660
1661 uint32_t:1;
1662 uint32_t MSTR3:3; /* FEC */
1663
1664 uint32_t:1;
1665 uint32_t MSTR2:3;
1666 uint32_t:1;
1667 uint32_t MSTR1:3;
1668 uint32_t:1;
1669 uint32_t MSTR0:3;
1670 } B;
1671 } MPR0; /* Master Priority Register for Slave Port 0 */
1672
1673 uint32_t xbar_reserved1[3];
1674
1675 union {
1676 uint32_t R;
1677 struct {
1678 uint32_t RO:1;
1679 uint32_t:21;
1680 uint32_t ARB:2;
1681 uint32_t:2;
1682 uint32_t PCTL:2;
1683 uint32_t:1;
1684 uint32_t PARK:3;
1685 } B;
1686 } SGPCR0; /* General Purpose Control Register for Slave Port 0 */
1687
1688 uint32_t xbar_reserved2[59];
1689
1690 union {
1691 uint32_t R;
1692 struct {
1693 uint32_t:4;
1694
1695 uint32_t:1;
1696 uint32_t MSTR6:3; /* FLEXRAY */
1697
1698 uint32_t:4;
1699
1700 uint32_t:4;
1701
1702 uint32_t:1;
1703 uint32_t MSTR3:3; /* FEC */
1704
1705 uint32_t:1;
1706 uint32_t MSTR2:3;
1707 uint32_t:1;
1708 uint32_t MSTR1:3;
1709 uint32_t:1;
1710 uint32_t MSTR0:3;
1711 } B;
1712 } MPR1; /* Master Priority Register for Slave Port 1 */
1713
1714 uint32_t xbar_reserved3[3];
1715
1716 union {
1717 uint32_t R;
1718 struct {
1719 uint32_t RO:1;
1720 uint32_t:21;
1721 uint32_t ARB:2;
1722 uint32_t:2;
1723 uint32_t PCTL:2;
1724 uint32_t:1;
1725 uint32_t PARK:3;
1726 } B;
1727 } SGPCR1; /* General Purpose Control Register for Slave Port 1 */
1728
1729 uint32_t xbar_reserved4[123];
1730
1731 union {
1732 uint32_t R;
1733 struct {
1734 uint32_t:4;
1735
1736 uint32_t:1;
1737 uint32_t MSTR6:3; /* FLEXRAY */
1738
1739 uint32_t:4;
1740
1741 uint32_t:4;
1742
1743 uint32_t:1;
1744 uint32_t MSTR3:3; /* FEC */
1745
1746 uint32_t:1;
1747 uint32_t MSTR2:3;
1748 uint32_t:1;
1749 uint32_t MSTR1:3;
1750 uint32_t:1;
1751 uint32_t MSTR0:3;
1752 } B;
1753 } MPR3; /* Master Priority Register for Slave Port 3 */
1754
1755 uint32_t xbar_reserved5[3];
1756
1757 union {
1758 uint32_t R;
1759 struct {
1760 uint32_t RO:1;
1761 uint32_t:21;
1762 uint32_t ARB:2;
1763 uint32_t:2;
1764 uint32_t PCTL:2;
1765 uint32_t:1;
1766 uint32_t PARK:3;
1767 } B;
1768 } SGPCR3; /* General Purpose Control Register for Slave Port 3 */
1769 uint32_t xbar_reserved6[187];
1770
1771 union {
1772 uint32_t R;
1773 struct {
1774 uint32_t:4;
1775
1776 uint32_t:1;
1777 uint32_t MSTR6:3; /* FLEXRAY */
1778
1779 uint32_t:4;
1780
1781 uint32_t:4;
1782
1783 uint32_t:1;
1784 uint32_t MSTR3:3; /* FEC */
1785
1786 uint32_t:1;
1787 uint32_t MSTR2:3;
1788 uint32_t:1;
1789 uint32_t MSTR1:3;
1790 uint32_t:1;
1791 uint32_t MSTR0:3;
1792 } B;
1793 } MPR6; /* Master Priority Register for Slave Port 6 */
1794
1795 uint32_t xbar_reserved7[3];
1796
1797 union {
1798 uint32_t R;
1799 struct {
1800 uint32_t RO:1;
1801 uint32_t:21;
1802 uint32_t ARB:2;
1803 uint32_t:2;
1804 uint32_t PCTL:2;
1805 uint32_t:1;
1806 uint32_t PARK:3;
1807 } B;
1808 } SGPCR6; /* General Purpose Control Register for Slave Port 6 */
1809
1810 uint32_t xbar_reserved8[59];
1811
1812 union {
1813 uint32_t R;
1814 struct {
1815 uint32_t:4;
1816
1817 uint32_t:1;
1818 uint32_t MSTR6:3; /* FLEXRAY */
1819
1820 uint32_t:4;
1821
1822 uint32_t:4;
1823
1824 uint32_t:1;
1825 uint32_t MSTR3:3; /* FEC */
1826
1827 uint32_t:1;
1828 uint32_t MSTR2:3;
1829 uint32_t:1;
1830 uint32_t MSTR1:3;
1831 uint32_t:1;
1832 uint32_t MSTR0:3;
1833 } B;
1834 } MPR7; /* Master Priority Register for Slave Port 7 */
1835
1836 uint32_t xbar_reserved9[3];
1837
1838 union {
1839 uint32_t R;
1840 struct {
1841 uint32_t RO:1;
1842 uint32_t:21;
1843 uint32_t ARB:2;
1844 uint32_t:2;
1845 uint32_t PCTL:2;
1846 uint32_t:1;
1847 uint32_t PARK:3;
1848 } B;
1849 } SGPCR7; /* General Purpose Control Register for Slave Port 7 */
1850
1851 };
1852/****************************************************************************/
1853/* MODULE : ECSM */
1854/****************************************************************************/
1855 struct ECSM_tag {
1856
1857 uint32_t ecsm_reserved1[5];
1858
1859 uint16_t ecsm_reserved2;
1860
1861 union {
1862 uint16_t R;
1863 } SWTCR; //Software Watchdog Timer Control
1864
1865 uint8_t ecsm_reserved3[3];
1866
1867 union {
1868 uint8_t R;
1869 } SWTSR; //SWT Service Register
1870
1871 uint8_t ecsm_reserved4[3];
1872
1873 union {
1874 uint8_t R;
1875 } SWTIR; //SWT Interrupt Register
1876
1877 uint32_t ecsm_reserved5a[1];
1878
1879 union {
1880 uint32_t R;
1881 struct {
1882 uint32_t FSBCR0:1;
1883 uint32_t FSBCR1:1;
1884 uint32_t FSBCR2:1;
1885 uint32_t FSBCR3:1;
1886 uint32_t FSBCR4:1;
1887 uint32_t FSBCR5:1;
1888 uint32_t FSBCR6:1;
1889 uint32_t FSBCR7:1;
1890 uint32_t RBEN:1;
1891 uint32_t WBEN:1;
1892 uint32_t ACCERR:1;
1893 uint32_t:21;
1894 } B;
1895 } FSBMCR; /* FEC System Bus Master Control Register */
1896
1897 uint32_t ecsm_reserved5c[6];
1898
1899 uint8_t ecsm_reserved6[3];
1900
1901 union {
1902 uint8_t R;
1903 struct {
1904 uint8_t:6;
1905 uint8_t ERNCR:1;
1906 uint8_t EFNCR:1;
1907 } B;
1908 } ECR; //ECC Configuration Register
1909
1910 uint8_t mcm_reserved8[3];
1911
1912 union {
1913 uint8_t R;
1914 struct {
1915 uint8_t:6;
1916 uint8_t RNCE:1;
1917 uint8_t FNCE:1;
1918 } B;
1919 } ESR; //ECC Status Register
1920
1921 uint16_t ecsm_reserved9;
1922
1923 union {
1924 uint16_t R;
1925 struct {
1926 uint16_t:6;
1927 uint16_t FRCNCI:1;
1928 uint16_t FR1NCI:1;
1929 uint16_t:1;
1930 uint16_t ERRBIT:7;
1931 } B;
1932 } EEGR; //ECC Error Generation Register
1933
1934 uint32_t ecsm_reserved10;
1935
1936 union {
1937 uint32_t R;
1938 struct {
1939 uint32_t FEAR:32;
1940 } B;
1941 } FEAR; //Flash ECC Address Register
1942
1943 uint16_t ecsm_reserved11;
1944
1945 union {
1946 uint8_t R;
1947 struct {
1948 uint8_t:4;
1949 uint8_t FEMR:4;
1950 } B;
1951 } FEMR; //Flash ECC Master Register
1952
1953 union {
1954 uint8_t R;
1955 struct {
1956 uint8_t WRITE:1;
1957 uint8_t SIZE:3;
1958 uint8_t PROT0:1;
1959 uint8_t PROT1:1;
1960 uint8_t PROT2:1;
1961 uint8_t PROT3:1;
1962 } B;
1963 } FEAT; //Flash ECC Attributes Register
1964
1965 union {
1966 uint32_t R;
1967 struct {
1968 uint32_t FEDH:32;
1969 } B;
1970 } FEDRH; //Flash ECC Data High Register
1971
1972 union {
1973 uint32_t R;
1974 struct {
1975 uint32_t FEDL:32;
1976 } B;
1977 } FEDRL; //Flash ECC Data Low Register
1978
1979 union {
1980 uint32_t R;
1981 struct {
1982 uint32_t REAR:32;
1983 } B;
1984 } REAR; //RAM ECC Address
1985
1986 uint8_t ecsm_reserved12[2];
1987
1988 union {
1989 uint8_t R;
1990 struct {
1991 uint8_t:4;
1992 uint8_t REMR:4;
1993 } B;
1994 } REMR; //RAM ECC Master
1995
1996 union {
1997 uint8_t R;
1998 struct {
1999 uint8_t WRITE:1;
2000 uint8_t SIZE:3;
2001 uint8_t PROT0:1;
2002 uint8_t PROT1:1;
2003 uint8_t PROT2:1;
2004 uint8_t PROT3:1;
2005 } B;
2006 } REAT; // RAM ECC Attributes Register
2007
2008 union {
2009 uint32_t R;
2010 struct {
2011 uint32_t REDH:32;
2012 } B;
2013 } REDRH; //RAM ECC Data High Register
2014
2015 union {
2016 uint32_t R;
2017 struct {
2018 uint32_t REDL:32;
2019 } B;
2020 } REDRL; //RAMECC Data Low Register
2021
2022 };
2023/****************************************************************************/
2024/* MODULE : INTC */
2025/****************************************************************************/
2026 struct INTC_tag {
2027 union {
2028 uint32_t R;
2029 struct {
2030 uint32_t:26;
2031 uint32_t VTES:1;
2032 uint32_t:4;
2033 uint32_t HVEN:1;
2034 } B;
2035 } MCR; /* Module Configuration Register */
2036
2037 int32_t INTC_reserved00;
2038
2039 union {
2040 uint32_t R;
2041 struct {
2042 uint32_t:28;
2043 uint32_t PRI:4;
2044 } B;
2045 } CPR; /* Current Priority Register */
2046
2047 uint32_t intc_reserved1;
2048
2049 union {
2050 uint32_t R;
2051 struct {
2052 uint32_t VTBA:21;
2053 uint32_t INTVEC:9;
2054 uint32_t:2;
2055 } B;
2056 } IACKR; /* Interrupt Acknowledge Register */
2057
2058 uint32_t intc_reserved2;
2059
2060 union {
2061 uint32_t R;
2062 struct {
2063 uint32_t:32;
2064 } B;
2065 } EOIR; /* End of Interrupt Register */
2066
2067 uint32_t intc_reserved3;
2068
2069 union {
2070 uint8_t R;
2071 struct {
2072 uint8_t:6;
2073 uint8_t SET:1;
2074 uint8_t CLR:1;
2075 } B;
2076 } SSCIR[8]; /* Software Set/Clear Interruput Register */
2077
2078 uint32_t intc_reserved4[6];
2079
2080 union {
2081 uint8_t R;
2082 struct {
2083 uint8_t:4;
2084 uint8_t PRI:4;
2085 } B;
2086 } PSR[358]; /* Software Set/Clear Interrupt Register */
2087
2088 };
2089/****************************************************************************/
2090/* MODULE : EQADC */
2091/****************************************************************************/
2092 struct EQADC_tag {
2093 union {
2094 uint32_t R;
2095 struct {
2096 uint32_t:27;
2097 uint32_t ESSIE:2;
2098 uint32_t:1;
2099 uint32_t DBG:2;
2100 } B;
2101 } MCR; /* Module Configuration Register */
2102
2103 int32_t EQADC_reserved00;
2104
2105 union {
2106 uint32_t R;
2107 struct {
2108 uint32_t:6;
2109 uint32_t NMF:26;
2110 } B;
2111 } NMSFR; /* Null Message Send Format Register */
2112
2113 union {
2114 uint32_t R;
2115 struct {
2116 uint32_t:28;
2117 uint32_t DFL:4;
2118 } B;
2119 } ETDFR; /* External Trigger Digital Filter Register */
2120
2121 union {
2122 uint32_t R;
2123 struct {
2124 uint32_t CFPUSH:32;
2125 } B;
2126 } CFPR[6]; /* CFIFO Push Registers */
2127
2128 uint32_t eqadc_reserved1;
2129
2130 uint32_t eqadc_reserved2;
2131
2132 union {
2133 uint32_t R;
2134 struct {
2135 uint32_t:16;
2136 uint32_t RFPOP:16;
2137 } B;
2138 } RFPR[6]; /* Result FIFO Pop Registers */
2139
2140 uint32_t eqadc_reserved3;
2141
2142 uint32_t eqadc_reserved4;
2143
2144 union {
2145 uint16_t R;
2146 struct {
2147 uint16_t:5;
2148 uint16_t SSE:1;
2149 uint16_t CFINV:1;
2150 uint16_t:1;
2151 uint16_t MODE:4;
2152 uint16_t:4;
2153 } B;
2154 } CFCR[6]; /* CFIFO Control Registers */
2155
2156 uint32_t eqadc_reserved5;
2157
2158 union {
2159 uint16_t R;
2160 struct {
2161 uint16_t NCIE:1;
2162 uint16_t TORIE:1;
2163 uint16_t PIE:1;
2164 uint16_t EOQIE:1;
2165 uint16_t CFUIE:1;
2166 uint16_t:1;
2167 uint16_t CFFE:1;
2168 uint16_t CFFS:1;
2169 uint16_t:4;
2170 uint16_t RFOIE:1;
2171 uint16_t:1;
2172 uint16_t RFDE:1;
2173 uint16_t RFDS:1;
2174 } B;
2175 } IDCR[6]; /* Interrupt and DMA Control Registers */
2176
2177 uint32_t eqadc_reserved6;
2178
2179 union {
2180 uint32_t R;
2181 struct {
2182 uint32_t NCF:1;
2183 uint32_t TORF:1;
2184 uint32_t PF:1;
2185 uint32_t EOQF:1;
2186 uint32_t CFUF:1;
2187 uint32_t SSS:1;
2188 uint32_t CFFF:1;
2189 uint32_t:5;
2190 uint32_t RFOF:1;
2191 uint32_t:1;
2192 uint32_t RFDF:1;
2193 uint32_t:1;
2194 uint32_t CFCTR:4;
2195 uint32_t TNXTPTR:4;
2196 uint32_t RFCTR:4;
2197 uint32_t POPNXTPTR:4;
2198 } B;
2199 } FISR[6]; /* FIFO and Interrupt Status Registers */
2200
2201 uint32_t eqadc_reserved7;
2202
2203 uint32_t eqadc_reserved8;
2204
2205 union {
2206 uint16_t R;
2207 struct {
2208 uint16_t:5;
2209 uint16_t TCCF:11;
2210 } B;
2211 } CFTCR[6]; /* CFIFO Transfer Counter Registers */
2212
2213 uint32_t eqadc_reserved9;
2214
2215 union {
2216 uint32_t R;
2217 struct {
2218 uint32_t CFS0:2;
2219 uint32_t CFS1:2;
2220 uint32_t CFS2:2;
2221 uint32_t CFS3:2;
2222 uint32_t CFS4:2;
2223 uint32_t CFS5:2;
2224 uint32_t:5;
2225 uint32_t LCFTCB0:4;
2226 uint32_t TC_LCFTCB0:11;
2227 } B;
2228 } CFSSR0; /* CFIFO Status Register 0 */
2229
2230 union {
2231 uint32_t R;
2232 struct {
2233 uint32_t CFS0:2;
2234 uint32_t CFS1:2;
2235 uint32_t CFS2:2;
2236 uint32_t CFS3:2;
2237 uint32_t CFS4:2;
2238 uint32_t CFS5:2;
2239 uint32_t:5;
2240 uint32_t LCFTCB1:4;
2241 uint32_t TC_LCFTCB1:11;
2242 } B;
2243 } CFSSR1; /* CFIFO Status Register 1 */
2244
2245 union {
2246 uint32_t R;
2247 struct {
2248 uint32_t CFS0:2;
2249 uint32_t CFS1:2;
2250 uint32_t CFS2:2;
2251 uint32_t CFS3:2;
2252 uint32_t CFS4:2;
2253 uint32_t CFS5:2;
2254 uint32_t:4;
2255 uint32_t ECBNI:1;
2256 uint32_t LCFTSSI:4;
2257 uint32_t TC_LCFTSSI:11;
2258 } B;
2259 } CFSSR2; /* CFIFO Status Register 2 */
2260
2261 union {
2262 uint32_t R;
2263 struct {
2264 uint32_t CFS0:2;
2265 uint32_t CFS1:2;
2266 uint32_t CFS2:2;
2267 uint32_t CFS3:2;
2268 uint32_t CFS4:2;
2269 uint32_t CFS5:2;
2270 uint32_t:20;
2271 } B;
2272 } CFSR;
2273
2274 uint32_t eqadc_reserved11;
2275
2276 union {
2277 uint32_t R;
2278 struct {
2279 uint32_t:21;
2280 uint32_t MDT:3;
2281 uint32_t:4;
2282 uint32_t BR:4;
2283 } B;
2284 } SSICR; /* SSI Control Register */
2285
2286 union {
2287 uint32_t R;
2288 struct {
2289 uint32_t RDV:1;
2290 uint32_t:5;
2291 uint32_t RDATA:26;
2292 } B;
2293 } SSIRDR; /* SSI Recieve Data Register */
2294
2295 uint32_t eqadc_reserved12[17];
2296
2297 struct {
2298 union {
2299 uint32_t R;
2300 struct {
2301 uint32_t:32;
2302 } B;
2303 } R[4];
2304
2305 uint32_t eqadc_reserved13[12];
2306
2307 } CF[6];
2308
2309 uint32_t eqadc_reserved14[32];
2310
2311 struct {
2312 union {
2313 uint32_t R;
2314 struct {
2315 uint32_t:32;
2316 } B;
2317 } R[4];
2318
2319 uint32_t eqadc_reserved15[12];
2320
2321 } RF[6];
2322
2323 };
2324/****************************************************************************/
2325/* MODULE : DSPI */
2326/****************************************************************************/
2327 struct DSPI_tag {
2328 union DSPI_MCR_tag {
2329 uint32_t R;
2330 struct {
2331 uint32_t MSTR:1;
2332 uint32_t CONT_SCKE:1;
2333 uint32_t DCONF:2;
2334 uint32_t FRZ:1;
2335 uint32_t MTFE:1;
2336 uint32_t PCSSE:1;
2337 uint32_t ROOE:1;
2338 uint32_t:2;
2339 uint32_t PCSIS5:1;
2340 uint32_t PCSIS4:1;
2341 uint32_t PCSIS3:1;
2342 uint32_t PCSIS2:1;
2343 uint32_t PCSIS1:1;
2344 uint32_t PCSIS0:1;
2345 uint32_t DOZE:1;
2346 uint32_t MDIS:1;
2347 uint32_t DIS_TXF:1;
2348 uint32_t DIS_RXF:1;
2349 uint32_t CLR_TXF:1;
2350 uint32_t CLR_RXF:1;
2351 uint32_t SMPL_PT:2;
2352 uint32_t:7;
2353 uint32_t HALT:1;
2354 } B;
2355 } MCR; /* Module Configuration Register */
2356
2357 uint32_t dspi_reserved1;
2358
2359 union {
2360 uint32_t R;
2361 struct {
2362 uint32_t TCNT:16;
2363 uint32_t:16;
2364 } B;
2365 } TCR;
2366
2367 union DSPI_CTAR_tag {
2368 uint32_t R;
2369 struct {
2370 uint32_t DBR:1;
2371 uint32_t FMSZ:4;
2372 uint32_t CPOL:1;
2373 uint32_t CPHA:1;
2374 uint32_t LSBFE:1;
2375 uint32_t PCSSCK:2;
2376 uint32_t PASC:2;
2377 uint32_t PDT:2;
2378 uint32_t PBR:2;
2379 uint32_t CSSCK:4;
2380 uint32_t ASC:4;
2381 uint32_t DT:4;
2382 uint32_t BR:4;
2383 } B;
2384 } CTAR[8]; /* Clock and Transfer Attributes Registers */
2385
2386 union DSPI_SR_tag {
2387 uint32_t R;
2388 struct {
2389 uint32_t TCF:1;
2390 uint32_t TXRXS:1;
2391 uint32_t:1;
2392 uint32_t EOQF:1;
2393 uint32_t TFUF:1;
2394 uint32_t:1;
2395 uint32_t TFFF:1;
2396 uint32_t:5;
2397 uint32_t RFOF:1;
2398 uint32_t:1;
2399 uint32_t RFDF:1;
2400 uint32_t:1;
2401 uint32_t TXCTR:4;
2402 uint32_t TXNXTPTR:4;
2403 uint32_t RXCTR:4;
2404 uint32_t POPNXTPTR:4;
2405 } B;
2406 } SR; /* Status Register */
2407
2408 union DSPI_RSER_tag {
2409 uint32_t R;
2410 struct {
2411 uint32_t TCFRE:1;
2412 uint32_t:2;
2413 uint32_t EOQFRE:1;
2414 uint32_t TFUFRE:1;
2415 uint32_t:1;
2416 uint32_t TFFFRE:1;
2417 uint32_t TFFFDIRS:1;
2418 uint32_t:4;
2419 uint32_t RFOFRE:1;
2420 uint32_t:1;
2421 uint32_t RFDFRE:1;
2422 uint32_t RFDFDIRS:1;
2423 uint32_t:16;
2424 } B;
2425 } RSER; /* DMA/Interrupt Request Select and Enable Register */
2426
2427 union DSPI_PUSHR_tag {
2428 uint32_t R;
2429 struct {
2430 uint32_t CONT:1;
2431 uint32_t CTAS:3;
2432 uint32_t EOQ:1;
2433 uint32_t CTCNT:1;
2434 uint32_t:4;
2435 uint32_t PCS5:1;
2436 uint32_t PCS4:1;
2437 uint32_t PCS3:1;
2438 uint32_t PCS2:1;
2439 uint32_t PCS1:1;
2440 uint32_t PCS0:1;
2441 uint32_t TXDATA:16;
2442 } B;
2443 } PUSHR; /* PUSH TX FIFO Register */
2444
2445 union DSPI_POPR_tag {
2446 uint32_t R;
2447 struct {
2448 uint32_t:16;
2449 uint32_t RXDATA:16;
2450 } B;
2451 } POPR; /* POP RX FIFO Register */
2452
2453 union {
2454 uint32_t R;
2455 struct {
2456 uint32_t TXCMD:16;
2457 uint32_t TXDATA:16;
2458 } B;
2459 } TXFR[4]; /* Transmit FIFO Registers */
2460
2461 uint32_t DSPI_reserved_txf[12];
2462
2463 union {
2464 uint32_t R;
2465 struct {
2466 uint32_t:16;
2467 uint32_t RXDATA:16;
2468 } B;
2469 } RXFR[4]; /* Transmit FIFO Registers */
2470
2471 uint32_t DSPI_reserved_rxf[12];
2472
2473 union {
2474 uint32_t R;
2475 struct {
2476 uint32_t MTOE:1;
2477 uint32_t:1;
2478 uint32_t MTOCNT:6;
2479 uint32_t:4;
2480 uint32_t TXSS:1;
2481 uint32_t TPOL:1;
2482 uint32_t TRRE:1;
2483 uint32_t CID:1;
2484 uint32_t DCONT:1;
2485 uint32_t DSICTAS:3;
2486 uint32_t:6;
2487 uint32_t DPCS5:1;
2488 uint32_t DPCS4:1;
2489 uint32_t DPCS3:1;
2490 uint32_t DPCS2:1;
2491 uint32_t DPCS1:1;
2492 uint32_t DPCS0:1;
2493 } B;
2494 } DSICR; /* DSI Configuration Register */
2495
2496 union {
2497 uint32_t R;
2498 struct {
2499 uint32_t:16;
2500 uint32_t SER_DATA:16;
2501 } B;
2502 } SDR; /* DSI Serialization Data Register */
2503
2504 union {
2505 uint32_t R;
2506 struct {
2507 uint32_t:16;
2508 uint32_t ASER_DATA:16;
2509 } B;
2510 } ASDR; /* DSI Alternate Serialization Data Register */
2511
2512 union {
2513 uint32_t R;
2514 struct {
2515 uint32_t:16;
2516 uint32_t COMP_DATA:16;
2517 } B;
2518 } COMPR; /* DSI Transmit Comparison Register */
2519
2520 union {
2521 uint32_t R;
2522 struct {
2523 uint32_t:16;
2524 uint32_t DESER_DATA:16;
2525 } B;
2526 } DDR; /* DSI deserialization Data Register */
2527
2528 };
2529/****************************************************************************/
2530/* MODULE : eSCI */
2531/****************************************************************************/
2532 struct ESCI_tag {
2533 union ESCI_CR1_tag {
2534 uint32_t R;
2535 struct {
2536 uint32_t:3;
2537 uint32_t SBR:13;
2538 uint32_t LOOPS:1;
2539 uint32_t SCISDOZ:1;
2540 uint32_t RSRC:1;
2541 uint32_t M:1;
2542 uint32_t WAKE:1;
2543 uint32_t ILT:1;
2544 uint32_t PE:1;
2545 uint32_t PT:1;
2546 uint32_t TIE:1;
2547 uint32_t TCIE:1;
2548 uint32_t RIE:1;
2549 uint32_t ILIE:1;
2550 uint32_t TE:1;
2551 uint32_t RE:1;
2552 uint32_t RWU:1;
2553 uint32_t SBK:1;
2554 } B;
2555 } CR1; /* Control Register 1 */
2556
2557 union ESCI_CR2_tag {
2558 uint16_t R;
2559 struct {
2560 uint16_t MDIS:1;
2561 uint16_t FBR:1;
2562 uint16_t BSTP:1;
2563 uint16_t IEBERR:1;
2564 uint16_t RXDMA:1;
2565 uint16_t TXDMA:1;
2566 uint16_t BRK13:1;
2567 uint16_t:1;
2568 uint16_t BESM13:1;
2569 uint16_t SBSTP:1;
2570 uint16_t:2;
2571 uint16_t ORIE:1;
2572 uint16_t NFIE:1;
2573 uint16_t FEIE:1;
2574 uint16_t PFIE:1;
2575 } B;
2576 } CR2; /* Control Register 2 */
2577
2578 union ESCI_DR_tag {
2579 uint16_t R;
2580 struct {
2581 uint16_t R8:1;
2582 uint16_t T8:1;
2583 uint16_t:6;
2584 uint8_t D;
2585 } B;
2586 } DR; /* Data Register */
2587
2588 union ESCI_SR_tag {
2589 uint32_t R;
2590 struct {
2591 uint32_t TDRE:1;
2592 uint32_t TC:1;
2593 uint32_t RDRF:1;
2594 uint32_t IDLE:1;
2595 uint32_t OR:1;
2596 uint32_t NF:1;
2597 uint32_t FE:1;
2598 uint32_t PF:1;
2599 uint32_t:3;
2600 uint32_t BERR:1;
2601 uint32_t:3;
2602 uint32_t RAF:1;
2603 uint32_t RXRDY:1;
2604 uint32_t TXRDY:1;
2605 uint32_t LWAKE:1;
2606 uint32_t STO:1;
2607 uint32_t PBERR:1;
2608 uint32_t CERR:1;
2609 uint32_t CKERR:1;
2610 uint32_t FRC:1;
2611 uint32_t:7;
2612 uint32_t OVFL:1;
2613 } B;
2614 } SR; /* Status Register */
2615
2616 union {
2617 uint32_t R;
2618 struct {
2619 uint32_t LRES:1;
2620 uint32_t WU:1;
2621 uint32_t WUD0:1;
2622 uint32_t WUD1:1;
2623 uint32_t LDBG:1;
2624 uint32_t DSF:1;
2625 uint32_t PRTY:1;
2626 uint32_t LIN:1;
2627 uint32_t RXIE:1;
2628 uint32_t TXIE:1;
2629 uint32_t WUIE:1;
2630 uint32_t STIE:1;
2631 uint32_t PBIE:1;
2632 uint32_t CIE:1;
2633 uint32_t CKIE:1;
2634 uint32_t FCIE:1;
2635 uint32_t:7;
2636 uint32_t OFIE:1;
2637 uint32_t:8;
2638 } B;
2639 } LCR; /* LIN Control Register */
2640
2641 union {
2642 uint32_t R;
2643 } LTR; /* LIN Transmit Register */
2644
2645 union {
2646 uint32_t R;
2647 } LRR; /* LIN Recieve Register */
2648
2649 union {
2650 uint32_t R;
2651 } LPR; /* LIN CRC Polynom Register */
2652
2653 };
2654/****************************************************************************/
2655/* MODULE : FlexCAN */
2656/****************************************************************************/
2657 struct FLEXCAN2_tag {
2658 union {
2659 uint32_t R;
2660 struct {
2661 uint32_t MDIS:1;
2662 uint32_t FRZ:1;
2663 uint32_t:1;
2664 uint32_t HALT:1;
2665 uint32_t NOTRDY:1;
2666 uint32_t:1;
2667 uint32_t SOFTRST:1;
2668 uint32_t FRZACK:1;
2669 uint32_t:1;
2670 uint32_t:1;
2671
2672 uint32_t WRNEN:1;
2673
2674 uint32_t MDISACK:1;
2675 uint32_t:1;
2676 uint32_t:1;
2677
2678 uint32_t SRXDIS:1;
2679 uint32_t MBFEN:1;
2680 uint32_t:10;
2681
2682 uint32_t MAXMB:6;
2683 } B;
2684 } MCR; /* Module Configuration Register */
2685
2686 union {
2687 uint32_t R;
2688 struct {
2689 uint32_t PRESDIV:8;
2690 uint32_t RJW:2;
2691 uint32_t PSEG1:3;
2692 uint32_t PSEG2:3;
2693 uint32_t BOFFMSK:1;
2694 uint32_t ERRMSK:1;
2695 uint32_t CLKSRC:1;
2696 uint32_t LPB:1;
2697
2698 uint32_t TWRNMSK:1;
2699 uint32_t RWRNMSK:1;
2700 uint32_t:2;
2701
2702 uint32_t SMP:1;
2703 uint32_t BOFFREC:1;
2704 uint32_t TSYN:1;
2705 uint32_t LBUF:1;
2706 uint32_t LOM:1;
2707 uint32_t PROPSEG:3;
2708 } B;
2709 } CR; /* Control Register */
2710
2711 union {
2712 uint32_t R;
2713 } TIMER; /* Free Running Timer */
2714 int32_t FLEXCAN_reserved00;
2715
2716 union {
2717 uint32_t R;
2718 struct {
2719 uint32_t:3;
2720 uint32_t MI:29;
2721 } B;
2722 } RXGMASK; /* RX Global Mask */
2723
2724 union {
2725 uint32_t R;
2726 struct {
2727 uint32_t:3;
2728 uint32_t MI:29;
2729 } B;
2730 } RX14MASK; /* RX 14 Mask */
2731
2732 union {
2733 uint32_t R;
2734 struct {
2735 uint32_t:3;
2736 uint32_t MI:29;
2737 } B;
2738 } RX15MASK; /* RX 15 Mask */
2739
2740 union {
2741 uint32_t R;
2742 struct {
2743 uint32_t:16;
2744 uint32_t RXECNT:8;
2745 uint32_t TXECNT:8;
2746 } B;
2747 } ECR; /* Error Counter Register */
2748
2749 union {
2750 uint32_t R;
2751 struct {
2752 uint32_t:14;
2753
2754 uint32_t TWRNINT:1;
2755 uint32_t RWRNINT:1;
2756
2757 uint32_t BIT1ERR:1;
2758 uint32_t BIT0ERR:1;
2759 uint32_t ACKERR:1;
2760 uint32_t CRCERR:1;
2761 uint32_t FRMERR:1;
2762 uint32_t STFERR:1;
2763 uint32_t TXWRN:1;
2764 uint32_t RXWRN:1;
2765 uint32_t IDLE:1;
2766 uint32_t TXRX:1;
2767 uint32_t FLTCONF:2;
2768 uint32_t:1;
2769 uint32_t BOFFINT:1;
2770 uint32_t ERRINT:1;
2771 uint32_t:1;
2772 } B;
2773 } ESR; /* Error and Status Register */
2774
2775 union {
2776 uint32_t R;
2777 struct {
2778 uint32_t BUF63M:1;
2779 uint32_t BUF62M:1;
2780 uint32_t BUF61M:1;
2781 uint32_t BUF60M:1;
2782 uint32_t BUF59M:1;
2783 uint32_t BUF58M:1;
2784 uint32_t BUF57M:1;
2785 uint32_t BUF56M:1;
2786 uint32_t BUF55M:1;
2787 uint32_t BUF54M:1;
2788 uint32_t BUF53M:1;
2789 uint32_t BUF52M:1;
2790 uint32_t BUF51M:1;
2791 uint32_t BUF50M:1;
2792 uint32_t BUF49M:1;
2793 uint32_t BUF48M:1;
2794 uint32_t BUF47M:1;
2795 uint32_t BUF46M:1;
2796 uint32_t BUF45M:1;
2797 uint32_t BUF44M:1;
2798 uint32_t BUF43M:1;
2799 uint32_t BUF42M:1;
2800 uint32_t BUF41M:1;
2801 uint32_t BUF40M:1;
2802 uint32_t BUF39M:1;
2803 uint32_t BUF38M:1;
2804 uint32_t BUF37M:1;
2805 uint32_t BUF36M:1;
2806 uint32_t BUF35M:1;
2807 uint32_t BUF34M:1;
2808 uint32_t BUF33M:1;
2809 uint32_t BUF32M:1;
2810 } B;
2811 } IMRH; /* Interruput Masks Register */
2812
2813 union {
2814 uint32_t R;
2815 struct {
2816 uint32_t BUF31M:1;
2817 uint32_t BUF30M:1;
2818 uint32_t BUF29M:1;
2819 uint32_t BUF28M:1;
2820 uint32_t BUF27M:1;
2821 uint32_t BUF26M:1;
2822 uint32_t BUF25M:1;
2823 uint32_t BUF24M:1;
2824 uint32_t BUF23M:1;
2825 uint32_t BUF22M:1;
2826 uint32_t BUF21M:1;
2827 uint32_t BUF20M:1;
2828 uint32_t BUF19M:1;
2829 uint32_t BUF18M:1;
2830 uint32_t BUF17M:1;
2831 uint32_t BUF16M:1;
2832 uint32_t BUF15M:1;
2833 uint32_t BUF14M:1;
2834 uint32_t BUF13M:1;
2835 uint32_t BUF12M:1;
2836 uint32_t BUF11M:1;
2837 uint32_t BUF10M:1;
2838 uint32_t BUF09M:1;
2839 uint32_t BUF08M:1;
2840 uint32_t BUF07M:1;
2841 uint32_t BUF06M:1;
2842 uint32_t BUF05M:1;
2843 uint32_t BUF04M:1;
2844 uint32_t BUF03M:1;
2845 uint32_t BUF02M:1;
2846 uint32_t BUF01M:1;
2847 uint32_t BUF00M:1;
2848 } B;
2849 } IMRL; /* Interruput Masks Register */
2850
2851 union {
2852 uint32_t R;
2853 struct {
2854 uint32_t BUF63I:1;
2855 uint32_t BUF62I:1;
2856 uint32_t BUF61I:1;
2857 uint32_t BUF60I:1;
2858 uint32_t BUF59I:1;
2859 uint32_t BUF58I:1;
2860 uint32_t BUF57I:1;
2861 uint32_t BUF56I:1;
2862 uint32_t BUF55I:1;
2863 uint32_t BUF54I:1;
2864 uint32_t BUF53I:1;
2865 uint32_t BUF52I:1;
2866 uint32_t BUF51I:1;
2867 uint32_t BUF50I:1;
2868 uint32_t BUF49I:1;
2869 uint32_t BUF48I:1;
2870 uint32_t BUF47I:1;
2871 uint32_t BUF46I:1;
2872 uint32_t BUF45I:1;
2873 uint32_t BUF44I:1;
2874 uint32_t BUF43I:1;
2875 uint32_t BUF42I:1;
2876 uint32_t BUF41I:1;
2877 uint32_t BUF40I:1;
2878 uint32_t BUF39I:1;
2879 uint32_t BUF38I:1;
2880 uint32_t BUF37I:1;
2881 uint32_t BUF36I:1;
2882 uint32_t BUF35I:1;
2883 uint32_t BUF34I:1;
2884 uint32_t BUF33I:1;
2885 uint32_t BUF32I:1;
2886 } B;
2887 } IFRH; /* Interruput Flag Register */
2888
2889 union {
2890 uint32_t R;
2891 struct {
2892 uint32_t BUF31I:1;
2893 uint32_t BUF30I:1;
2894 uint32_t BUF29I:1;
2895 uint32_t BUF28I:1;
2896 uint32_t BUF27I:1;
2897 uint32_t BUF26I:1;
2898 uint32_t BUF25I:1;
2899 uint32_t BUF24I:1;
2900 uint32_t BUF23I:1;
2901 uint32_t BUF22I:1;
2902 uint32_t BUF21I:1;
2903 uint32_t BUF20I:1;
2904 uint32_t BUF19I:1;
2905 uint32_t BUF18I:1;
2906 uint32_t BUF17I:1;
2907 uint32_t BUF16I:1;
2908 uint32_t BUF15I:1;
2909 uint32_t BUF14I:1;
2910 uint32_t BUF13I:1;
2911 uint32_t BUF12I:1;
2912 uint32_t BUF11I:1;
2913 uint32_t BUF10I:1;
2914 uint32_t BUF09I:1;
2915 uint32_t BUF08I:1;
2916 uint32_t BUF07I:1;
2917 uint32_t BUF06I:1;
2918 uint32_t BUF05I:1;
2919 uint32_t BUF04I:1;
2920 uint32_t BUF03I:1;
2921 uint32_t BUF02I:1;
2922 uint32_t BUF01I:1;
2923 uint32_t BUF00I:1;
2924 } B;
2925 } IFRL; /* Interruput Flag Register */
2926
2927 uint32_t flexcan2_reserved2[19];
2928
2929 struct canbuf_t {
2930 union {
2931 uint32_t R;
2932 struct {
2933 uint32_t:4;
2934 uint32_t CODE:4;
2935 uint32_t:1;
2936 uint32_t SRR:1;
2937 uint32_t IDE:1;
2938 uint32_t RTR:1;
2939 uint32_t LENGTH:4;
2940 uint32_t TIMESTAMP:16;
2941 } B;
2942 } CS;
2943
2944 union {
2945 uint32_t R;
2946 struct {
2947 uint32_t:3;
2948 uint32_t STD_ID:11;
2949 uint32_t EXT_ID:18;
2950 } B;
2951 } ID;
2952
2953 union {
2954 uint8_t B[8]; /* Data buffer in Bytes (8 bits) */
2955 uint16_t H[4]; /* Data buffer in Half-words (16 bits) */
2956 uint32_t W[2]; /* Data buffer in words (32 bits) */
2957 uint32_t R[2]; /* Data buffer in words (32 bits) */
2958 } DATA;
2959
2960 } BUF[64];
2961
2962 uint32_t flexcan2_reserved3[256];
2963
2964 union {
2965 uint32_t R;
2966 struct {
2967 uint32_t:3;
2968 uint32_t MI:29;
2969 } B;
2970 } RXIMR[64]; /* RX Individual Mask Registers */
2971
2972 };
2973/****************************************************************************/
2974/* MODULE : FEC */
2975/****************************************************************************/
2976 struct FEC_tag {
2977
2978 uint32_t fec_reserved_start[0x1];
2979
2980 union {
2981 uint32_t R;
2982 struct {
2983 uint32_t HBERR:1;
2984 uint32_t BABR:1;
2985 uint32_t BABT:1;
2986 uint32_t GRA:1;
2987 uint32_t TXF:1;
2988 uint32_t TXB:1;
2989 uint32_t RXF:1;
2990 uint32_t RXB:1;
2991 uint32_t MII:1;
2992 uint32_t EBERR:1;
2993 uint32_t LC:1;
2994 uint32_t RL:1;
2995 uint32_t UN:1;
2996 uint32_t:19;
2997 } B;
2998 } EIR; /* Interrupt Event Register */
2999
3000 union {
3001 uint32_t R;
3002 struct {
3003 uint32_t HBERRM:1;
3004 uint32_t BABRM:1;
3005 uint32_t BABTM:1;
3006 uint32_t GRAM:1;
3007 uint32_t TXFM:1;
3008 uint32_t TXBM:1;
3009 uint32_t RXFM:1;
3010 uint32_t RXBM:1;
3011 uint32_t MIIM:1;
3012 uint32_t EBERRM:1;
3013 uint32_t LCM:1;
3014 uint32_t RLM:1;
3015 uint32_t UNM:1;
3016 uint32_t:19;
3017 } B;
3018 } EIMR; /* Interrupt Mask Register */
3019
3020 uint32_t fec_reserved_eimr;
3021
3022 union {
3023 uint32_t R;
3024 struct {
3025 uint32_t:7;
3026 uint32_t R_DES_ACTIVE:1;
3027 uint32_t:24;
3028 } B;
3029 } RDAR; /* Receive Descriptor Active Register */
3030
3031 union {
3032 uint32_t R;
3033 struct {
3034 uint32_t:7;
3035 uint32_t X_DES_ACTIVE:1;
3036 uint32_t:24;
3037 } B;
3038 } TDAR; /* Transmit Descriptor Active Register */
3039
3040 uint32_t fec_reserved_tdar[3];
3041
3042 union {
3043 uint32_t R;
3044 struct {
3045 uint32_t:30;
3046 uint32_t ETHER_EN:1;
3047 uint32_t RESET:1;
3048 } B;
3049 } ECR; /* Ethernet Control Register */
3050
3051 uint32_t fec_reserved_ecr[6];
3052
3053 union {
3054 uint32_t R;
3055 struct {
3056 uint32_t ST:2;
3057 uint32_t CP:2;
3058 uint32_t PA:5;
3059 uint32_t RA:5;
3060 uint32_t TA:2;
3061 uint32_t DATA:16;
3062 } B;
3063 } MDATA; /* MII Data Register */
3064
3065 union {
3066 uint32_t R;
3067 struct {
3068 uint32_t:24;
3069 uint32_t DIS_PREAMBLE:1;
3070 uint32_t MII_SPEED:6;
3071 uint32_t:1;
3072 } B;
3073 } MSCR; /* MII Speed Control Register */
3074
3075 uint32_t fec_reserved_mscr[7];
3076
3077 union {
3078 uint32_t R;
3079 struct {
3080 uint32_t MIB_DISABLE:1;
3081 uint32_t MIB_IDLE:1;
3082 uint32_t:30;
3083 } B;
3084 } MIBC; /* MIB Control Register */
3085
3086 uint32_t fec_reserved_mibc[7];
3087
3088 union {
3089 uint32_t R;
3090 struct {
3091 uint32_t:5;
3092 uint32_t MAX_FL:11;
3093 uint32_t:10;
3094 uint32_t FCE:1;
3095 uint32_t BC_REJ:1;
3096 uint32_t PROM:1;
3097 uint32_t MII_MODE:1;
3098 uint32_t DRT:1;
3099 uint32_t LOOP:1;
3100 } B;
3101 } RCR; /* Receive Control Register */
3102
3103 uint32_t fec_reserved_rcr[15];
3104
3105 union {
3106 uint32_t R;
3107 struct {
3108 uint32_t:27;
3109 uint32_t RFC_PAUSE:1;
3110 uint32_t TFC_PAUSE:1;
3111 uint32_t FDEN:1;
3112 uint32_t HBC:1;
3113 uint32_t GTS:1;
3114 } B;
3115 } TCR; /* Transmit Control Register */
3116
3117 uint32_t fec_reserved_tcr[7];
3118
3119 union {
3120 uint32_t R;
3121 struct {
3122 uint32_t PADDR1:32;
3123 } B;
3124 } PALR; /* Physical Address Low Register */
3125
3126 union {
3127 uint32_t R;
3128 struct {
3129 uint32_t PADDR2:16;
3130 uint32_t TYPE:16;
3131 } B;
3132 } PAUR; /* Physical Address High + Type Register */
3133
3134 union {
3135 uint32_t R;
3136 struct {
3137 uint32_t OPCODE:16;
3138 uint32_t PAUSE_DUR:16;
3139 } B;
3140 } OPD; /* Opcode/Pause Duration Register */
3141
3142 uint32_t fec_reserved_opd[10];
3143
3144 union {
3145 uint32_t R;
3146 struct {
3147 uint32_t IADDR1:32;
3148 } B;
3149 } IAUR; /* Descriptor Individual Upper Address Register */
3150
3151 union {
3152 uint32_t R;
3153 struct {
3154 uint32_t IADDR2:32;
3155 } B;
3156 } IALR; /* Descriptor Individual Lower Address Register */
3157
3158 union {
3159 uint32_t R;
3160 struct {
3161 uint32_t GADDR1:32;
3162 } B;
3163 } GAUR; /* Descriptor Group Upper Address Register */
3164
3165 union {
3166 uint32_t R;
3167 struct {
3168 uint32_t GADDR2:32;
3169 } B;
3170 } GALR; /* Descriptor Group Lower Address Register */
3171
3172 uint32_t fec_reserved_galr[7];
3173
3174 union {
3175 uint32_t R;
3176 struct {
3177 uint32_t:30;
3178 uint32_t X_WMRK:2;
3179 } B;
3180 } TFWR; /* FIFO Transmit FIFO Watermark Register */
3181
3182 uint32_t fec_reserved_tfwr;
3183
3184 union {
3185 uint32_t R;
3186 struct {
3187 uint32_t:22;
3188 uint32_t R_BOUND:8;
3189 uint32_t:2;
3190 } B;
3191 } FRBR; /* FIFO Receive Bound Register */
3192
3193 union {
3194 uint32_t R;
3195 struct {
3196 uint32_t:22;
3197 uint32_t R_FSTART:8;
3198 uint32_t:2;
3199 } B;
3200 } FRSR; /* FIFO Receive Start Register */
3201
3202 uint32_t fec_reserved_frsr[11];
3203
3204 union {
3205 uint32_t R;
3206 struct {
3207 uint32_t R_DES_START:30;
3208 uint32_t:2;
3209 } B;
3210 } ERDSR; /* Receive Descriptor Ring Start Register */
3211
3212 union {
3213 uint32_t R;
3214 struct {
3215 uint32_t X_DES_START:30;
3216 uint32_t:2;
3217 } B;
3218 } ETDSR; /* Transmit Descriptor Ring Start Register */
3219
3220 union {
3221 uint32_t R;
3222 struct {
3223 uint32_t:21;
3224 uint32_t R_BUF_SIZE:7;
3225 uint32_t:4;
3226 } B;
3227 } EMRBR; /* Receive Buffer Size Register */
3228
3229 uint32_t fec_reserved_emrbr[29];
3230
3231 union {
3232 uint32_t R;
3233 } RMON_T_DROP; /* Count of frames not counted correctly */
3234
3235 union {
3236 uint32_t R;
3237 } RMON_T_PACKETS; /* RMON Tx packet count */
3238
3239 union {
3240 uint32_t R;
3241 } RMON_T_BC_PKT; /* RMON Tx Broadcast Packets */
3242
3243 union {
3244 uint32_t R;
3245 } RMON_T_MC_PKT; /* RMON Tx Multicast Packets */
3246
3247 union {
3248 uint32_t R;
3249 } RMON_T_CRC_ALIGN; /* RMON Tx Packets w CRC/Align error */
3250
3251 union {
3252 uint32_t R;
3253 } RMON_T_UNDERSIZE; /* RMON Tx Packets < 64 bytes, good crc */
3254
3255 union {
3256 uint32_t R;
3257 } RMON_T_OVERSIZE; /* RMON Tx Packets > MAX_FL bytes, good crc */
3258
3259 union {
3260 uint32_t R;
3261 } RMON_T_FRAG; /* RMON Tx Packets < 64 bytes, bad crc */
3262
3263 union {
3264 uint32_t R;
3265 } RMON_T_JAB; /* RMON Tx Packets > MAX_FL bytes, bad crc */
3266
3267 union {
3268 uint32_t R;
3269 } RMON_T_COL; /* RMON Tx collision count */
3270
3271 union {
3272 uint32_t R;
3273 } RMON_T_P64; /* RMON Tx 64 byte packets */
3274
3275 union {
3276 uint32_t R;
3277 } RMON_T_P65TO127; /* RMON Tx 65 to 127 byte packets */
3278
3279 union {
3280 uint32_t R;
3281 } RMON_T_P128TO255; /* RMON Tx 128 to 255 byte packets */
3282
3283 union {
3284 uint32_t R;
3285 } RMON_T_P256TO511; /* RMON Tx 256 to 511 byte packets */
3286
3287 union {
3288 uint32_t R;
3289 } RMON_T_P512TO1023; /* RMON Tx 512 to 1023 byte packets */
3290
3291 union {
3292 uint32_t R;
3293 } RMON_T_P1024TO2047; /* RMON Tx 1024 to 2047 byte packets */
3294
3295 union {
3296 uint32_t R;
3297 } RMON_T_P_GTE2048; /* RMON Tx packets w > 2048 bytes */
3298
3299 union {
3300 uint32_t R;
3301 } RMON_T_OCTETS; /* RMON Tx Octets */
3302
3303 union {
3304 uint32_t R;
3305 } IEEE_T_DROP; /* Count of frames not counted correctly */
3306
3307 union {
3308 uint32_t R;
3309 } IEEE_T_FRAME_OK; /* Frames Transmitted OK */
3310
3311 union {
3312 uint32_t R;
3313 } IEEE_T_1COL; /* Frames Transmitted with Single Collision */
3314
3315 union {
3316 uint32_t R;
3317 } IEEE_T_MCOL; /* Frames Transmitted with Multiple Collisions */
3318
3319 union {
3320 uint32_t R;
3321 } IEEE_T_DEF; /* Frames Transmitted after Deferral Delay */
3322
3323 union {
3324 uint32_t R;
3325 } IEEE_T_LCOL; /* Frames Transmitted with Late Collision */
3326
3327 union {
3328 uint32_t R;
3329 } IEEE_T_EXCOL; /* Frames Transmitted with Excessive Collisions */
3330
3331 union {
3332 uint32_t R;
3333 } IEEE_T_MACERR; /* Frames Transmitted with Tx FIFO Underrun */
3334
3335 union {
3336 uint32_t R;
3337 } IEEE_T_CSERR; /* Frames Transmitted with Carrier Sense Error */
3338
3339 union {
3340 uint32_t R;
3341 } IEEE_T_SQE; /* Frames Transmitted with SQE Error */
3342
3343 union {
3344 uint32_t R;
3345 } IEEE_T_FDXFC; /* Flow Control Pause frames transmitted */
3346
3347 union {
3348 uint32_t R;
3349 } IEEE_T_OCTETS_OK; /* Octet count for Frames Transmitted w/o Error */
3350
3351 uint32_t fec_reserved_rmon_t_octets_ok[2];
3352
3353 union {
3354 uint32_t R;
3355 } RMON_R_DROP; /* Count of frames not counted correctly */
3356
3357 union {
3358 uint32_t R;
3359 } RMON_R_PACKETS; /* RMON Rx packet count */
3360
3361 union {
3362 uint32_t R;
3363 } RMON_R_BC_PKT; /* RMON Rx Broadcast Packets */
3364
3365 union {
3366 uint32_t R;
3367 } RMON_R_MC_PKT; /* RMON Rx Multicast Packets */
3368
3369 union {
3370 uint32_t R;
3371 } RMON_R_CRC_ALIGN; /* RMON Rx Packets w CRC/Align error */
3372
3373 union {
3374 uint32_t R;
3375 } RMON_R_UNDERSIZE; /* RMON Rx Packets < 64 bytes, good crc */
3376
3377 union {
3378 uint32_t R;
3379 } RMON_R_OVERSIZE; /* RMON Rx Packets > MAX_FL bytes, good crc */
3380
3381 union {
3382 uint32_t R;
3383 } RMON_R_FRAG; /* RMON Rx Packets < 64 bytes, bad crc */
3384
3385 union {
3386 uint32_t R;
3387 } RMON_R_JAB; /* RMON Rx Packets > MAX_FL bytes, bad crc */
3388
3389 uint32_t fec_reserved_rmon_r_jab;
3390
3391 union {
3392 uint32_t R;
3393 } RMON_R_P64; /* RMON Rx 64 byte packets */
3394
3395 union {
3396 uint32_t R;
3397 } RMON_R_P65TO127; /* RMON Rx 65 to 127 byte packets */
3398
3399 union {
3400 uint32_t R;
3401 } RMON_R_P128TO255; /* RMON Rx 128 to 255 byte packets */
3402
3403 union {
3404 uint32_t R;
3405 } RMON_R_P256TO511; /* RMON Rx 256 to 511 byte packets */
3406
3407 union {
3408 uint32_t R;
3409 } RMON_R_P512TO1023; /* RMON Rx 512 to 1023 byte packets */
3410
3411 union {
3412 uint32_t R;
3413 } RMON_R_P1024TO2047; /* RMON Rx 1024 to 2047 byte packets */
3414
3415 union {
3416 uint32_t R;
3417 } RMON_R_P_GTE2048; /* RMON Rx packets w > 2048 bytes */
3418
3419 union {
3420 uint32_t R;
3421 } RMON_R_OCTETS; /* RMON Rx Octets */
3422
3423 union {
3424 uint32_t R;
3425 } IEEE_R_DROP; /* Count of frames not counted correctly */
3426
3427 union {
3428 uint32_t R;
3429 } IEEE_R_FRAME_OK; /* Frames Received OK */
3430
3431 union {
3432 uint32_t R;
3433 } IEEE_R_CRC; /* Frames Received with CRC Error */
3434
3435 union {
3436 uint32_t R;
3437 } IEEE_R_ALIGN; /* Frames Received with Alignment Error */
3438
3439 union {
3440 uint32_t R;
3441 } IEEE_R_MACERR; /* Receive Fifo Overflow count */
3442
3443 union {
3444 uint32_t R;
3445 } IEEE_R_FDXFC; /* Flow Control Pause frames received */
3446
3447 union {
3448 uint32_t R;
3449 } IEEE_R_OCTETS_OK; /* Octet count for Frames Rcvd w/o Error */
3450
3451 };
3452/****************************************************************************/
3453/* MODULE : FlexRay */
3454/****************************************************************************/
3455
3456 typedef union uMVR {
3457 uint16_t R;
3458 struct {
3459 uint16_t CHIVER:8; /* CHI Version Number */
3460 uint16_t PEVER:8; /* PE Version Number */
3461 } B;
3462 } MVR_t;
3463
3464 typedef union uMCR {
3465 uint16_t R;
3466 struct {
3467 uint16_t MEN:1; /* module enable */
3468 uint16_t:1;
3469 uint16_t SCMD:1; /* single channel mode */
3470 uint16_t CHB:1; /* channel B enable */
3471 uint16_t CHA:1; /* channel A enable */
3472 uint16_t SFFE:1; /* synchronization frame filter enable */
3473 uint16_t:5;
3474 uint16_t CLKSEL:1; /* protocol engine clock source select */
3475 uint16_t PRESCALE:3; /* protocol engine clock prescaler */
3476 uint16_t:1;
3477 } B;
3478 } MCR_t;
3479 typedef union uSTBSCR {
3480 uint16_t R;
3481 struct {
3482 uint16_t WMD:1; /* write mode */
3483 uint16_t STBSSEL:7; /* strobe signal select */
3484 uint16_t:3;
3485 uint16_t ENB:1; /* strobe signal enable */
3486 uint16_t:2;
3487 uint16_t STBPSEL:2; /* strobe port select */
3488 } B;
3489 } STBSCR_t;
3490 typedef union uSTBPCR {
3491 uint16_t R;
3492 struct {
3493 uint16_t:12;
3494 uint16_t STB3EN:1; /* strobe port enable */
3495 uint16_t STB2EN:1; /* strobe port enable */
3496 uint16_t STB1EN:1; /* strobe port enable */
3497 uint16_t STB0EN:1; /* strobe port enable */
3498 } B;
3499 } STBPCR_t;
3500
3501 typedef union uMBDSR {
3502 uint16_t R;
3503 struct {
3504 uint16_t:1;
3505 uint16_t MBSEG2DS:7; /* message buffer segment 2 data size */
3506 uint16_t:1;
3507 uint16_t MBSEG1DS:7; /* message buffer segment 1 data size */
3508 } B;
3509 } MBDSR_t;
3510 typedef union uMBSSUTR {
3511 uint16_t R;
3512 struct {
3513
3514 uint16_t:1;
3515 uint16_t LAST_MB_SEG1:7; /* last message buffer control register for message buffer segment 1 */
3516 uint16_t:1;
3517 uint16_t LAST_MB_UTIL:7; /* last message buffer utilized */
3518 } B;
3519 } MBSSUTR_t;
3520
3521 typedef union uPOCR {
3522 uint16_t R;
3523 uint8_t byte[2];
3524 struct {
3525 uint16_t WME:1; /* write mode external correction command */
3526 uint16_t:3;
3527 uint16_t EOC_AP:2; /* external offset correction application */
3528 uint16_t ERC_AP:2; /* external rate correction application */
3529 uint16_t BSY:1; /* command write busy / write mode command */
3530 uint16_t:3;
3531 uint16_t POCCMD:4; /* protocol command */
3532 } B;
3533 } POCR_t;
3534/* protocol commands */
3535 typedef union uGIFER {
3536 uint16_t R;
3537 struct {
3538 uint16_t MIF:1; /* module interrupt flag */
3539 uint16_t PRIF:1; /* protocol interrupt flag */
3540 uint16_t CHIF:1; /* CHI interrupt flag */
3541 uint16_t WKUPIF:1; /* wakeup interrupt flag */
3542 uint16_t FNEBIF:1; /* receive FIFO channel B not empty interrupt flag */
3543 uint16_t FNEAIF:1; /* receive FIFO channel A not empty interrupt flag */
3544 uint16_t RBIF:1; /* receive message buffer interrupt flag */
3545 uint16_t TBIF:1; /* transmit buffer interrupt flag */
3546 uint16_t MIE:1; /* module interrupt enable */
3547 uint16_t PRIE:1; /* protocol interrupt enable */
3548 uint16_t CHIE:1; /* CHI interrupt enable */
3549 uint16_t WKUPIE:1; /* wakeup interrupt enable */
3550 uint16_t FNEBIE:1; /* receive FIFO channel B not empty interrupt enable */
3551 uint16_t FNEAIE:1; /* receive FIFO channel A not empty interrupt enable */
3552 uint16_t RBIE:1; /* receive message buffer interrupt enable */
3553 uint16_t TBIE:1; /* transmit buffer interrupt enable */
3554 } B;
3555 } GIFER_t;
3556 typedef union uPIFR0 {
3557 uint16_t R;
3558 struct {
3559 uint16_t FATLIF:1; /* fatal protocol error interrupt flag */
3560 uint16_t INTLIF:1; /* internal protocol error interrupt flag */
3561 uint16_t ILCFIF:1; /* illegal protocol configuration flag */
3562 uint16_t CSAIF:1; /* cold start abort interrupt flag */
3563 uint16_t MRCIF:1; /* missing rate correctio interrupt flag */
3564 uint16_t MOCIF:1; /* missing offset correctio interrupt flag */
3565 uint16_t CCLIF:1; /* clock correction limit reached interrupt flag */
3566 uint16_t MXSIF:1; /* max sync frames detected interrupt flag */
3567 uint16_t MTXIF:1; /* media access test symbol received flag */
3568 uint16_t LTXBIF:1; /* pdLatestTx violation on channel B interrupt flag */
3569 uint16_t LTXAIF:1; /* pdLatestTx violation on channel A interrupt flag */
3570 uint16_t TBVBIF:1; /* Transmission across boundary on channel B Interrupt Flag */
3571 uint16_t TBVAIF:1; /* Transmission across boundary on channel A Interrupt Flag */
3572 uint16_t TI2IF:1; /* timer 2 expired interrupt flag */
3573 uint16_t TI1IF:1; /* timer 1 expired interrupt flag */
3574 uint16_t CYSIF:1; /* cycle start interrupt flag */
3575 } B;
3576 } PIFR0_t;
3577 typedef union uPIFR1 {
3578 uint16_t R;
3579 struct {
3580 uint16_t EMCIF:1; /* error mode changed interrupt flag */
3581 uint16_t IPCIF:1; /* illegal protocol command interrupt flag */
3582 uint16_t PECFIF:1; /* protocol engine communication failure interrupt flag */
3583 uint16_t PSCIF:1; /* Protocol State Changed Interrupt Flag */
3584 uint16_t SSI3IF:1; /* slot status counter incremented interrupt flag */
3585 uint16_t SSI2IF:1; /* slot status counter incremented interrupt flag */
3586 uint16_t SSI1IF:1; /* slot status counter incremented interrupt flag */
3587 uint16_t SSI0IF:1; /* slot status counter incremented interrupt flag */
3588 uint16_t:2;
3589 uint16_t EVTIF:1; /* even cycle table written interrupt flag */
3590 uint16_t ODTIF:1; /* odd cycle table written interrupt flag */
3591 uint16_t:4;
3592 } B;
3593 } PIFR1_t;
3594 typedef union uPIER0 {
3595 uint16_t R;
3596 struct {
3597 uint16_t FATLIE:1; /* fatal protocol error interrupt enable */
3598 uint16_t INTLIE:1; /* internal protocol error interrupt interrupt enable */
3599 uint16_t ILCFIE:1; /* illegal protocol configuration interrupt enable */
3600 uint16_t CSAIE:1; /* cold start abort interrupt enable */
3601 uint16_t MRCIE:1; /* missing rate correctio interrupt enable */
3602 uint16_t MOCIE:1; /* missing offset correctio interrupt enable */
3603 uint16_t CCLIE:1; /* clock correction limit reached interrupt enable */
3604 uint16_t MXSIE:1; /* max sync frames detected interrupt enable */
3605 uint16_t MTXIE:1; /* media access test symbol received interrupt enable */
3606 uint16_t LTXBIE:1; /* pdLatestTx violation on channel B interrupt enable */
3607 uint16_t LTXAIE:1; /* pdLatestTx violation on channel A interrupt enable */
3608 uint16_t TBVBIE:1; /* Transmission across boundary on channel B Interrupt enable */
3609 uint16_t TBVAIE:1; /* Transmission across boundary on channel A Interrupt enable */
3610 uint16_t TI2IE:1; /* timer 2 expired interrupt enable */
3611 uint16_t TI1IE:1; /* timer 1 expired interrupt enable */
3612 uint16_t CYSIE:1; /* cycle start interrupt enable */
3613 } B;
3614 } PIER0_t;
3615 typedef union uPIER1 {
3616 uint16_t R;
3617 struct {
3618 uint16_t EMCIE:1; /* error mode changed interrupt enable */
3619 uint16_t IPCIE:1; /* illegal protocol command interrupt enable */
3620 uint16_t PECFIE:1; /* protocol engine communication failure interrupt enable */
3621 uint16_t PSCIE:1; /* Protocol State Changed Interrupt enable */
3622 uint16_t SSI3IE:1; /* slot status counter incremented interrupt enable */
3623 uint16_t SSI2IE:1; /* slot status counter incremented interrupt enable */
3624 uint16_t SSI1IE:1; /* slot status counter incremented interrupt enable */
3625 uint16_t SSI0IE:1; /* slot status counter incremented interrupt enable */
3626 uint16_t:2;
3627 uint16_t EVTIE:1; /* even cycle table written interrupt enable */
3628 uint16_t ODTIE:1; /* odd cycle table written interrupt enable */
3629 uint16_t:4;
3630 } B;
3631 } PIER1_t;
3632 typedef union uCHIERFR {
3633 uint16_t R;
3634 struct {
3635 uint16_t FRLBEF:1; /* flame lost channel B error flag */
3636 uint16_t FRLAEF:1; /* frame lost channel A error flag */
3637 uint16_t PCMIEF:1; /* command ignored error flag */
3638 uint16_t FOVBEF:1; /* receive FIFO overrun channel B error flag */
3639 uint16_t FOVAEF:1; /* receive FIFO overrun channel A error flag */
3640 uint16_t MSBEF:1; /* message buffer search error flag */
3641 uint16_t MBUEF:1; /* message buffer utilization error flag */
3642 uint16_t LCKEF:1; /* lock error flag */
3643 uint16_t DBLEF:1; /* double transmit message buffer lock error flag */
3644 uint16_t SBCFEF:1; /* system bus communication failure error flag */
3645 uint16_t FIDEF:1; /* frame ID error flag */
3646 uint16_t DPLEF:1; /* dynamic payload length error flag */
3647 uint16_t SPLEF:1; /* static payload length error flag */
3648 uint16_t NMLEF:1; /* network management length error flag */
3649 uint16_t NMFEF:1; /* network management frame error flag */
3650 uint16_t ILSAEF:1; /* illegal access error flag */
3651 } B;
3652 } CHIERFR_t;
3653 typedef union uMBIVEC {
3654 uint16_t R;
3655 struct {
3656
3657 uint16_t:1;
3658 uint16_t TBIVEC:7; /* transmit buffer interrupt vector */
3659 uint16_t:1;
3660 uint16_t RBIVEC:7; /* receive buffer interrupt vector */
3661 } B;
3662 } MBIVEC_t;
3663
3664 typedef union uPSR0 {
3665 uint16_t R;
3666 struct {
3667 uint16_t ERRMODE:2; /* error mode */
3668 uint16_t SLOTMODE:2; /* slot mode */
3669 uint16_t:1;
3670 uint16_t PROTSTATE:3; /* protocol state */
3671 uint16_t SUBSTATE:4; /* protocol sub state */
3672 uint16_t:1;
3673 uint16_t WAKEUPSTATUS:3; /* wakeup status */
3674 } B;
3675 } PSR0_t;
3676
3677/* protocol states */
3678/* protocol sub-states */
3679/* wakeup status */
3680 typedef union uPSR1 {
3681 uint16_t R;
3682 struct {
3683 uint16_t CSAA:1; /* cold start attempt abort flag */
3684 uint16_t SCP:1; /* cold start path */
3685 uint16_t:1;
3686 uint16_t REMCSAT:5; /* remanining coldstart attempts */
3687 uint16_t CPN:1; /* cold start noise path */
3688 uint16_t HHR:1; /* host halt request pending */
3689 uint16_t FRZ:1; /* freeze occured */
3690 uint16_t APTAC:5; /* allow passive to active counter */
3691 } B;
3692 } PSR1_t;
3693 typedef union uPSR2 {
3694 uint16_t R;
3695 struct {
3696 uint16_t NBVB:1; /* NIT boundary violation on channel B */
3697 uint16_t NSEB:1; /* NIT syntax error on channel B */
3698 uint16_t STCB:1; /* symbol window transmit conflict on channel B */
3699 uint16_t SBVB:1; /* symbol window boundary violation on channel B */
3700 uint16_t SSEB:1; /* symbol window syntax error on channel B */
3701 uint16_t MTB:1; /* media access test symbol MTS received on channel B */
3702 uint16_t NBVA:1; /* NIT boundary violation on channel A */
3703 uint16_t NSEA:1; /* NIT syntax error on channel A */
3704 uint16_t STCA:1; /* symbol window transmit conflict on channel A */
3705 uint16_t SBVA:1; /* symbol window boundary violation on channel A */
3706 uint16_t SSEA:1; /* symbol window syntax error on channel A */
3707 uint16_t MTA:1; /* media access test symbol MTS received on channel A */
3708 uint16_t CLKCORRFAILCNT:4; /* clock correction failed counter */
3709 } B;
3710 } PSR2_t;
3711 typedef union uPSR3 {
3712 uint16_t R;
3713 struct {
3714 uint16_t:2;
3715 uint16_t WUB:1; /* wakeup symbol received on channel B */
3716 uint16_t ABVB:1; /* aggregated boundary violation on channel B */
3717 uint16_t AACB:1; /* aggregated additional communication on channel B */
3718 uint16_t ACEB:1; /* aggregated content error on channel B */
3719 uint16_t ASEB:1; /* aggregated syntax error on channel B */
3720 uint16_t AVFB:1; /* aggregated valid frame on channel B */
3721 uint16_t:2;
3722 uint16_t WUA:1; /* wakeup symbol received on channel A */
3723 uint16_t ABVA:1; /* aggregated boundary violation on channel A */
3724 uint16_t AACA:1; /* aggregated additional communication on channel A */
3725 uint16_t ACEA:1; /* aggregated content error on channel A */
3726 uint16_t ASEA:1; /* aggregated syntax error on channel A */
3727 uint16_t AVFA:1; /* aggregated valid frame on channel A */
3728 } B;
3729 } PSR3_t;
3730 typedef union uCIFRR {
3731 uint16_t R;
3732 struct {
3733 uint16_t:8;
3734 uint16_t MIFR:1; /* module interrupt flag */
3735 uint16_t PRIFR:1; /* protocol interrupt flag */
3736 uint16_t CHIFR:1; /* CHI interrupt flag */
3737 uint16_t WUPIFR:1; /* wakeup interrupt flag */
3738 uint16_t FNEBIFR:1; /* receive fifo channel B no empty interrupt flag */
3739 uint16_t FNEAIFR:1; /* receive fifo channel A no empty interrupt flag */
3740 uint16_t RBIFR:1; /* receive message buffer interrupt flag */
3741 uint16_t TBIFR:1; /* transmit buffer interrupt flag */
3742 } B;
3743 } CIFRR_t;
3744 typedef union uSFCNTR {
3745 uint16_t R;
3746 struct {
3747 uint16_t SFEVB:4; /* sync frames channel B, even cycle */
3748 uint16_t SFEVA:4; /* sync frames channel A, even cycle */
3749 uint16_t SFODB:4; /* sync frames channel B, odd cycle */
3750 uint16_t SFODA:4; /* sync frames channel A, odd cycle */
3751 } B;
3752 } SFCNTR_t;
3753
3754 typedef union uSFTCCSR {
3755 uint16_t R;
3756 struct {
3757 uint16_t ELKT:1; /* even cycle tables lock and unlock trigger */
3758 uint16_t OLKT:1; /* odd cycle tables lock and unlock trigger */
3759 uint16_t CYCNUM:6; /* cycle number */
3760 uint16_t ELKS:1; /* even cycle tables lock status */
3761 uint16_t OLKS:1; /* odd cycle tables lock status */
3762 uint16_t EVAL:1; /* even cycle tables valid */
3763 uint16_t OVAL:1; /* odd cycle tables valid */
3764 uint16_t:1;
3765 uint16_t OPT:1; /*one pair trigger */
3766 uint16_t SDVEN:1; /* sync frame deviation table enable */
3767 uint16_t SIDEN:1; /* sync frame ID table enable */
3768 } B;
3769 } SFTCCSR_t;
3770 typedef union uSFIDRFR {
3771 uint16_t R;
3772 struct {
3773 uint16_t:6;
3774 uint16_t SYNFRID:10; /* sync frame rejection ID */
3775 } B;
3776 } SFIDRFR_t;
3777
3778 typedef union uTICCR {
3779 uint16_t R;
3780 struct {
3781 uint16_t:2;
3782 uint16_t T2CFG:1; /* timer 2 configuration */
3783 uint16_t T2REP:1; /* timer 2 repetitive mode */
3784 uint16_t:1;
3785 uint16_t T2SP:1; /* timer 2 stop */
3786 uint16_t T2TR:1; /* timer 2 trigger */
3787 uint16_t T2ST:1; /* timer 2 state */
3788 uint16_t:3;
3789 uint16_t T1REP:1; /* timer 1 repetitive mode */
3790 uint16_t:1;
3791 uint16_t T1SP:1; /* timer 1 stop */
3792 uint16_t T1TR:1; /* timer 1 trigger */
3793 uint16_t T1ST:1; /* timer 1 state */
3794
3795 } B;
3796 } TICCR_t;
3797 typedef union uTI1CYSR {
3798 uint16_t R;
3799 struct {
3800 uint16_t:2;
3801 uint16_t TI1CYCVAL:6; /* timer 1 cycle filter value */
3802 uint16_t:2;
3803 uint16_t TI1CYCMSK:6; /* timer 1 cycle filter mask */
3804
3805 } B;
3806 } TI1CYSR_t;
3807
3808 typedef union uSSSR {
3809 uint16_t R;
3810 struct {
3811 uint16_t WMD:1; /* write mode */
3812 uint16_t:1;
3813 uint16_t SEL:2; /* static slot number */
3814 uint16_t:1;
3815 uint16_t SLOTNUMBER:11; /* selector */
3816 } B;
3817 } SSSR_t;
3818
3819 typedef union uSSCCR {
3820 uint16_t R;
3821 struct {
3822 uint16_t WMD:1; /* write mode */
3823 uint16_t:1;
3824 uint16_t SEL:2; /* selector */
3825 uint16_t:1;
3826 uint16_t CNTCFG:2; /* counter configuration */
3827 uint16_t MCY:1; /* multi cycle selection */
3828 uint16_t VFR:1; /* valid frame selection */
3829 uint16_t SYF:1; /* sync frame selection */
3830 uint16_t NUF:1; /* null frame selection */
3831 uint16_t SUF:1; /* startup frame selection */
3832 uint16_t STATUSMASK:4; /* slot status mask */
3833 } B;
3834 } SSCCR_t;
3835 typedef union uSSR {
3836 uint16_t R;
3837 struct {
3838 uint16_t VFB:1; /* valid frame on channel B */
3839 uint16_t SYB:1; /* valid sync frame on channel B */
3840 uint16_t NFB:1; /* valid null frame on channel B */
3841 uint16_t SUB:1; /* valid startup frame on channel B */
3842 uint16_t SEB:1; /* syntax error on channel B */
3843 uint16_t CEB:1; /* content error on channel B */
3844 uint16_t BVB:1; /* boundary violation on channel B */
3845 uint16_t TCB:1; /* tx conflict on channel B */
3846 uint16_t VFA:1; /* valid frame on channel A */
3847 uint16_t SYA:1; /* valid sync frame on channel A */
3848 uint16_t NFA:1; /* valid null frame on channel A */
3849 uint16_t SUA:1; /* valid startup frame on channel A */
3850 uint16_t SEA:1; /* syntax error on channel A */
3851 uint16_t CEA:1; /* content error on channel A */
3852 uint16_t BVA:1; /* boundary violation on channel A */
3853 uint16_t TCA:1; /* tx conflict on channel A */
3854 } B;
3855 } SSR_t;
3856 typedef union uMTSCFR {
3857 uint16_t R;
3858 struct {
3859 uint16_t MTE:1; /* media access test symbol transmission enable */
3860 uint16_t:1;
3861 uint16_t CYCCNTMSK:6; /* cycle counter mask */
3862 uint16_t:2;
3863 uint16_t CYCCNTVAL:6; /* cycle counter value */
3864 } B;
3865 } MTSCFR_t;
3866 typedef union uRSBIR {
3867 uint16_t R;
3868 struct {
3869 uint16_t WMD:1; /* write mode */
3870 uint16_t:1;
3871 uint16_t SEL:2; /* selector */
3872 uint16_t:4;
3873 uint16_t RSBIDX:8; /* receive shadow buffer index */
3874 } B;
3875 } RSBIR_t;
3876 typedef union uRFDSR {
3877 uint16_t R;
3878 struct {
3879 uint16_t FIFODEPTH:8; /* fifo depth */
3880 uint16_t:1;
3881 uint16_t ENTRYSIZE:7; /* entry size */
3882 } B;
3883 } RFDSR_t;
3884
3885 typedef union uRFRFCFR {
3886 uint16_t R;
3887 struct {
3888 uint16_t WMD:1; /* write mode */
3889 uint16_t IBD:1; /* interval boundary */
3890 uint16_t SEL:2; /* filter number */
3891 uint16_t:1;
3892 uint16_t SID:11; /* slot ID */
3893 } B;
3894 } RFRFCFR_t;
3895
3896 typedef union uRFRFCTR {
3897 uint16_t R;
3898 struct {
3899 uint16_t:4;
3900 uint16_t F3MD:1; /* filter mode */
3901 uint16_t F2MD:1; /* filter mode */
3902 uint16_t F1MD:1; /* filter mode */
3903 uint16_t F0MD:1; /* filter mode */
3904 uint16_t:4;
3905 uint16_t F3EN:1; /* filter enable */
3906 uint16_t F2EN:1; /* filter enable */
3907 uint16_t F1EN:1; /* filter enable */
3908 uint16_t F0EN:1; /* filter enable */
3909 } B;
3910 } RFRFCTR_t;
3911 typedef union uPCR0 {
3912 uint16_t R;
3913 struct {
3914 uint16_t ACTION_POINT_OFFSET:6;
3915 uint16_t STATIC_SLOT_LENGTH:10;
3916 } B;
3917 } PCR0_t;
3918
3919 typedef union uPCR1 {
3920 uint16_t R;
3921 struct {
3922 uint16_t:2;
3923 uint16_t MACRO_AFTER_FIRST_STATIC_SLOT:14;
3924 } B;
3925 } PCR1_t;
3926
3927 typedef union uPCR2 {
3928 uint16_t R;
3929 struct {
3930 uint16_t MINISLOT_AFTER_ACTION_POINT:6;
3931 uint16_t NUMBER_OF_STATIC_SLOTS:10;
3932 } B;
3933 } PCR2_t;
3934
3935 typedef union uPCR3 {
3936 uint16_t R;
3937 struct {
3938 uint16_t WAKEUP_SYMBOL_RX_LOW:6;
3939 uint16_t MINISLOT_ACTION_POINT_OFFSET:5;
3940 uint16_t COLDSTART_ATTEMPTS:5;
3941 } B;
3942 } PCR3_t;
3943
3944 typedef union uPCR4 {
3945 uint16_t R;
3946 struct {
3947 uint16_t CAS_RX_LOW_MAX:7;
3948 uint16_t WAKEUP_SYMBOL_RX_WINDOW:9;
3949 } B;
3950 } PCR4_t;
3951
3952 typedef union uPCR5 {
3953 uint16_t R;
3954 struct {
3955 uint16_t TSS_TRANSMITTER:4;
3956 uint16_t WAKEUP_SYMBOL_TX_LOW:6;
3957 uint16_t WAKEUP_SYMBOL_RX_IDLE:6;
3958 } B;
3959 } PCR5_t;
3960
3961 typedef union uPCR6 {
3962 uint16_t R;
3963 struct {
3964 uint16_t:1;
3965 uint16_t SYMBOL_WINDOW_AFTER_ACTION_POINT:8;
3966 uint16_t MACRO_INITIAL_OFFSET_A:7;
3967 } B;
3968 } PCR6_t;
3969
3970 typedef union uPCR7 {
3971 uint16_t R;
3972 struct {
3973 uint16_t DECODING_CORRECTION_B:9;
3974 uint16_t MICRO_PER_MACRO_NOM_HALF:7;
3975 } B;
3976 } PCR7_t;
3977
3978 typedef union uPCR8 {
3979 uint16_t R;
3980 struct {
3981 uint16_t MAX_WITHOUT_CLOCK_CORRECTION_FATAL:4;
3982 uint16_t MAX_WITHOUT_CLOCK_CORRECTION_PASSIVE:4;
3983 uint16_t WAKEUP_SYMBOL_TX_IDLE:8;
3984 } B;
3985 } PCR8_t;
3986
3987 typedef union uPCR9 {
3988 uint16_t R;
3989 struct {
3990 uint16_t MINISLOT_EXISTS:1;
3991 uint16_t SYMBOL_WINDOW_EXISTS:1;
3992 uint16_t OFFSET_CORRECTION_OUT:14;
3993 } B;
3994 } PCR9_t;
3995
3996 typedef union uPCR10 {
3997 uint16_t R;
3998 struct {
3999 uint16_t SINGLE_SLOT_ENABLED:1;
4000 uint16_t WAKEUP_CHANNEL:1;
4001 uint16_t MACRO_PER_CYCLE:14;
4002 } B;
4003 } PCR10_t;
4004
4005 typedef union uPCR11 {
4006 uint16_t R;
4007 struct {
4008 uint16_t KEY_SLOT_USED_FOR_STARTUP:1;
4009 uint16_t KEY_SLOT_USED_FOR_SYNC:1;
4010 uint16_t OFFSET_CORRECTION_START:14;
4011 } B;
4012 } PCR11_t;
4013
4014 typedef union uPCR12 {
4015 uint16_t R;
4016 struct {
4017 uint16_t ALLOW_PASSIVE_TO_ACTIVE:5;
4018 uint16_t KEY_SLOT_HEADER_CRC:11;
4019 } B;
4020 } PCR12_t;
4021
4022 typedef union uPCR13 {
4023 uint16_t R;
4024 struct {
4025 uint16_t FIRST_MINISLOT_ACTION_POINT_OFFSET:6;
4026 uint16_t STATIC_SLOT_AFTER_ACTION_POINT:10;
4027 } B;
4028 } PCR13_t;
4029
4030 typedef union uPCR14 {
4031 uint16_t R;
4032 struct {
4033 uint16_t RATE_CORRECTION_OUT:11;
4034 uint16_t LISTEN_TIMEOUT_H:5;
4035 } B;
4036 } PCR14_t;
4037
4038 typedef union uPCR15 {
4039 uint16_t R;
4040 struct {
4041 uint16_t LISTEN_TIMEOUT_L:16;
4042 } B;
4043 } PCR15_t;
4044
4045 typedef union uPCR16 {
4046 uint16_t R;
4047 struct {
4048 uint16_t MACRO_INITIAL_OFFSET_B:7;
4049 uint16_t NOISE_LISTEN_TIMEOUT_H:9;
4050 } B;
4051 } PCR16_t;
4052
4053 typedef union uPCR17 {
4054 uint16_t R;
4055 struct {
4056 uint16_t NOISE_LISTEN_TIMEOUT_L:16;
4057 } B;
4058 } PCR17_t;
4059
4060 typedef union uPCR18 {
4061 uint16_t R;
4062 struct {
4063 uint16_t WAKEUP_PATTERN:6;
4064 uint16_t KEY_SLOT_ID:10;
4065 } B;
4066 } PCR18_t;
4067
4068 typedef union uPCR19 {
4069 uint16_t R;
4070 struct {
4071 uint16_t DECODING_CORRECTION_A:9;
4072 uint16_t PAYLOAD_LENGTH_STATIC:7;
4073 } B;
4074 } PCR19_t;
4075
4076 typedef union uPCR20 {
4077 uint16_t R;
4078 struct {
4079 uint16_t MICRO_INITIAL_OFFSET_B:8;
4080 uint16_t MICRO_INITIAL_OFFSET_A:8;
4081 } B;
4082 } PCR20_t;
4083
4084 typedef union uPCR21 {
4085 uint16_t R;
4086 struct {
4087 uint16_t EXTERN_RATE_CORRECTION:3;
4088 uint16_t LATEST_TX:13;
4089 } B;
4090 } PCR21_t;
4091
4092 typedef union uPCR22 {
4093 uint16_t R;
4094 struct {
4095 uint16_t:1;
4096 uint16_t COMP_ACCEPTED_STARTUP_RANGE_A:11;
4097 uint16_t MICRO_PER_CYCLE_H:4;
4098 } B;
4099 } PCR22_t;
4100
4101 typedef union uPCR23 {
4102 uint16_t R;
4103 struct {
4104 uint16_t micro_per_cycle_l:16;
4105 } B;
4106 } PCR23_t;
4107
4108 typedef union uPCR24 {
4109 uint16_t R;
4110 struct {
4111 uint16_t CLUSTER_DRIFT_DAMPING:5;
4112 uint16_t MAX_PAYLOAD_LENGTH_DYNAMIC:7;
4113 uint16_t MICRO_PER_CYCLE_MIN_H:4;
4114 } B;
4115 } PCR24_t;
4116
4117 typedef union uPCR25 {
4118 uint16_t R;
4119 struct {
4120 uint16_t MICRO_PER_CYCLE_MIN_L:16;
4121 } B;
4122 } PCR25_t;
4123
4124 typedef union uPCR26 {
4125 uint16_t R;
4126 struct {
4127 uint16_t ALLOW_HALT_DUE_TO_CLOCK:1;
4128 uint16_t COMP_ACCEPTED_STARTUP_RANGE_B:11;
4129 uint16_t MICRO_PER_CYCLE_MAX_H:4;
4130 } B;
4131 } PCR26_t;
4132
4133 typedef union uPCR27 {
4134 uint16_t R;
4135 struct {
4136 uint16_t MICRO_PER_CYCLE_MAX_L:16;
4137 } B;
4138 } PCR27_t;
4139
4140 typedef union uPCR28 {
4141 uint16_t R;
4142 struct {
4143 uint16_t DYNAMIC_SLOT_IDLE_PHASE:2;
4144 uint16_t MACRO_AFTER_OFFSET_CORRECTION:14;
4145 } B;
4146 } PCR28_t;
4147
4148 typedef union uPCR29 {
4149 uint16_t R;
4150 struct {
4151 uint16_t EXTERN_OFFSET_CORRECTION:3;
4152 uint16_t MINISLOTS_MAX:13;
4153 } B;
4154 } PCR29_t;
4155
4156 typedef union uPCR30 {
4157 uint16_t R;
4158 struct {
4159 uint16_t:12;
4160 uint16_t SYNC_NODE_MAX:4;
4161 } B;
4162 } PCR30_t;
4163
4164 typedef struct uMSG_BUFF_CCS {
4165 union {
4166 uint16_t R;
4167 struct {
4168 uint16_t:1;
4169 uint16_t MCM:1; /* message buffer commit mode */
4170 uint16_t MBT:1; /* message buffer type */
4171 uint16_t MTD:1; /* message buffer direction */
4172 uint16_t CMT:1; /* commit for transmission */
4173 uint16_t EDT:1; /* enable / disable trigger */
4174 uint16_t LCKT:1; /* lock request trigger */
4175 uint16_t MBIE:1; /* message buffer interrupt enable */
4176 uint16_t:3;
4177 uint16_t DUP:1; /* data updated */
4178 uint16_t DVAL:1; /* data valid */
4179 uint16_t EDS:1; /* lock status */
4180 uint16_t LCKS:1; /* enable / disable status */
4181 uint16_t MBIF:1; /* message buffer interrupt flag */
4182 } B;
4183 } MBCCSR;
4184 union {
4185 uint16_t R;
4186 struct {
4187 uint16_t MTM:1; /* message buffer transmission mode */
4188 uint16_t CHNLA:1; /* channel assignement */
4189 uint16_t CHNLB:1; /* channel assignement */
4190 uint16_t CCFE:1; /* cycle counter filter enable */
4191 uint16_t CCFMSK:6; /* cycle counter filter mask */
4192 uint16_t CCFVAL:6; /* cycle counter filter value */
4193 } B;
4194 } MBCCFR;
4195 union {
4196 uint16_t R;
4197 struct {
4198 uint16_t:5;
4199 uint16_t FID:11; /* frame ID */
4200 } B;
4201 } MBFIDR;
4202 union {
4203 uint16_t R;
4204 struct {
4205 uint16_t:8;
4206 uint16_t MBIDX:8; /* message buffer index */
4207 } B;
4208 } MBIDXR;
4209 } MSG_BUFF_CCS_t;
4210 typedef union uSYSBADHR {
4211 uint16_t R;
4212 } SYSBADHR_t;
4213 typedef union uSYSBADLR {
4214 uint16_t R;
4215 } SYSBADLR_t;
4216 typedef union uPDAR {
4217 uint16_t R;
4218 } PDAR_t;
4219 typedef union uCASERCR {
4220 uint16_t R;
4221 } CASERCR_t;
4222 typedef union uCBSERCR {
4223 uint16_t R;
4224 } CBSERCR_t;
4225 typedef union uCYCTR {
4226 uint16_t R;
4227 } CYCTR_t;
4228 typedef union uMTCTR {
4229 uint16_t R;
4230 } MTCTR_t;
4231 typedef union uSLTCTAR {
4232 uint16_t R;
4233 } SLTCTAR_t;
4234 typedef union uSLTCTBR {
4235 uint16_t R;
4236 } SLTCTBR_t;
4237 typedef union uRTCORVR {
4238 uint16_t R;
4239 } RTCORVR_t;
4240 typedef union uOFCORVR {
4241 uint16_t R;
4242 } OFCORVR_t;
4243 typedef union uSFTOR {
4244 uint16_t R;
4245 } SFTOR_t;
4246 typedef union uSFIDAFVR {
4247 uint16_t R;
4248 } SFIDAFVR_t;
4249 typedef union uSFIDAFMR {
4250 uint16_t R;
4251 } SFIDAFMR_t;
4252 typedef union uNMVR {
4253 uint16_t R;
4254 } NMVR_t;
4255 typedef union uNMVLR {
4256 uint16_t R;
4257 } NMVLR_t;
4258 typedef union uT1MTOR {
4259 uint16_t R;
4260 } T1MTOR_t;
4261 typedef union uTI2CR0 {
4262 uint16_t R;
4263 } TI2CR0_t;
4264 typedef union uTI2CR1 {
4265 uint16_t R;
4266 } TI2CR1_t;
4267 typedef union uSSCR {
4268 uint16_t R;
4269 } SSCR_t;
4270 typedef union uRFSR {
4271 uint16_t R;
4272 } RFSR_t;
4273 typedef union uRFSIR {
4274 uint16_t R;
4275 } RFSIR_t;
4276 typedef union uRFARIR {
4277 uint16_t R;
4278 } RFARIR_t;
4279 typedef union uRFBRIR {
4280 uint16_t R;
4281 } RFBRIR_t;
4282 typedef union uRFMIDAFVR {
4283 uint16_t R;
4284 } RFMIDAFVR_t;
4285 typedef union uRFMIAFMR {
4286 uint16_t R;
4287 } RFMIAFMR_t;
4288 typedef union uRFFIDRFVR {
4289 uint16_t R;
4290 } RFFIDRFVR_t;
4291 typedef union uRFFIDRFMR {
4292 uint16_t R;
4293 } RFFIDRFMR_t;
4294 typedef union uLDTXSLAR {
4295 uint16_t R;
4296 } LDTXSLAR_t;
4297 typedef union uLDTXSLBR {
4298 uint16_t R;
4299 } LDTXSLBR_t;
4300
4301 typedef struct FR_tag {
4302 volatile MVR_t MVR; /*module version register *//*0 */
4303 volatile MCR_t MCR; /*module configuration register *//*2 */
4304 volatile SYSBADHR_t SYSBADHR; /*system memory base address high register *//*4 */
4305 volatile SYSBADLR_t SYSBADLR; /*system memory base address low register *//*6 */
4306 volatile STBSCR_t STBSCR; /*strobe signal control register *//*8 */
4307 volatile STBPCR_t STBPCR; /*strobe port control register *//*A */
4308 volatile MBDSR_t MBDSR; /*message buffer data size register *//*C */
4309 volatile MBSSUTR_t MBSSUTR; /*message buffer segment size and utilization register *//*E */
4310 uint16_t reserved3a[1]; /*10 */
4311 volatile PDAR_t PDAR; /*PE data register *//*12 */
4312 volatile POCR_t POCR; /*Protocol operation control register *//*14 */
4313 volatile GIFER_t GIFER; /*global interrupt flag and enable register *//*16 */
4314 volatile PIFR0_t PIFR0; /*protocol interrupt flag register 0 *//*18 */
4315 volatile PIFR1_t PIFR1; /*protocol interrupt flag register 1 *//*1A */
4316 volatile PIER0_t PIER0; /*protocol interrupt enable register 0 *//*1C */
4317 volatile PIER1_t PIER1; /*protocol interrupt enable register 1 *//*1E */
4318 volatile CHIERFR_t CHIERFR; /*CHI error flag register *//*20 */
4319 volatile MBIVEC_t MBIVEC; /*message buffer interrupt vector register *//*22 */
4320 volatile CASERCR_t CASERCR; /*channel A status error counter register *//*24 */
4321 volatile CBSERCR_t CBSERCR; /*channel B status error counter register *//*26 */
4322 volatile PSR0_t PSR0; /*protocol status register 0 *//*28 */
4323 volatile PSR1_t PSR1; /*protocol status register 1 *//*2A */
4324 volatile PSR2_t PSR2; /*protocol status register 2 *//*2C */
4325 volatile PSR3_t PSR3; /*protocol status register 3 *//*2E */
4326 volatile MTCTR_t MTCTR; /*macrotick counter register *//*30 */
4327 volatile CYCTR_t CYCTR; /*cycle counter register *//*32 */
4328 volatile SLTCTAR_t SLTCTAR; /*slot counter channel A register *//*34 */
4329 volatile SLTCTBR_t SLTCTBR; /*slot counter channel B register *//*36 */
4330 volatile RTCORVR_t RTCORVR; /*rate correction value register *//*38 */
4331 volatile OFCORVR_t OFCORVR; /*offset correction value register *//*3A */
4332 volatile CIFRR_t CIFRR; /*combined interrupt flag register *//*3C */
4333 uint16_t reserved3[1]; /*3E */
4334 volatile SFCNTR_t SFCNTR; /*sync frame counter register *//*40 */
4335 volatile SFTOR_t SFTOR; /*sync frame table offset register *//*42 */
4336 volatile SFTCCSR_t SFTCCSR; /*sync frame table configuration, control, status register *//*44 */
4337 volatile SFIDRFR_t SFIDRFR; /*sync frame ID rejection filter register *//*46 */
4338 volatile SFIDAFVR_t SFIDAFVR; /*sync frame ID acceptance filter value regiater *//*48 */
4339 volatile SFIDAFMR_t SFIDAFMR; /*sync frame ID acceptance filter mask register *//*4A */
4340 volatile NMVR_t NMVR[6]; /*network management vector registers (12 bytes) *//*4C */
4341 volatile NMVLR_t NMVLR; /*network management vector length register *//*58 */
4342 volatile TICCR_t TICCR; /*timer configuration and control register *//*5A */
4343 volatile TI1CYSR_t TI1CYSR; /*timer 1 cycle set register *//*5C */
4344 volatile T1MTOR_t T1MTOR; /*timer 1 macrotick offset register *//*5E */
4345 volatile TI2CR0_t TI2CR0; /*timer 2 configuration register 0 *//*60 */
4346 volatile TI2CR1_t TI2CR1; /*timer 2 configuration register 1 *//*62 */
4347 volatile SSSR_t SSSR; /*slot status selection register *//*64 */
4348 volatile SSCCR_t SSCCR; /*slot status counter condition register *//*66 */
4349 volatile SSR_t SSR[8]; /*slot status registers 0-7 *//*68 */
4350 volatile SSCR_t SSCR[4]; /*slot status counter registers 0-3 *//*78 */
4351 volatile MTSCFR_t MTSACFR; /*mts a config register *//*80 */
4352 volatile MTSCFR_t MTSBCFR; /*mts b config register *//*82 */
4353 volatile RSBIR_t RSBIR; /*receive shadow buffer index register *//*84 */
4354 volatile RFSR_t RFSR; /*receive fifo selection register *//*86 */
4355 volatile RFSIR_t RFSIR; /*receive fifo start index register *//*88 */
4356 volatile RFDSR_t RFDSR; /*receive fifo depth and size register *//*8A */
4357 volatile RFARIR_t RFARIR; /*receive fifo a read index register *//*8C */
4358 volatile RFBRIR_t RFBRIR; /*receive fifo b read index register *//*8E */
4359 volatile RFMIDAFVR_t RFMIDAFVR; /*receive fifo message ID acceptance filter value register *//*90 */
4360 volatile RFMIAFMR_t RFMIAFMR; /*receive fifo message ID acceptance filter mask register *//*92 */
4361 volatile RFFIDRFVR_t RFFIDRFVR; /*receive fifo frame ID rejection filter value register *//*94 */
4362 volatile RFFIDRFMR_t RFFIDRFMR; /*receive fifo frame ID rejection filter mask register *//*96 */
4363 volatile RFRFCFR_t RFRFCFR; /*receive fifo range filter configuration register *//*98 */
4364 volatile RFRFCTR_t RFRFCTR; /*receive fifo range filter control register *//*9A */
4365 volatile LDTXSLAR_t LDTXSLAR; /*last dynamic transmit slot channel A register *//*9C */
4366 volatile LDTXSLBR_t LDTXSLBR; /*last dynamic transmit slot channel B register *//*9E */
4367 volatile PCR0_t PCR0; /*protocol configuration register 0 *//*A0 */
4368 volatile PCR1_t PCR1; /*protocol configuration register 1 *//*A2 */
4369 volatile PCR2_t PCR2; /*protocol configuration register 2 *//*A4 */
4370 volatile PCR3_t PCR3; /*protocol configuration register 3 *//*A6 */
4371 volatile PCR4_t PCR4; /*protocol configuration register 4 *//*A8 */
4372 volatile PCR5_t PCR5; /*protocol configuration register 5 *//*AA */
4373 volatile PCR6_t PCR6; /*protocol configuration register 6 *//*AC */
4374 volatile PCR7_t PCR7; /*protocol configuration register 7 *//*AE */
4375 volatile PCR8_t PCR8; /*protocol configuration register 8 *//*B0 */
4376 volatile PCR9_t PCR9; /*protocol configuration register 9 *//*B2 */
4377 volatile PCR10_t PCR10; /*protocol configuration register 10 *//*B4 */
4378 volatile PCR11_t PCR11; /*protocol configuration register 11 *//*B6 */
4379 volatile PCR12_t PCR12; /*protocol configuration register 12 *//*B8 */
4380 volatile PCR13_t PCR13; /*protocol configuration register 13 *//*BA */
4381 volatile PCR14_t PCR14; /*protocol configuration register 14 *//*BC */
4382 volatile PCR15_t PCR15; /*protocol configuration register 15 *//*BE */
4383 volatile PCR16_t PCR16; /*protocol configuration register 16 *//*C0 */
4384 volatile PCR17_t PCR17; /*protocol configuration register 17 *//*C2 */
4385 volatile PCR18_t PCR18; /*protocol configuration register 18 *//*C4 */
4386 volatile PCR19_t PCR19; /*protocol configuration register 19 *//*C6 */
4387 volatile PCR20_t PCR20; /*protocol configuration register 20 *//*C8 */
4388 volatile PCR21_t PCR21; /*protocol configuration register 21 *//*CA */
4389 volatile PCR22_t PCR22; /*protocol configuration register 22 *//*CC */
4390 volatile PCR23_t PCR23; /*protocol configuration register 23 *//*CE */
4391 volatile PCR24_t PCR24; /*protocol configuration register 24 *//*D0 */
4392 volatile PCR25_t PCR25; /*protocol configuration register 25 *//*D2 */
4393 volatile PCR26_t PCR26; /*protocol configuration register 26 *//*D4 */
4394 volatile PCR27_t PCR27; /*protocol configuration register 27 *//*D6 */
4395 volatile PCR28_t PCR28; /*protocol configuration register 28 *//*D8 */
4396 volatile PCR29_t PCR29; /*protocol configuration register 29 *//*DA */
4397 volatile PCR30_t PCR30; /*protocol configuration register 30 *//*DC */
4398 uint16_t reserved2[17];
4399 volatile MSG_BUFF_CCS_t MBCCS[128]; /* message buffer configuration, control & status registers 0-31 *//*100 */
4400 } FR_tag_t;
4401
4402 typedef union uF_HEADER /* frame header */
4403 {
4404 struct {
4405 uint16_t:5;
4406 uint16_t HDCRC:11; /* Header CRC */
4407 uint16_t:2;
4408 uint16_t CYCCNT:6; /* Cycle Count */
4409 uint16_t:1;
4410 uint16_t PLDLEN:7; /* Payload Length */
4411 uint16_t:1;
4412 uint16_t PPI:1; /* Payload Preamble Indicator */
4413 uint16_t NUF:1; /* Null Frame Indicator */
4414 uint16_t SYF:1; /* Sync Frame Indicator */
4415 uint16_t SUF:1; /* Startup Frame Indicator */
4416 uint16_t FID:11; /* Frame ID */
4417 } B;
4418 uint16_t WORDS[3];
4419 } F_HEADER_t;
4420 typedef union uS_STSTUS /* slot status */
4421 {
4422 struct {
4423 uint16_t VFB:1; /* Valid Frame on channel B */
4424 uint16_t SYB:1; /* Sync Frame Indicator channel B */
4425 uint16_t NFB:1; /* Null Frame Indicator channel B */
4426 uint16_t SUB:1; /* Startup Frame Indicator channel B */
4427 uint16_t SEB:1; /* Syntax Error on channel B */
4428 uint16_t CEB:1; /* Content Error on channel B */
4429 uint16_t BVB:1; /* Boundary Violation on channel B */
4430 uint16_t CH:1; /* Channel */
4431 uint16_t VFA:1; /* Valid Frame on channel A */
4432 uint16_t SYA:1; /* Sync Frame Indicator channel A */
4433 uint16_t NFA:1; /* Null Frame Indicator channel A */
4434 uint16_t SUA:1; /* Startup Frame Indicator channel A */
4435 uint16_t SEA:1; /* Syntax Error on channel A */
4436 uint16_t CEA:1; /* Content Error on channel A */
4437 uint16_t BVA:1; /* Boundary Violation on channel A */
4438 uint16_t:1;
4439 } RX;
4440 struct {
4441 uint16_t VFB:1; /* Valid Frame on channel B */
4442 uint16_t SYB:1; /* Sync Frame Indicator channel B */
4443 uint16_t NFB:1; /* Null Frame Indicator channel B */
4444 uint16_t SUB:1; /* Startup Frame Indicator channel B */
4445 uint16_t SEB:1; /* Syntax Error on channel B */
4446 uint16_t CEB:1; /* Content Error on channel B */
4447 uint16_t BVB:1; /* Boundary Violation on channel B */
4448 uint16_t TCB:1; /* Tx Conflict on channel B */
4449 uint16_t VFA:1; /* Valid Frame on channel A */
4450 uint16_t SYA:1; /* Sync Frame Indicator channel A */
4451 uint16_t NFA:1; /* Null Frame Indicator channel A */
4452 uint16_t SUA:1; /* Startup Frame Indicator channel A */
4453 uint16_t SEA:1; /* Syntax Error on channel A */
4454 uint16_t CEA:1; /* Content Error on channel A */
4455 uint16_t BVA:1; /* Boundary Violation on channel A */
4456 uint16_t TCA:1; /* Tx Conflict on channel A */
4457 } TX;
4458 uint16_t R;
4459 } S_STATUS_t;
4460
4461 typedef struct uMB_HEADER /* message buffer header */
4462 {
4463 F_HEADER_t FRAME_HEADER;
4464 uint16_t DATA_OFFSET;
4465 S_STATUS_t SLOT_STATUS;
4466 } MB_HEADER_t;
4467
4468/* Define memories */
4469
4470#define SRAM_START 0x40000000
4471#define SRAM_SIZE 0x14000
4472#define SRAM_END 0x40013FFF
4473
4474#define FLASH_START 0x0
4475#define FLASH_SIZE 0x200000
4476#define FLASH_END 0x1FFFFF
4477
4478/* Define instances of modules */
4479#define PBRIDGE_A (*(volatile struct PBRIDGE_A_tag *) 0xC3F00000)
4480#define FMPLL (*(volatile struct FMPLL_tag *) 0xC3F80000)
4481#define EBI (*(volatile struct EBI_tag *) 0xC3F84000)
4482#define FLASH (*(volatile struct FLASH_tag *) 0xC3F88000)
4483#define SIU (*(volatile struct SIU_tag *) 0xC3F90000)
4484
4485#define EMIOS (*(volatile struct EMIOS_tag *) 0xC3FA0000)
4486#define ETPU (*(volatile struct ETPU_tag *) 0xC3FC0000)
4487#define ETPU_DATA_RAM (*( uint32_t *) 0xC3FC8000)
4488#define ETPU_DATA_RAM_EXT (*( uint32_t *) 0xC3FCC000)
4489#define ETPU_DATA_RAM_END 0xC3FC89FC
4490#define CODE_RAM (*( uint32_t *) 0xC3FD0000)
4491#define ETPU_CODE_RAM (*( uint32_t *) 0xC3FD0000)
4492
4493#define PBRIDGE_B (*(volatile struct PBRIDGE_B_tag *) 0xFFF00000)
4494#define XBAR (*(volatile struct XBAR_tag *) 0xFFF04000)
4495#define ECSM (*(volatile struct ECSM_tag *) 0xFFF40000)
4496#define EDMA (*(volatile struct EDMA_tag *) 0xFFF44000)
4497#define INTC (*(volatile struct INTC_tag *) 0xFFF48000)
4498
4499#define EQADC (*(volatile struct EQADC_tag *) 0xFFF80000)
4500
4501#define DSPI_A (*(volatile struct DSPI_tag *) 0xFFF90000)
4502#define DSPI_B (*(volatile struct DSPI_tag *) 0xFFF94000)
4503#define DSPI_C (*(volatile struct DSPI_tag *) 0xFFF98000)
4504#define DSPI_D (*(volatile struct DSPI_tag *) 0xFFF9C000)
4505
4506#define ESCI_A (*(volatile struct ESCI_tag *) 0xFFFB0000)
4507#define ESCI_B (*(volatile struct ESCI_tag *) 0xFFFB4000)
4508
4509#define CAN_A (*(volatile struct FLEXCAN2_tag *) 0xFFFC0000)
4510#define CAN_B (*(volatile struct FLEXCAN2_tag *) 0xFFFC4000)
4511#define CAN_C (*(volatile struct FLEXCAN2_tag *) 0xFFFC8000)
4512#define CAN_D (*(volatile struct FLEXCAN2_tag *) 0xFFFCC000)
4513#define CAN_E (*(volatile struct FLEXCAN2_tag *) 0xFFFD0000)
4514
4515#define FEC (*(volatile struct FEC_tag *) 0xFFF4C000)
4516
4517#define FR (*(volatile struct FR_tag *) 0xFFFE0000)
4518
4519#ifdef __MWERKS__
4520#pragma pop
4521#endif
4522
4523#ifdef __cplusplus
4524}
4525#endif
4526#endif /* ASM */
4527#endif /* ifdef _MPC5567_H */
4528/*********************************************************************
4529 *
4530 * Copyright:
4531 * Freescale Semiconductor, INC. All Rights Reserved.
4532 * You are hereby granted a copyright license to use, modify, and
4533 * distribute the SOFTWARE so long as this entire notice is
4534 * retained without alteration in any modified and/or redistributed
4535 * versions, and that such modified versions are clearly identified
4536 * as such. No licenses are granted by implication, estoppel or
4537 * otherwise under any patents or trademarks of Freescale
4538 * Semiconductor, Inc. This software is provided on an "AS IS"
4539 * basis and without warranty.
4540 *
4541 * To the maximum extent permitted by applicable law, Freescale
4542 * Semiconductor DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED,
4543 * INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A
4544 * PARTICULAR PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH
4545 * REGARD TO THE SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF)
4546 * AND ANY ACCOMPANYING WRITTEN MATERIALS.
4547 *
4548 * To the maximum extent permitted by applicable law, IN NO EVENT
4549 * SHALL Freescale Semiconductor BE LIABLE FOR ANY DAMAGES WHATSOEVER
4550 * (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS,
4551 * BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER
4552 * PECUNIARY LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE.
4553 *
4554 * Freescale Semiconductor assumes no responsibility for the
4555 * maintenance and support of this software
4556 *
4557 ********************************************************************/
DSPI_tag
Definition: fsl-mpc551x.h:238
EBI_CAL_CS_tag
Definition: fsl-mpc551x.h:473
EBI_CS_tag
Definition: fsl-mpc551x.h:441
EBI_tag
Definition: fsl-mpc551x.h:477
ECSM_tag
Definition: fsl-mpc555x.h:2173
EMIOS_tag
Definition: fsl-mpc551x.h:525
EQADC_tag
Definition: fsl-mpc551x.h:710
ESCI_tag
Definition: fsl-mpc551x.h:893
ETPU_tag
Definition: fsl-mpc555x.h:1130
FEC_tag
Definition: fsl-mpc556x.h:2976
FLASH_tag
Definition: fsl-mpc551x.h:1021
FLEXCAN2_tag
Definition: fsl-mpc555x.h:2993
FMPLL_tag
Definition: fsl-mpc551x.h:1478
FR_tag
Definition: fsl-mpc551x.h:3616
INTC_tag
Definition: fsl-mpc551x.h:1597
PBRIDGE_A_tag
Definition: fsl-mpc555x.h:118
PBRIDGE_B_tag
Definition: fsl-mpc555x.h:230
SIU_tag
Definition: fsl-mpc551x.h:2215
XBAR_tag
Definition: fsl-mpc555x.h:1976
uMB_HEADER
Definition: fsl-mpc551x.h:3777
uMSG_BUFF_CCS
Definition: fsl-mpc551x.h:3475
DSPI_CTAR_tag
Definition: fsl-mpc564xL.h:16580
DSPI_MCR_tag
Definition: fsl-mpc564xL.h:16535
DSPI_POPR_tag
Definition: fsl-mpc564xL.h:16692
DSPI_PUSHR_tag
Definition: fsl-mpc564xL.h:16672
DSPI_RSER_tag
Definition: fsl-mpc564xL.h:16621
DSPI_SR_tag
Definition: fsl-mpc564xL.h:16599
SIU_PCR_tag
Definition: fsl-mpc564xL.h:960
uCASERCR
Definition: fsl-mpc551x.h:3534
uCBSERCR
Definition: fsl-mpc551x.h:3537
uCHIERFR
Definition: fsl-mpc551x.h:2933
uCIFRR
Definition: fsl-mpc551x.h:3031
uCYCTR
Definition: fsl-mpc551x.h:3540
uF_HEADER
Definition: fsl-mpc551x.h:3718
uGIFER
Definition: fsl-mpc551x.h:2836
uLDTXSLAR
Definition: fsl-mpc551x.h:3609
uLDTXSLBR
Definition: fsl-mpc551x.h:3612
uMBDSR
Definition: fsl-mpc551x.h:2801
uMBIVEC
Definition: fsl-mpc551x.h:2954
uMBSSUTR
Definition: fsl-mpc551x.h:2811
uMCR
Definition: fsl-mpc551x.h:2775
uMTCTR
Definition: fsl-mpc551x.h:3543
uMTSCFR
Definition: fsl-mpc551x.h:3165
uMVR
Definition: fsl-mpc551x.h:2767
uNMVLR
Definition: fsl-mpc551x.h:3570
uNMVR
Definition: fsl-mpc551x.h:3567
uOFCORVR
Definition: fsl-mpc551x.h:3555
uPCR0
Definition: fsl-mpc551x.h:3222
uPCR10
Definition: fsl-mpc551x.h:3307
uPCR11
Definition: fsl-mpc551x.h:3316
uPCR12
Definition: fsl-mpc551x.h:3325
uPCR13
Definition: fsl-mpc551x.h:3333
uPCR14
Definition: fsl-mpc551x.h:3341
uPCR15
Definition: fsl-mpc551x.h:3349
uPCR16
Definition: fsl-mpc551x.h:3356
uPCR17
Definition: fsl-mpc551x.h:3364
uPCR18
Definition: fsl-mpc551x.h:3371
uPCR19
Definition: fsl-mpc551x.h:3379
uPCR1
Definition: fsl-mpc551x.h:3230
uPCR20
Definition: fsl-mpc551x.h:3387
uPCR21
Definition: fsl-mpc551x.h:3395
uPCR22
Definition: fsl-mpc551x.h:3403
uPCR23
Definition: fsl-mpc551x.h:3412
uPCR24
Definition: fsl-mpc551x.h:3419
uPCR25
Definition: fsl-mpc551x.h:3428
uPCR26
Definition: fsl-mpc551x.h:3435
uPCR27
Definition: fsl-mpc551x.h:3444
uPCR28
Definition: fsl-mpc551x.h:3451
uPCR29
Definition: fsl-mpc551x.h:3459
uPCR2
Definition: fsl-mpc551x.h:3238
uPCR30
Definition: fsl-mpc551x.h:3467
uPCR3
Definition: fsl-mpc551x.h:3246
uPCR4
Definition: fsl-mpc551x.h:3255
uPCR5
Definition: fsl-mpc551x.h:3263
uPCR6
Definition: fsl-mpc551x.h:3272
uPCR7
Definition: fsl-mpc551x.h:3281
uPCR8
Definition: fsl-mpc551x.h:3289
uPCR9
Definition: fsl-mpc551x.h:3298
uPDAR
Definition: fsl-mpc551x.h:3531
uPIER0
Definition: fsl-mpc551x.h:2895
uPIER1
Definition: fsl-mpc551x.h:2916
uPIFR0
Definition: fsl-mpc551x.h:2857
uPIFR1
Definition: fsl-mpc551x.h:2878
uPOCR
Definition: fsl-mpc551x.h:2822
uPSR0
Definition: fsl-mpc551x.h:2965
uPSR1
Definition: fsl-mpc551x.h:2981
uPSR2
Definition: fsl-mpc551x.h:2994
uPSR3
Definition: fsl-mpc551x.h:3012
uRFARIR
Definition: fsl-mpc551x.h:3591
uRFBRIR
Definition: fsl-mpc551x.h:3594
uRFDSR
Definition: fsl-mpc551x.h:3187
uRFFIDRFMR
Definition: fsl-mpc551x.h:3606
uRFFIDRFVR
Definition: fsl-mpc551x.h:3603
uRFMIAFMR
Definition: fsl-mpc551x.h:3600
uRFMIDAFVR
Definition: fsl-mpc551x.h:3597
uRFRFCFR
Definition: fsl-mpc551x.h:3196
uRFRFCTR
Definition: fsl-mpc551x.h:3207
uRFSIR
Definition: fsl-mpc551x.h:3588
uRFSR
Definition: fsl-mpc551x.h:3585
uRSBIR
Definition: fsl-mpc551x.h:3176
uRTCORVR
Definition: fsl-mpc551x.h:3552
uSFCNTR
Definition: fsl-mpc551x.h:3053
uSFIDAFMR
Definition: fsl-mpc551x.h:3564
uSFIDAFVR
Definition: fsl-mpc551x.h:3561
uSFIDRFR
Definition: fsl-mpc551x.h:3079
uSFTCCSR
Definition: fsl-mpc551x.h:3063
uSFTOR
Definition: fsl-mpc551x.h:3558
uSLTCTAR
Definition: fsl-mpc551x.h:3546
uSLTCTBR
Definition: fsl-mpc551x.h:3549
uSSCCR
Definition: fsl-mpc551x.h:3128
uSSCR
Definition: fsl-mpc551x.h:3582
uSSR
Definition: fsl-mpc551x.h:3144
uSSSR
Definition: fsl-mpc551x.h:3117
uSTBPCR
Definition: fsl-mpc556x.h:3490
uSTBSCR
Definition: fsl-mpc551x.h:2790
uSYSBADHR
Definition: fsl-mpc551x.h:3522
uSYSBADLR
Definition: fsl-mpc551x.h:3525
uS_STSTUS
Definition: fsl-mpc551x.h:3736
uT1MTOR
Definition: fsl-mpc551x.h:3573
uTI1CYSR
Definition: fsl-mpc551x.h:3106
uTI2CR0
Definition: fsl-mpc551x.h:3576
uTI2CR1
Definition: fsl-mpc551x.h:3579
uTICCR
Definition: fsl-mpc551x.h:3087
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