RTEMS 6.1-rc6
Loading...
Searching...
No Matches
bestcomm_cntrl.h
1#ifndef __TASK_API_BESTCOMM_CNTRL_H
2#define __TASK_API_BESTCOMM_CNTRL_H 1
3
4/******************************************************************************
5*
6* Copyright (c) 2004 Freescale Semiconductor, Inc.
7*
8* Permission is hereby granted, free of charge, to any person obtaining a
9* copy of this software and associated documentation files (the "Software"),
10* to deal in the Software without restriction, including without limitation
11* the rights to use, copy, modify, merge, publish, distribute, sublicense,
12* and/or sell copies of the Software, and to permit persons to whom the
13* Software is furnished to do so, subject to the following conditions:
14*
15* The above copyright notice and this permission notice shall be included
16* in all copies or substantial portions of the Software.
17*
18* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
22* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
23* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
24* OTHER DEALINGS IN THE SOFTWARE.
25*
26******************************************************************************/
27
28/*******************************************************************************
29 * Defines to control SmartDMA and its tasks. These defines are used for the
30 * task build process to minimize disconnects at the task/driver interface.
31 ******************************************************************************/
32
33#define SDMA_INT_BIT_DBG 31 /* debug interrupt bit */
34#define SDMA_INT_BIT_TEA 28 /* TEA interrupt bit */
35#define SDMA_INT_BIT_TEA_TASK 24 /* lsb for TEA task number */
36#define SDMA_INT_BIT_IMPL 0x9000FFFF
37
38#define SDMA_PTDCTRL_BIT_TEA 14 /* TEA detection enable bit */
39
40#define SDMA_TCR_BIT_AUTO 15 /* auto start bit */
41#define SDMA_TCR_BIT_HOLD 5 /* hold initiator bit */
42
43#define SDMA_STAT_BIT_ALARM 17
44#define SDMA_FIFO_ALARM_MASK 0x0020000
45
46#define SDMA_DRD_BIT_TFD 27 /* mark last buffer of frame */
47#define SDMA_DRD_BIT_INT 26 /* interrupt after buffer processed */
48#define SDMA_DRD_BIT_INIT 21 /* lsb position of initiator */
49#define SDMA_DRD_MASK_FLAGS 0x0C000000 /* BD_FLAGS flag bits */
50#define SDMA_DRD_MASK_LENGTH 0x03FFFFFF /* BD_FLAGS length mask */
51#define SDMA_BD_BIT_READY 30 /* Status BD ready bit */
52#ifdef SAS_COMPILE
53 #define SDMA_BD_MASK_READY constant(1<<SDMA_BD_BIT_READY)
54#else
55 #define SDMA_BD_MASK_READY (1<<SDMA_BD_BIT_READY)
56#endif
57#define SDMA_BD_MASK_SIGN 0x7FFFFFFF /* task code needs Status>0 */
58
59#define SDMA_PRAGMA_BIT_RSV 7 /* reserved pragma bit */
60#define SDMA_PRAGMA_BIT_PRECISE_INC 6 /* increment 0=when possible, 1=iter end */
61#define SDMA_PRAGMA_BIT_RST_ERROR_NO 5 /* don't reset errors on task enable */
62#define SDMA_PRAGMA_BIT_PACK 4 /* pack data enable */
63#define SDMA_PRAGMA_BIT_INTEGER 3 /* data alignment 0=frac(msb), 1=int(lsb) */
64#define SDMA_PRAGMA_BIT_SPECREAD 2 /* XLB speculative read enable */
65#define SDMA_PRAGMA_BIT_CW 1 /* write line buffer enable */
66#define SDMA_PRAGMA_BIT_RL 0 /* read line buffer enable */
67
68#define SDMA_TASK_ENTRY_BYTES 32 /* Bytes per task in entry table */
69#define SDMA_TASK_GROUP_NUM 16 /* Number of tasks per task group */
70#define SDMA_TASK_GROUP_BYTES (SDMA_TASK_ENTRY_BYTES*SDMA_TASK_GROUP_NUM)
71
72
73/*******************************************************************************
74 * Task group control macros, use when TaskNum > 15
75 ******************************************************************************/
76#define SDMA_TASKNUM_EXT(OldTaskNum) (OldTaskNum%16)
77
78#define SDMA_TASKBAR_CHANGE(sdma, OldTaskNum) { \
79 sdma->taskBar += (((int)(OldTaskNum/SDMA_TASK_GROUP_NUM))*SDMA_TASK_GROUP_BYTES); \
80}
81
82#define SDMA_TASKBAR_RESTORE(sdma, OldTaskNum) { \
83 sdma->taskBar -= (((int)(OldTaskNum/SDMA_TASK_GROUP_NUM))*SDMA_TASK_GROUP_BYTES); \
84}
85
86
87/*******************************************************************************
88 * Task control macros
89 ******************************************************************************/
90#define SDMA_TASK_CFG(RegAddr, TaskNum, AutoStart, AutoStartNum) { \
91 *(((volatile uint16 *)RegAddr)+TaskNum) = (uint16)(0x0000 | \
92 ((AutoStart!=0)<<7) | \
93 (AutoStartNum&0xF) ); \
94}
95
96#define SDMA_TASK_AUTO_START(RegAddr, TaskNum, AutoStart, AutoStartNum) { \
97 *(((volatile uint16 *)RegAddr)+TaskNum) = (uint16)((*(((volatile uint16 *)RegAddr)+TaskNum) & \
98 (uint16) 0xff30) | ((uint16)(0x0000 | \
99 ((AutoStart!=0)<<7) | \
100 (AutoStartNum&0xF)) )); \
101}
102
103#define SDMA_TASK_ENABLE(RegAddr, TaskNum) { \
104 *(((volatile uint16 *)RegAddr)+TaskNum) |= (uint16)0x8000; \
105}
106
107#define SDMA_TASK_DISABLE(RegAddr, TaskNum) { \
108 *(((volatile uint16 *)RegAddr)+TaskNum) &= ~(uint16)0x8000; \
109}
110
111#define SDMA_TASK_STATUS(RegAddr, TaskNum) \
112 *(((volatile uint16 *)RegAddr)+TaskNum)
113
114
115/*******************************************************************************
116 * Interrupt control macros
117 ******************************************************************************/
118#define SDMA_INT_ENABLE(RegAddr, Bit) \
119 do { \
120 rtems_interrupt_level level; \
121 rtems_interrupt_disable(level); \
122 *((volatile uint32 *) RegAddr) &= ~((uint32) (1 << Bit)); \
123 rtems_interrupt_enable(level); \
124 } while (0)
125
126#define SDMA_INT_DISABLE(RegAddr, Bit) \
127 do { \
128 rtems_interrupt_level level; \
129 rtems_interrupt_disable(level); \
130 *((volatile uint32 *) (RegAddr)) |= ((uint32)(1 << Bit)); \
131 rtems_interrupt_enable(level); \
132 } while (0)
133
134#define SDMA_INT_SOURCE(RegPend, RegMask) \
135 (*((volatile uint32 *)(RegPend)) & (~*((volatile uint32 *)(RegMask))) & (uint32)SDMA_INT_BIT_IMPL)
136
137#define SDMA_INT_PENDING(RegPend, RegMask) \
138 (*((volatile uint32 *)(RegPend)) & (~*((volatile uint32 *)(RegMask))))
139
140#define SDMA_INT_TEST(IntSource, Bit) \
141 (((uint32)IntSource) & ((uint32)(1<<Bit)))
142
143/*
144 * define SDMA_INT_FIND to get int bit rather than scan all bits use
145 * cntlzw
146 */
147
148/* Clear the IntPend bit */
149#define SDMA_CLEAR_IEVENT(RegAddr, Bit) { \
150 *((volatile uint32 *)RegAddr) = ((uint32)(1<<Bit)); \
151}
152
153#define SDMA_GET_PENDINGBIT(sdma, Bit) \
154 (sdma->IntPend & (uint32)(1<<Bit))
155
156#define SDMA_GET_MASKBIT(sdma, Bit) \
157 (sdma->IntMask & (uint32)(1<<Bit))
158
159
160/*******************************************************************************
161 * SmartDMA FIFO control macros
162 ******************************************************************************/
163
164/*******************************************************************************
165 * SmartDMA TEA detection control macros
166 ******************************************************************************/
167/* Enable SmartDMA TEA detection and TEA interrupt */
168#define SDMA_TEA_ENABLE(sdma) { \
169 SDMA_INT_ENABLE(sdma, SDMA_INT_BIT_TEA); \
170 sdma->PtdCntrl &= ~((uint32)(1<<SDMA_PTDCTRL_BIT_TEA)); \
171}
172
173/* Disable SmartDMA TEA detection and TEA interrupt */
174#define SDMA_TEA_DISABLE(sdma) { \
175 SDMA_INT_DISABLE(sdma, SDMA_INT_BIT_TEA); \
176 sdma->PtdCntrl |= ((uint32)(1<<SDMA_PTDCTRL_BIT_TEA)); \
177}
178
179/* Clear the TEA interrupt */
180#define SDMA_TEA_CLEAR(sdma) { \
181 sdma->IntPend = ((uint32)(0x1F<<SDMA_INT_BIT_TEA_TASK)); \
182}
183
184/* Determine which task caused a TEA on the XLB */
185#define SDMA_TEA_SOURCE(RegPend) \
186 (uint32)(((*(volatile uint32 *)RegPend)>>SDMA_INT_BIT_TEA_TASK) & 0xF)
187
188
189/*******************************************************************************
190 * SmartDMA debug control macros
191 ******************************************************************************/
192/* Enable the SmartDMA debug unit and DBG interrupt */
193/* add sdma->dbg_regs setup? */
194#define SDMA_DBG_ENABLE(sdma) { \
195 SDMA_INT_ENABLE(sdma, SDMA_INT_BIT_DBG); \
196}
197
198#define SDMA_DBG_DISABLE(sdma) { \
199 SDMA_INT_DISABLE(sdma, SDMA_INT_BIT_DBG); \
200}
201
202/* Clear the debug interrupt */
203#define SDMA_DBG_CLEAR(sdma) { \
204 SDMA_CLEAR_IEVENT(sdma, SDMA_INT_BIT_DBG); \
205}
206
207#define SDMA_DBG_MDE(dst, sdma, addr) { \
208 sdma->MDEDebug = addr; \
209 dst = sdma->MDEDebug; \
210}
211
212#define SDMA_DBG_ADS(dst, sdma, addr) { \
213 sdma->ADSDebug = addr; \
214 dst = sdma->ADSDebug; \
215}
216
217#define SDMA_DBG_PTD(dst, sdma, addr) { \
218 sdma->PTDDebug = addr; \
219 dst = sdma->PTDDebug; \
220}
221
222
223/*******************************************************************************
224 * Initiator control macros
225 ******************************************************************************/
226
227/* This macro may not work, getting compile errors */
228/* Set the Transfer Size */
229/* Note that masking the size w/ 0x3 gives the desired value for uint32 */
230/* (expressed as 4), namely 0. */
231#define SDMA_SET_SIZE(RegAddr, TaskNum, SrcSize, DstSize) \
232 *(((volatile uint8 *)RegAddr)+((uint32)(TaskNum/2))) = \
233 (uint8)((*(((volatile uint8 *)RegAddr)+((uint32)(TaskNum/2))) & \
234 ((TaskNum%2) ? 0xf0 : 0x0f)) | \
235 ((uint8)(((SrcSize & 0x3)<<2) | \
236 ( DstSize & 0x3 ) ) <<(4*((int)(1-(TaskNum%2))))));
237
238/* This macro may not work */
239/* Set the Initiator in TCR */
240#define SDMA_SET_INIT(RegAddr, TaskNum, Initiator) \
241{ \
242 *(((volatile uint16 *)RegAddr)+TaskNum) &= (uint16)0xE0FF; \
243 *(((volatile uint16 *)RegAddr)+TaskNum) |= (((0x01F & Initiator)<<8) | \
244 (0<<SDMA_TCR_BIT_HOLD)); \
245}
246
247/* Change DRD initiator number */
248#define SDMA_INIT_CHANGE(task, oldInitiator, newInitiator) { \
249 int i; \
250 for (i=0; i<task->NumDRD; i++) { \
251 if (SDMA_INIT_READ(task->DRD[i]) == (uint32)oldInitiator) { \
252 SDMA_INIT_WRITE(task->DRD[i],newInitiator); \
253 } \
254 } \
255}
256
257/* Set the Initiator Priority */
258#define SDMA_SET_INITIATOR_PRIORITY(sdma, initiator, priority) \
259 *(((volatile uint8 *)&sdma->IPR0)+initiator) = priority;
260
261
262/* Read DRD initiator number */
263#define SDMA_INIT_READ(PtrDRD) \
264 (((*(volatile uint32 *)PtrDRD)>>SDMA_DRD_BIT_INIT) & (uint32)0x1F)
265
266/* Write DRD initiator number */
267#define SDMA_INIT_WRITE(PtrDRD, Initiator) { \
268 *(volatile uint32 *)PtrDRD = ((*(volatile uint32 *)PtrDRD) & 0xFC1FFFFF) | \
269 (Initiator<<SDMA_DRD_BIT_INIT); \
270}
271
272/* Change DRD initiator number */
273#define SDMA_INIT_CHANGE(task, oldInitiator, newInitiator) { \
274 int i; \
275 for (i=0; i<task->NumDRD; i++) { \
276 if (SDMA_INIT_READ(task->DRD[i]) == (uint32)oldInitiator) { \
277 SDMA_INIT_WRITE(task->DRD[i],newInitiator); \
278 } \
279 } \
280}
281
282#endif /* __TASK_API_BESTCOMM_CNTRL_H */
Generated by doxygen 1.9.6