37#ifndef _RTEMS_SCORE_ARMV7_PMSA_H
38#define _RTEMS_SCORE_ARMV7_PMSA_H
42#include <rtems/score/cpu.h>
52#ifndef ARMV7_PMSA_TEXT_SECTION
53#define ARMV7_PMSA_TEXT_SECTION
69#define ARMV7_RGNR_REGION_SHIFT 0
70#define ARMV7_RGNR_REGION_MASK 0xffU
71#define ARMV7_RGNR_REGION_GET(_reg) \
72 (((_reg)&ARMV7_RGNR_REGION_MASK) >> ARMV7_RGNR_REGION_SHIFT)
73#define ARMV7_RGNR_REGION_SET(_reg, _val) \
74 (((_reg) & ~ARMV7_RGNR_REGION_MASK) | \
75 (((_val) << ARMV7_RGNR_REGION_SHIFT) & ARMV7_RGNR_REGION_MASK))
76#define ARMV7_RGNR_REGION(_val) \
77 (((_val) << ARMV7_RGNR_REGION_SHIFT) & ARMV7_RGNR_REGION_MASK)
79static inline uint32_t _ARMV7_Read_rgnr(
void) {
82 __asm__
volatile(
"mrc p15, 0, %0, c6, c2, 0" :
"=&r"(value) : :
"memory");
87static inline void _ARMV7_Write_rgnr(uint32_t value) {
88 __asm__
volatile(
"mcr p15, 0, %0, c6, c2, 0" : :
"r"(value) :
"memory");
93static inline uint32_t _ARMV7_Read_drbar(
void) {
96 __asm__
volatile(
"mrc p15, 0, %0, c6, c1, 0" :
"=&r"(value) : :
"memory");
101static inline void _ARMV7_Write_drbar(uint32_t value) {
102 __asm__
volatile(
"mcr p15, 0, %0, c6, c1, 0" : :
"r"(value) :
"memory");
107static inline uint32_t _ARMV7_Read_irbar(
void) {
110 __asm__
volatile(
"mrc p15, 0, %0, c6, c1, 1" :
"=&r"(value) : :
"memory");
115static inline void _ARMV7_Write_irbar(uint32_t value) {
116 __asm__
volatile(
"mcr p15, 0, %0, c6, c1, 1" : :
"r"(value) :
"memory");
119#define ARMV7_RSR_EN 0x1U
121#define ARMV7_RSR_RSIZE_SHIFT 1
122#define ARMV7_RSR_RSIZE_MASK 0x3eU
123#define ARMV7_RSR_RSIZE_GET(_reg) \
124 (((_reg)&ARMV7_RSR_RSIZE_MASK) >> ARMV7_RSR_RSIZE_SHIFT)
125#define ARMV7_RSR_RSIZE_SET(_reg, _val) \
126 (((_reg) & ~ARMV7_RSR_RSIZE_MASK) | \
127 (((_val) << ARMV7_RSR_RSIZE_SHIFT) & ARMV7_RSR_RSIZE_MASK))
128#define ARMV7_RSR_RSIZE(_val) \
129 (((_val) << ARMV7_RSR_RSIZE_SHIFT) & ARMV7_RSR_RSIZE_MASK)
131#define ARMV7_RSR_SD_SHIFT 8
132#define ARMV7_RSR_SD_MASK 0xff00U
133#define ARMV7_RSR_SD_GET(_reg) \
134 (((_reg)&ARMV7_RSR_SD_MASK) >> ARMV7_RSR_SD_SHIFT)
135#define ARMV7_RSR_SD_SET(_reg, _val) \
136 (((_reg) & ~ARMV7_RSR_SD_MASK) | \
137 (((_val) << ARMV7_RSR_SD_SHIFT) & ARMV7_RSR_SD_MASK))
138#define ARMV7_RSR_SD(_val) (((_val) << ARMV7_RSR_SD_SHIFT) & ARMV7_RSR_SD_MASK)
142static inline uint32_t _ARMV7_Read_drsr(
void) {
145 __asm__
volatile(
"mrc p15, 0, %0, c6, c1, 2" :
"=&r"(value) : :
"memory");
150static inline void _ARMV7_Write_drsr(uint32_t value) {
151 __asm__
volatile(
"mcr p15, 0, %0, c6, c1, 2" : :
"r"(value) :
"memory");
156static inline uint32_t _ARMV7_Read_irsr(
void) {
159 __asm__
volatile(
"mrc p15, 0, %0, c6, c1, 3" :
"=&r"(value) : :
"memory");
164static inline void _ARMV7_Write_irsr(uint32_t value) {
165 __asm__
volatile(
"mcr p15, 0, %0, c6, c1, 3" : :
"r"(value) :
"memory");
168#define ARMV7_RACR_B 0x1U
169#define ARMV7_RACR_C 0x2U
170#define ARMV7_RACR_S 0x4U
171#define ARMV7_RACR_TEX_0 0x8U
172#define ARMV7_RACR_TEX_1 0x10U
173#define ARMV7_RACR_TEX_2 0x20U
174#define ARMV7_RACR_AP_0 0x100U
175#define ARMV7_RACR_AP_1 0x200U
176#define ARMV7_RACR_AP_2 0x400U
177#define ARMV7_RACR_XN 0x1000U
181static inline uint32_t _ARMV7_Read_dracr(
void) {
184 __asm__
volatile(
"mrc p15, 0, %0, c6, c1, 4" :
"=&r"(value) : :
"memory");
189static inline void _ARMV7_Write_dracr(uint32_t value) {
190 __asm__
volatile(
"mcr p15, 0, %0, c6, c1, 4" : :
"r"(value) :
"memory");
195static inline uint32_t _ARMV7_Read_iracr(
void) {
198 __asm__
volatile(
"mrc p15, 0, %0, c6, c1, 5" :
"=&r"(value) : :
"memory");
203static inline void _ARMV7_Write_iracr(uint32_t value) {
204 __asm__
volatile(
"mcr p15, 0, %0, c6, c1, 5" : :
"r"(value) :
"memory");
207#define ARMV7_PMSA_READ_ONLY_CACHED \
208 (ARMV7_RACR_TEX_0 | ARMV7_RACR_C | ARMV7_RACR_B | ARMV7_RACR_AP_0 | \
211#define ARMV7_PMSA_READ_ONLY_UNCACHED \
212 (ARMV7_RACR_TEX_0 | ARMV7_RACR_AP_0 | ARMV7_RACR_AP_2)
214#define ARMV7_PMSA_READ_WRITE_CACHED \
215 (ARMV7_RACR_TEX_0 | ARMV7_RACR_C | ARMV7_RACR_B | ARMV7_RACR_AP_0)
217#define ARMV7_PMSA_READ_WRITE_UNCACHED (ARMV7_RACR_TEX_0 | ARMV7_RACR_AP_0)
219#define ARMV7_PMSA_READ_WRITE_SHARED \
220 (ARMV7_RACR_TEX_0 | ARMV7_RACR_S | ARMV7_RACR_AP_0)
222#define ARMV7_PMSA_SHAREABLE_DEVICE (ARMV7_RACR_B | ARMV7_RACR_AP_0)
224#define ARMV7_PMSA_NON_SHAREABLE_DEVICE (ARMV7_RACR_TEX_1 | ARMV7_RACR_AP_0)
249ARMV7_PMSA_TEXT_SECTION
static inline uint32_t _ARMV7_PMSA_Power2(uint32_t x) {
250 return 32 - __builtin_clz(x - 1U);
253ARMV7_PMSA_TEXT_SECTION
static inline uint32_t _ARMV7_PMSA_Ceil2(uint32_t x) {
254 return 1U << _ARMV7_PMSA_Power2(x);
257ARMV7_PMSA_TEXT_SECTION
static inline uint32_t _ARMV7_PMSA_Down2(uint32_t x,
263ARMV7_PMSA_TEXT_SECTION
static inline uint32_t _ARMV7_PMSA_Up2(uint32_t x,
269ARMV7_PMSA_TEXT_SECTION
static inline uint32_t
270_ARMV7_PMSA_Get_region(uint32_t b, uint32_t s, uint32_t* rs) {
272 uint32_t s2 = _ARMV7_PMSA_Ceil2(s);
273 uint32_t b2 = _ARMV7_PMSA_Down2(b, s2);
274 uint32_t e2 = _ARMV7_PMSA_Up2(
e, s2);
275 uint32_t s3 = _ARMV7_PMSA_Ceil2(e2 - b2);
277 return _ARMV7_PMSA_Down2(b2, s3);
280ARMV7_PMSA_TEXT_SECTION
static inline void _ARMV7_PMSA_Write_region(
287 int rp = _ARMV7_PMSA_Power2(rs);
289 uint32_t u = (b - rb) >> shift;
290 uint32_t v = (_ARMV7_PMSA_Up2(b + s, 1U << shift) - rb) >> shift;
291 uint32_t sub = ((0xffU >> (8 - v)) >> u) << u;
293 _ARMV7_Write_rgnr(ARMV7_RGNR_REGION(index));
294 _ARM_Instruction_synchronization_barrier();
295 _ARMV7_Write_drbar(rb);
296 _ARMV7_Write_dracr(attr);
297 _ARMV7_Write_drsr(ARMV7_RSR_SD(~sub) | ARMV7_RSR_RSIZE(rp - 1) |
299 _ARM_Data_synchronization_barrier();
300 _ARM_Instruction_synchronization_barrier();
303ARMV7_PMSA_TEXT_SECTION
static inline uint32_t
304_ARMV7_PMSA_Add_regions(uint32_t index, uint32_t b, uint32_t s, uint32_t attr) {
306 uint32_t rb = _ARMV7_PMSA_Get_region(b, s, &rs);
310 uint32_t re = rb + rs;
312 uint32_t sl = re - b;
314 rb = _ARMV7_PMSA_Get_region(bl, sl, &rs);
315 _ARMV7_PMSA_Write_region(index, bl, sl, rb, rs, attr);
320 rb = _ARMV7_PMSA_Get_region(b, s, &rs);
323 _ARMV7_PMSA_Write_region(index, b, s, rb, rs, attr);
327ARMV7_PMSA_TEXT_SECTION
static inline uint32_t _ARMV7_PMSA_Get_max_regions(
331 uint32_t region_count = _AArch32_Read_mpuir();
333 region_count &= AARCH32_MPUIR_REGION_MASK;
334 region_count >>= AARCH32_MPUIR_REGION_SHIFT;
339ARMV7_PMSA_TEXT_SECTION
static inline uint32_t _ARMV7_PMSA_Find_region(
342 uint32_t region_count = _ARMV7_PMSA_Get_max_regions();
344 while (index < region_count) {
345 _ARMV7_Write_rgnr(ARMV7_RGNR_REGION(index));
346 _ARM_Instruction_synchronization_barrier();
348 uint32_t rsr = _ARMV7_Read_drsr();
350 if ((rsr & ARMV7_RSR_EN) != 0) {
351 uint32_t rbar = _ARMV7_Read_drbar();
352 uint32_t offset = (address & ~UINT32_C(0x3)) - rbar;
353 uint32_t region_power = ARMV7_RSR_RSIZE_GET(rsr) + 1;
354 uint32_t region_size = UINT32_C(1) << region_power;
356 if (offset < region_size) {
357 if (region_size < 256) {
361 uint32_t sub = offset >> (region_power - 3);
363 if ((ARMV7_RSR_SD_GET(rsr) & (UINT32_C(1) << sub)) == 0) {
375ARMV7_PMSA_TEXT_SECTION
376static inline bool _ARMV7_PMSA_Is_region_enabled(uint32_t index)
378 _Assert(index < _ARMV7_PMSA_Get_max_regions());
380 _ARMV7_Write_rgnr(ARMV7_RGNR_REGION(index));
381 _ARM_Instruction_synchronization_barrier();
383 return (_ARMV7_Read_drsr() & ARMV7_RSR_EN) != 0;
386ARMV7_PMSA_TEXT_SECTION
387static inline uint32_t _ARMV7_PMSA_Find_available_region(
void)
389 uint32_t region_count = _ARMV7_PMSA_Get_max_regions();
392 for (index = 0; index < region_count; index++) {
393 if (!_ARMV7_PMSA_Is_region_enabled(index)) {
This header file provides the API to read and write the AArch32 system registers.
This header file provides the interfaces of the Assert Handler.
#define _Assert(_e)
Assertion similar to assert() controlled via RTEMS_DEBUG instead of NDEBUG and static analysis runs.
Definition: assert.h:96
The region definition is used to initialize the Memory Protection Unit (MPU).
Definition: armv7-pmsa.h:232
uint32_t size
This member defines the size in bytes of the region.
Definition: armv7-pmsa.h:241
uint32_t begin
This member defines the begin address of the region.
Definition: armv7-pmsa.h:236
uint32_t attributes
This member defines the attributes of the region.
Definition: armv7-pmsa.h:246
unsigned e
Definition: tlb.h:13