38#ifndef _RTEMS_DEV_IRQ_ARM_GICV3_H
39#define _RTEMS_DEV_IRQ_ARM_GICV3_H
42#include <dev/irq/arm-gic-arch.h>
54#define PRIORITY_DEFAULT 127
56#define MPIDR_AFFINITY2(val) BSP_FLD64(val, 16, 23)
57#define MPIDR_AFFINITY2_GET(reg) BSP_FLD64GET(reg, 16, 23)
58#define MPIDR_AFFINITY2_SET(reg, val) BSP_FLD64SET(reg, val, 16, 23)
59#define MPIDR_AFFINITY1(val) BSP_FLD64(val, 8, 15)
60#define MPIDR_AFFINITY1_GET(reg) BSP_FLD64GET(reg, 8, 15)
61#define MPIDR_AFFINITY1_SET(reg, val) BSP_FLD64SET(reg, val, 8, 15)
62#define MPIDR_AFFINITY0(val) BSP_FLD64(val, 0, 7)
63#define MPIDR_AFFINITY0_GET(reg) BSP_FLD64GET(reg, 0, 7)
64#define MPIDR_AFFINITY0_SET(reg, val) BSP_FLD64SET(reg, val, 0, 7)
66#define ICC_SGIR_AFFINITY3(val) BSP_FLD64(val, 48, 55)
67#define ICC_SGIR_AFFINITY3_GET(reg) BSP_FLD64GET(reg, 48, 55)
68#define ICC_SGIR_AFFINITY3_SET(reg, val) BSP_FLD64SET(reg, val, 48, 55)
69#define ICC_SGIR_IRM BSP_BIT32(40)
70#define ICC_SGIR_AFFINITY2(val) BSP_FLD64(val, 32, 39)
71#define ICC_SGIR_AFFINITY2_GET(reg) BSP_FLD64GET(reg, 32, 39)
72#define ICC_SGIR_AFFINITY2_SET(reg, val) BSP_FLD64SET(reg, val, 32, 39)
73#define ICC_SGIR_INTID(val) BSP_FLD64(val, 24, 27)
74#define ICC_SGIR_INTID_GET(reg) BSP_FLD64GET(reg, 24, 27)
75#define ICC_SGIR_INTID_SET(reg, val) BSP_FLD64SET(reg, val, 24, 27)
76#define ICC_SGIR_AFFINITY1(val) BSP_FLD64(val, 16, 23)
77#define ICC_SGIR_AFFINITY1_GET(reg) BSP_FLD64GET(reg, 16, 23)
78#define ICC_SGIR_AFFINITY1_SET(reg, val) BSP_FLD64SET(reg, val, 16, 23)
79#define ICC_SGIR_CPU_TARGET_LIST(val) BSP_FLD64(val, 0, 15)
80#define ICC_SGIR_CPU_TARGET_LIST_GET(reg) BSP_FLD64GET(reg, 0, 15)
81#define ICC_SGIR_CPU_TARGET_LIST_SET(reg, val) BSP_FLD64SET(reg, val, 0, 15)
83#ifdef ARM_MULTILIB_ARCH_V4
85#define ICC_CTLR "p15, 0, %0, c12, c12, 4"
88#define ICC_PMR "p15, 0, %0, c4, c6, 0"
91#define ICC_BPR0 "p15, 0, %0, c12, c8, 3"
92#define ICC_BPR1 "p15, 0, %0, c12, c12, 3"
95#define ICC_IAR0 "p15, 0, %0, c12, c8, 0"
96#define ICC_IAR1 "p15, 0, %0, c12, c12, 0"
99#define ICC_EOIR0 "p15, 0, %0, c12, c8, 1"
100#define ICC_EOIR1 "p15, 0, %0, c12, c12, 1"
102#define ICC_SRE "p15, 0, %0, c12, c12, 5"
104#define ICC_IGRPEN0 "p15, 0, %0, c12, c12, 6"
105#define ICC_IGRPEN1 "p15, 0, %0, c12, c12, 7"
107#define MPIDR "p15, 0, %0, c0, c0, 5"
109#define READ_SR(SR_NAME) \
112 __asm__ volatile("mrc " SR_NAME : "=r" (value) ); \
116#define WRITE_SR(SR_NAME, VALUE) \
117 __asm__ volatile("mcr " SR_NAME " \n" : : "r" (VALUE) );
119#define ICC_SGI1 "p15, 0, %Q0, %R0, c12"
120#define WRITE64_SR(SR_NAME, VALUE) \
121 __asm__ volatile("mcrr " SR_NAME " \n" : : "r" (VALUE) );
126#define ICC_IGRPEN0_EL1 "S3_0_C12_C12_6, %0"
127#define ICC_IGRPEN1_EL1 "S3_0_C12_C12_7, %0"
128#define ICC_IGRPEN1_EL3 "S3_6_C12_C12_7, %0"
129#define ICC_IGRPEN0 ICC_IGRPEN0_EL1
130#define ICC_IGRPEN1 ICC_IGRPEN1_EL1
131#define ICC_PMR "S3_0_C4_C6_0, %0"
132#define ICC_EOIR1 "S3_0_C12_C12_1, %0"
133#define ICC_SRE "S3_0_C12_C12_5, %0"
134#define ICC_BPR0 "S3_0_C12_C8_3, %0"
135#define ICC_BPR1 "S3_0_C12_C12_3, %0"
136#define ICC_CTLR "S3_0_C12_C12_4, %0"
137#define ICC_IAR1 "%0, S3_0_C12_C12_0"
138#define MPIDR "%0, mpidr_el1"
139#define MPIDR_AFFINITY3(val) BSP_FLD64(val, 32, 39)
140#define MPIDR_AFFINITY3_GET(reg) BSP_FLD64GET(reg, 32, 39)
141#define MPIDR_AFFINITY3_SET(reg, val) BSP_FLD64SET(reg, val, 32, 39)
143#define ICC_SGI1 "S3_0_C12_C11_5, %0"
144#define WRITE64_SR(SR_NAME, VALUE) \
145 __asm__ volatile("msr " SR_NAME " \n" : : "r" (VALUE) );
146#define WRITE_SR(SR_NAME, VALUE) WRITE64_SR(SR_NAME, VALUE)
148#define READ_SR(SR_NAME) \
151 __asm__ volatile("mrs " SR_NAME : "=&r" (value) ); \
157static inline volatile gic_redist *gicv3_get_redist(uint32_t cpu_index)
160 ((uintptr_t)BSP_ARM_GIC_REDIST_BASE + cpu_index * 0x20000);
163static inline volatile gic_sgi_ppi *gicv3_get_sgi_ppi(uint32_t cpu_index)
166 ((uintptr_t)BSP_ARM_GIC_REDIST_BASE + cpu_index * 0x20000 + 0x10000);
169static inline void gicv3_sgi_ppi_enable(
174 volatile gic_sgi_ppi *sgi_ppi = gicv3_get_sgi_ppi(cpu_index);
177 sgi_ppi->icspigrpr[0] |= 1U << vector;
178 sgi_ppi->icspigrpmodr[0] &= ~(1U << vector);
181 sgi_ppi->icspiser[0] = 1U << vector;
184static inline void gicv3_sgi_ppi_disable(
189 volatile gic_sgi_ppi *sgi_ppi = gicv3_get_sgi_ppi(cpu_index);
191 sgi_ppi->icspicer[0] = 1U << vector;
194static inline bool gicv3_sgi_ppi_is_enabled(
199 volatile gic_sgi_ppi *sgi_ppi = gicv3_get_sgi_ppi(cpu_index);
201 return (sgi_ppi->icspiser[0] & (1U << vector)) != 0;
204static inline void gicv3_sgi_ppi_set_priority(
210 volatile gic_sgi_ppi *sgi_ppi = gicv3_get_sgi_ppi(cpu_index);
212 sgi_ppi->icspiprior[vector] = priority;
215static inline uint8_t gicv3_sgi_ppi_get_priority(
220 volatile gic_sgi_ppi *sgi_ppi = gicv3_get_sgi_ppi(cpu_index);
222 return sgi_ppi->icspiprior[vector];
225static inline bool gicv3_sgi_ppi_is_pending(
230 volatile gic_sgi_ppi *sgi_ppi = gicv3_get_sgi_ppi(cpu_index);
232 return (sgi_ppi->icspispendr[0] & (1U << vector)) != 0;
235static inline void gicv3_ppi_set_pending(
240 volatile gic_sgi_ppi *sgi_ppi = gicv3_get_sgi_ppi(cpu_index);
242 sgi_ppi->icspispendr[0] = 1U << vector;
245static inline void gicv3_ppi_clear_pending(
250 volatile gic_sgi_ppi *sgi_ppi = gicv3_get_sgi_ppi(cpu_index);
252 sgi_ppi->icspicpendr[0] = 1U << vector;
255static inline void gicv3_trigger_sgi(
260#ifndef ARM_MULTILIB_ARCH_V4
265 mpidr = READ_SR(MPIDR);
266 uint64_t value = ICC_SGIR_AFFINITY2(MPIDR_AFFINITY2_GET(mpidr))
267 | ICC_SGIR_INTID(vector)
268 | ICC_SGIR_AFFINITY1(MPIDR_AFFINITY1_GET(mpidr))
269 | ICC_SGIR_CPU_TARGET_LIST(targets);
270#ifndef ARM_MULTILIB_ARCH_V4
271 value |= ICC_SGIR_AFFINITY3(MPIDR_AFFINITY3_GET(mpidr));
273 WRITE64_SR(ICC_SGI1, value);
276static inline uint32_t gicv3_get_id_count(
volatile gic_dist *dist)
278 uint32_t id_count = GIC_DIST_ICDICTR_IT_LINES_NUMBER_GET(dist->icdictr);
280 id_count = 32 * (id_count + 1);
281 id_count = id_count <= 1020 ? id_count : 1020;
286static void gicv3_init_dist(
volatile gic_dist *dist)
288 uint32_t id_count = gicv3_get_id_count(dist);
291 dist->icddcr = GIC_DIST_ICDDCR_ARE_NS | GIC_DIST_ICDDCR_ARE_S
292 | GIC_DIST_ICDDCR_ENABLE_GRP1S | GIC_DIST_ICDDCR_ENABLE_GRP1NS
293 | GIC_DIST_ICDDCR_ENABLE_GRP0;
295 for (
id = 0;
id < id_count;
id += 32) {
297 dist->icdicer[
id / 32] = 0xffffffff;
300 dist->icdigr[
id / 32] = 0xffffffff;
301 dist->icdigmr[
id / 32] = 0;
304 for (
id = 0;
id < id_count; ++id) {
305 gic_id_set_priority(dist,
id, PRIORITY_DEFAULT);
308 for (
id = 32;
id < id_count; ++id) {
309 gic_id_set_targets(dist,
id, 0x01);
313static void gicv3_init_cpu_interface(uint32_t cpu_index)
316#ifdef BSP_ARM_GIC_ICC_SRE
317 WRITE_SR(ICC_SRE, BSP_ARM_GIC_ICC_SRE);
321#ifdef BSP_ARM_GIC_ICC_PMR
322 WRITE_SR(ICC_PMR, BSP_ARM_GIC_ICC_PMR);
326#ifdef BSP_ARM_GIC_ICC_BPR0
327 WRITE_SR(ICC_BPR0, BSP_ARM_GIC_ICC_BPR0);
331#ifdef BSP_ARM_GIC_ICC_BPR1
332 WRITE_SR(ICC_BPR1, BSP_ARM_GIC_ICC_BPR1);
335 volatile gic_redist *redist = gicv3_get_redist(cpu_index);
336 uint32_t waker = redist->icrwaker;
337 uint32_t waker_mask = GIC_REDIST_ICRWAKER_PROCESSOR_SLEEP;
338 waker &= ~waker_mask;
339 redist->icrwaker = waker;
341 volatile gic_sgi_ppi *sgi_ppi = gicv3_get_sgi_ppi(cpu_index);
343 sgi_ppi->icspigrpr[0] = 0xffffffff;
344 sgi_ppi->icspigrpmodr[0] = 0;
345 for (
int id = 0;
id < 32;
id++) {
346 sgi_ppi->icspiprior[id] = PRIORITY_DEFAULT;
350#ifdef BSP_ARM_GIC_ICC_IGRPEN0
351 WRITE_SR(ICC_IGRPEN0, BSP_ARM_GIC_ICC_IGRPEN0);
355#ifdef BSP_ARM_GIC_ICC_IGRPEN1
356 WRITE_SR(ICC_IGRPEN1, BSP_ARM_GIC_ICC_IGRPEN1);
360#ifdef BSP_ARM_GIC_ICC_CTRL
361 WRITE_SR(ICC_CTLR, BSP_ARM_GIC_ICC_CTRL);
365static inline void gicv3_get_attributes(
378 if ( vector <= ARM_GIC_IRQ_SGI_LAST ) {
392 if ( vector > ARM_GIC_IRQ_PPI_LAST ) {
This header file provides interfaces of the ARM Generic Interrupt Controller (GIC) support.
ISR_Vector_number rtems_vector_number
This integer type represents interrupt vector numbers.
Definition: intr.h:102
@ RTEMS_INTERRUPT_NO_SIGNAL
This interrupt signal variant indicates that the interrupt cannot be triggered by a signal.
Definition: intr.h:2039
@ RTEMS_INTERRUPT_UNSPECIFIED_SIGNAL
This interrupt signal variant indicates that the interrupt trigger signal is unspecified.
Definition: intr.h:2033
Definition: arm-gic-regs.h:108
Definition: arm-gic-regs.h:217
Definition: arm-gic-regs.h:249
This structure provides the attributes of an interrupt vector.
Definition: intr.h:2076
bool can_raise_on
This member is true, if the interrupt vector can be raised on a processor by rtems_interrupt_raise_on...
Definition: intr.h:2140
bool can_disable
This member is true, if the interrupt vector can be disabled by rtems_interrupt_vector_disable(),...
Definition: intr.h:2117
bool can_set_priority
This member is true, if the priority of the interrupt vector can be set by rtems_interrupt_set_priori...
Definition: intr.h:2198
bool maybe_enable
This member is true, if the interrupt vector may be enabled by rtems_interrupt_vector_enable(),...
Definition: intr.h:2107
rtems_interrupt_signal_variant trigger_signal
This member describes the trigger signal of the interrupt associated with the interrupt vector.
Definition: intr.h:2186
bool can_raise
This member is true, if the interrupt vector can be raised by rtems_interrupt_raise(),...
Definition: intr.h:2134
bool can_clear
This member is true, if the interrupt vector can be cleared by rtems_interrupt_clear(),...
Definition: intr.h:2146
bool can_set_affinity
This member is true, if the affinity set of the interrupt vector can be set by rtems_interrupt_set_af...
Definition: intr.h:2165
bool cleared_by_acknowledge
This member is true, if the pending status of the interrupt associated with the interrupt vector is c...
Definition: intr.h:2153
uint32_t maximum_priority
This member represents the maximum priority value of the interrupt vector. By convention,...
Definition: intr.h:2209
bool maybe_disable
This member is true, if the interrupt vector may be disabled by rtems_interrupt_vector_disable(),...
Definition: intr.h:2128
bool can_get_priority
This member is true, if the priority of the interrupt vector can be obtained by rtems_interrupt_get_p...
Definition: intr.h:2192
bool is_maskable
This member is true, if the interrupt vector is maskable by rtems_interrupt_local_disable(),...
Definition: intr.h:2085
bool can_get_affinity
This member is true, if the affinity set of the interrupt vector can be obtained by rtems_interrupt_g...
Definition: intr.h:2159