RTEMS 6.1-rc6
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arm-gic-tm27.h
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1/* SPDX-License-Identifier: BSD-2-Clause */
2
12/*
13 * Copyright (C) 2013, 2014 embedded brains GmbH & Co. KG
14 *
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions
17 * are met:
18 * 1. Redistributions of source code must retain the above copyright
19 * notice, this list of conditions and the following disclaimer.
20 * 2. Redistributions in binary form must reproduce the above copyright
21 * notice, this list of conditions and the following disclaimer in the
22 * documentation and/or other materials provided with the distribution.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
28 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
35 */
36
37#ifndef _RTEMS_TMTEST27
38#error "This is an RTEMS internal file you must not include directly."
39#endif
40
41#ifndef LIBBSP_ARM_SHARED_ARM_GIC_TM27_H
42#define LIBBSP_ARM_SHARED_ARM_GIC_TM27_H
43
44#include <bsp.h>
45#include <bsp/irq.h>
46
47#include <rtems/score/assert.h>
48
49#define MUST_WAIT_FOR_INTERRUPT 1
50
51#ifndef ARM_GIC_TM27_IRQ_LOW
52#define ARM_GIC_TM27_IRQ_LOW ARM_GIC_IRQ_SGI_12
53#endif
54
55#ifndef ARM_GIC_TM27_IRQ_HIGH
56#define ARM_GIC_TM27_IRQ_HIGH ARM_GIC_IRQ_SGI_13
57#endif
58
59#define TM27_INTERRUPT_VECTOR_DEFAULT ARM_GIC_TM27_IRQ_LOW
60
61#define ARM_GIC_TM27_PRIO_LOW 0x80
62
63#define ARM_GIC_TM27_PRIO_HIGH 0x00
64
65static inline void Install_tm27_vector( rtems_interrupt_handler handler )
66{
67 static rtems_interrupt_entry entry_low;
68 static rtems_interrupt_entry entry_high;
70
71 rtems_interrupt_entry_initialize(
72 &entry_low,
73 handler,
74 NULL,
75 "tm27 low"
76 );
78 ARM_GIC_TM27_IRQ_LOW,
80 &entry_low
81 );
83
85 ARM_GIC_TM27_IRQ_LOW,
86 ARM_GIC_TM27_PRIO_LOW
87 );
89
90 rtems_interrupt_entry_initialize(
91 &entry_high,
92 handler,
93 NULL,
94 "tm27 high"
95 );
97 ARM_GIC_TM27_IRQ_HIGH,
99 &entry_high
100 );
102
104 ARM_GIC_TM27_IRQ_HIGH,
105 ARM_GIC_TM27_PRIO_HIGH
106 );
108}
109
110static inline void Cause_tm27_intr(void)
111{
113
115 ARM_GIC_TM27_IRQ_LOW,
116 _SMP_Get_current_processor()
117 );
119}
120
121static inline void Clear_tm27_intr(void)
122{
123 /* Nothing to do */
124}
125
126static inline void Lower_tm27_intr(void)
127{
129
131 ARM_GIC_TM27_IRQ_HIGH,
132 _SMP_Get_current_processor()
133 );
135}
136
137#endif /* LIBBSP_ARM_SHARED_ARM_GIC_TM27_H */
This header file provides the interfaces of the Assert Handler.
rtems_status_code rtems_interrupt_entry_install(rtems_vector_number vector, rtems_option options, rtems_interrupt_entry *entry)
Installs the interrupt entry at the interrupt vector.
Definition: irq-generic.c:264
#define RTEMS_INTERRUPT_UNIQUE
This interrupt handler install option ensures that the interrupt handler is unique.
Definition: intr.h:972
rtems_status_code rtems_interrupt_raise_on(rtems_vector_number vector, uint32_t cpu_index)
Raises the interrupt vector on the processor.
Definition: irq-raise-clear.c:68
void(* rtems_interrupt_handler)(void *)
Interrupt handler routines shall have this type.
Definition: intr.h:1030
rtems_status_code rtems_interrupt_set_priority(rtems_vector_number vector, uint32_t priority)
Sets the priority of the interrupt vector.
Definition: irq-priority.c:39
rtems_status_code
This enumeration provides status codes for directives of the Classic API.
Definition: status.h:85
@ RTEMS_SUCCESSFUL
This status code indicates successful completion of a requested operation.
Definition: status.h:90
#define _Assert_Unused_variable_equals(_var, _val)
Assert if unused return value is equal.
Definition: assert.h:108
This structure represents an interrupt entry.
Definition: intr.h:1070