RTEMS 6.1-rc6
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arm-gic-irq.h
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1/* SPDX-License-Identifier: BSD-2-Clause */
2
12/*
13 * Copyright (C) 2013, 2019 embedded brains GmbH & Co. KG
14 *
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions
17 * are met:
18 * 1. Redistributions of source code must retain the above copyright
19 * notice, this list of conditions and the following disclaimer.
20 * 2. Redistributions in binary form must reproduce the above copyright
21 * notice, this list of conditions and the following disclaimer in the
22 * documentation and/or other materials provided with the distribution.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
28 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
35 */
36
37#ifndef LIBBSP_ARM_SHARED_ARM_GIC_IRQ_H
38#define LIBBSP_ARM_SHARED_ARM_GIC_IRQ_H
39
40#include <bsp.h>
41#include <dev/irq/arm-gic.h>
42
43#ifdef __cplusplus
44extern "C" {
45#endif /* __cplusplus */
46
53#define ARM_GIC_IRQ_SGI_0 0
54#define ARM_GIC_IRQ_SGI_1 1
55#define ARM_GIC_IRQ_SGI_2 2
56#define ARM_GIC_IRQ_SGI_3 3
57#define ARM_GIC_IRQ_SGI_5 5
58#define ARM_GIC_IRQ_SGI_6 6
59#define ARM_GIC_IRQ_SGI_7 7
60#define ARM_GIC_IRQ_SGI_8 8
61#define ARM_GIC_IRQ_SGI_9 9
62#define ARM_GIC_IRQ_SGI_10 10
63#define ARM_GIC_IRQ_SGI_11 11
64#define ARM_GIC_IRQ_SGI_12 12
65#define ARM_GIC_IRQ_SGI_13 13
66#define ARM_GIC_IRQ_SGI_14 14
67#define ARM_GIC_IRQ_SGI_15 15
68#define ARM_GIC_IRQ_SGI_LAST 15
69
70#define ARM_GIC_IRQ_PPI_LAST 31
71
72#define ARM_GIC_DIST ((volatile gic_dist *) BSP_ARM_GIC_DIST_BASE)
73
74rtems_status_code arm_gic_irq_set_group(
76 gic_group group
77);
78
79rtems_status_code arm_gic_irq_get_group(
81 gic_group *group
82);
83
84void arm_gic_trigger_sgi(rtems_vector_number vector, uint32_t targets);
85
86#ifdef RTEMS_SMP
87uint32_t arm_gic_irq_processor_count(void);
88
89void arm_gic_irq_initialize_secondary_cpu(void);
90#endif
91
94#ifdef __cplusplus
95}
96#endif /* __cplusplus */
97
98#endif /* LIBBSP_ARM_SHARED_ARM_GIC_IRQ_H */
This header file provides interfaces of the ARM Generic Interrupt Controller (GIC) support.
ISR_Vector_number rtems_vector_number
This integer type represents interrupt vector numbers.
Definition: intr.h:102
rtems_status_code
This enumeration provides status codes for directives of the Classic API.
Definition: status.h:85