RTEMS 6.1-rc5
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zynq-slcr.h
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1/* SPDX-License-Identifier: BSD-2-Clause */
2
9/*
10 *
11 * Copyright (c) 2017
12 * NSF Center for High-Performance Reconfigurable Computing (CHREC),
13 * University of Pittsburgh. All rights reserved.
14 *
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions are
17 * met:
18 * 1. Redistributions of source code must retain the above copyright
19 * notice, this list of conditions and the following disclaimer.
20 * 2. Redistributions in binary form must reproduce the above copyright
21 * notice, this list of conditions and the following disclaimer in the
22 * documentation and/or other materials provided with the distribution.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
25 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
27 * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER
28 * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
29 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
30 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
31 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
32 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
33 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
34 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 *
36 * The views and conclusions contained in the software and documentation
37 * are those of the authors and should not be interpreted as representing
38 * official policies, either expressed or implied, of CHREC.
39 *
40 * Author: Patrick Gauvin <gauvin@hcs.ufl.edu>
41 */
42
49#ifndef LIBBSP_ARM_XILINX_ZYNQ_SLCR_H
50#define LIBBSP_ARM_XILINX_ZYNQ_SLCR_H
51
52#include <stdint.h>
53
54#ifdef __cplusplus
55extern "C" {
56#endif /* __cplusplus */
57
66 uint32_t mask
67);
68
76 uint32_t val
77);
78
86 uint32_t val
87);
88
89#ifdef __cplusplus
90}
91#endif /* __cplusplus */
92
93#endif /* LIBBSP_ARM_XILINX_ZYNQ_SLCR_H */
void zynq_slcr_level_shifter_enable(uint32_t val)
Control the level shifters between the PS and PL.
Definition: zynq-slcr.c:95
void zynq_slcr_fpga_clk_rst_mask_set(uint32_t mask)
Set the mask that allows the FPGA resets to be modified.
Definition: zynq-slcr.c:62
void zynq_slcr_fpga_clk_rst(uint32_t val)
Control the FPGA reset values.
Definition: zynq-slcr.c:73