RTEMS 6.1-rc5
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xqspipsu_hw.h
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1/******************************************************************************
2* Copyright (C) 2014 - 2022 Xilinx, Inc. All rights reserved.
3* SPDX-License-Identifier: MIT
4******************************************************************************/
5
6/*****************************************************************************/
37#ifndef XQSPIPSU_HW_H
38#define XQSPIPSU_HW_H
40#ifdef __cplusplus
41extern "C" {
42#endif
43
44/***************************** Include Files *********************************/
45
46#ifndef __rtems__
47#include "xil_types.h"
48#include "xil_assert.h"
49#include "xil_io.h"
50#include "xparameters.h"
51#else
52#include <bsp/xil-compat.h>
53#endif
54
55/************************** Constant Definitions *****************************/
64#if defined (versal)
65#define XQSPIPS_BASEADDR 0XF1030000U
66#else
67#define XQSPIPS_BASEADDR 0XFF0F0000U
68#endif
69
70#if defined (versal)
71#define XQSPIPSU_BASEADDR 0XF1030100U
72#else
73#define XQSPIPSU_BASEADDR 0xFF0F0100U
74#endif
75#define XQSPIPSU_OFFSET 0x100U
86#define XQSPIPS_EN_REG ( ( XQSPIPS_BASEADDR ) + 0X00000014U )
87#define XQSPIPS_EN_SHIFT 0U
88#define XQSPIPS_EN_WIDTH 1U
89#define XQSPIPS_EN_MASK 0X00000001U
100#define XQSPIPSU_CFG_OFFSET 0X00000000U
101
102#define XQSPIPSU_CFG_MODE_EN_SHIFT 30U
103#define XQSPIPSU_CFG_MODE_EN_WIDTH 2U
104#define XQSPIPSU_CFG_MODE_EN_MASK 0XC0000000U
105#define XQSPIPSU_CFG_MODE_EN_DMA_MASK 0X80000000U
106
107#define XQSPIPSU_CFG_GEN_FIFO_START_MODE_SHIFT 29U
108#define XQSPIPSU_CFG_GEN_FIFO_START_MODE_WIDTH 1U
109#define XQSPIPSU_CFG_GEN_FIFO_START_MODE_MASK 0X20000000U
110
111#define XQSPIPSU_CFG_START_GEN_FIFO_SHIFT 28U
112#define XQSPIPSU_CFG_START_GEN_FIFO_WIDTH 1U
113#define XQSPIPSU_CFG_START_GEN_FIFO_MASK 0X10000000U
114
115#define XQSPIPSU_CFG_ENDIAN_SHIFT 26U
116#define XQSPIPSU_CFG_ENDIAN_WIDTH 1U
117#define XQSPIPSU_CFG_ENDIAN_MASK 0X04000000U
118
119#define XQSPIPSU_CFG_EN_POLL_TO_SHIFT 20U
120#define XQSPIPSU_CFG_EN_POLL_TO_WIDTH 1U
121#define XQSPIPSU_CFG_EN_POLL_TO_MASK 0X00100000U
122
123#define XQSPIPSU_CFG_WP_HOLD_SHIFT 19U
124#define XQSPIPSU_CFG_WP_HOLD_WIDTH 1U
125#define XQSPIPSU_CFG_WP_HOLD_MASK 0X00080000U
126
127#define XQSPIPSU_CFG_BAUD_RATE_DIV_SHIFT 3U
128#define XQSPIPSU_CFG_BAUD_RATE_DIV_WIDTH 3U
129#define XQSPIPSU_CFG_BAUD_RATE_DIV_MASK 0X00000038U
130
131#define XQSPIPSU_CFG_CLK_PHA_SHIFT 2U
132#define XQSPIPSU_CFG_CLK_PHA_WIDTH 1U
133#define XQSPIPSU_CFG_CLK_PHA_MASK 0X00000004U
134
135#define XQSPIPSU_CFG_CLK_POL_SHIFT 1U
136#define XQSPIPSU_CFG_CLK_POL_WIDTH 1U
137#define XQSPIPSU_CFG_CLK_POL_MASK 0X00000002U
148#if !defined (versal)
149#define XQSPIPSU_LQSPI_CR_OFFSET 0X000000A0U
150#define XQSPIPSU_LQSPI_CR_LINEAR_MASK 0x80000000U
151#define XQSPIPSU_LQSPI_CR_TWO_MEM_MASK 0x40000000U
152#define XQSPIPSU_LQSPI_CR_SEP_BUS_MASK 0x20000000U
153#define XQSPIPSU_LQSPI_CR_U_PAGE_MASK 0x10000000U
154#define XQSPIPSU_LQSPI_CR_ADDR_32BIT_MASK 0x01000000U
155#define XQSPIPSU_LQSPI_CR_MODE_EN_MASK 0x02000000U
156#define XQSPIPSU_LQSPI_CR_MODE_ON_MASK 0x01000000U
157#define XQSPIPSU_LQSPI_CR_MODE_BITS_MASK 0x00FF0000U
159#define XQSPIPS_LQSPI_CR_INST_MASK 0x000000FFU
160#define XQSPIPS_LQSPI_CR_RST_STATE 0x80000003U
161#define XQSPIPS_LQSPI_CR_4_BYTE_STATE 0x88000013U
162#define XQSPIPS_LQSPI_CFG_RST_STATE 0x800238C1U
163#endif
174#define XQSPIPSU_ISR_OFFSET 0X00000004U
175
176#define XQSPIPSU_ISR_RXEMPTY_SHIFT 11U
177#define XQSPIPSU_ISR_RXEMPTY_WIDTH 1U
178#define XQSPIPSU_ISR_RXEMPTY_MASK 0X00000800U
179
180#define XQSPIPSU_ISR_GENFIFOFULL_SHIFT 10U
181#define XQSPIPSU_ISR_GENFIFOFULL_WIDTH 1U
182#define XQSPIPSU_ISR_GENFIFOFULL_MASK 0X00000400U
183
184#define XQSPIPSU_ISR_GENFIFONOT_FULL_SHIFT 9U
185#define XQSPIPSU_ISR_GENFIFONOT_FULL_WIDTH 1U
186#define XQSPIPSU_ISR_GENFIFONOT_FULL_MASK 0X00000200U
187
188#define XQSPIPSU_ISR_TXEMPTY_SHIFT 8U
189#define XQSPIPSU_ISR_TXEMPTY_WIDTH 1U
190#define XQSPIPSU_ISR_TXEMPTY_MASK 0X00000100U
191
192#define XQSPIPSU_ISR_GENFIFOEMPTY_SHIFT 7U
193#define XQSPIPSU_ISR_GENFIFOEMPTY_WIDTH 1U
194#define XQSPIPSU_ISR_GENFIFOEMPTY_MASK 0X00000080U
195
196#define XQSPIPSU_ISR_RXFULL_SHIFT 5U
197#define XQSPIPSU_ISR_RXFULL_WIDTH 1U
198#define XQSPIPSU_ISR_RXFULL_MASK 0X00000020U
199
200#define XQSPIPSU_ISR_RXNEMPTY_SHIFT 4U
201#define XQSPIPSU_ISR_RXNEMPTY_WIDTH 1U
202#define XQSPIPSU_ISR_RXNEMPTY_MASK 0X00000010U
203
204#define XQSPIPSU_ISR_TXFULL_SHIFT 3U
205#define XQSPIPSU_ISR_TXFULL_WIDTH 1U
206#define XQSPIPSU_ISR_TXFULL_MASK 0X00000008U
207
208#define XQSPIPSU_ISR_TXNOT_FULL_SHIFT 2U
209#define XQSPIPSU_ISR_TXNOT_FULL_WIDTH 1U
210#define XQSPIPSU_ISR_TXNOT_FULL_MASK 0X00000004U
211
212#define XQSPIPSU_ISR_POLL_TIME_EXPIRE_SHIFT 1U
213#define XQSPIPSU_ISR_POLL_TIME_EXPIRE_WIDTH 1U
214#define XQSPIPSU_ISR_POLL_TIME_EXPIRE_MASK 0X00000002U
215
216#define XQSPIPSU_ISR_WR_TO_CLR_MASK 0X00000002U
227#define XQSPIPSU_IER_OFFSET 0X00000008U
228
229#define XQSPIPSU_IER_RXEMPTY_SHIFT 11U
230#define XQSPIPSU_IER_RXEMPTY_WIDTH 1U
231#define XQSPIPSU_IER_RXEMPTY_MASK 0X00000800U
232
233#define XQSPIPSU_IER_GENFIFOFULL_SHIFT 10U
234#define XQSPIPSU_IER_GENFIFOFULL_WIDTH 1U
235#define XQSPIPSU_IER_GENFIFOFULL_MASK 0X00000400U
236
237#define XQSPIPSU_IER_GENFIFONOT_FULL_SHIFT 9U
238#define XQSPIPSU_IER_GENFIFONOT_FULL_WIDTH 1U
239#define XQSPIPSU_IER_GENFIFONOT_FULL_MASK 0X00000200U
240
241#define XQSPIPSU_IER_TXEMPTY_SHIFT 8U
242#define XQSPIPSU_IER_TXEMPTY_WIDTH 1U
243#define XQSPIPSU_IER_TXEMPTY_MASK 0X00000100U
244
245#define XQSPIPSU_IER_GENFIFOEMPTY_SHIFT 7U
246#define XQSPIPSU_IER_GENFIFOEMPTY_WIDTH 1U
247#define XQSPIPSU_IER_GENFIFOEMPTY_MASK 0X00000080U
248
249#define XQSPIPSU_IER_RXFULL_SHIFT 5U
250#define XQSPIPSU_IER_RXFULL_WIDTH 1U
251#define XQSPIPSU_IER_RXFULL_MASK 0X00000020U
252
253#define XQSPIPSU_IER_RXNEMPTY_SHIFT 4U
254#define XQSPIPSU_IER_RXNEMPTY_WIDTH 1U
255#define XQSPIPSU_IER_RXNEMPTY_MASK 0X00000010U
256
257#define XQSPIPSU_IER_TXFULL_SHIFT 3U
258#define XQSPIPSU_IER_TXFULL_WIDTH 1U
259#define XQSPIPSU_IER_TXFULL_MASK 0X00000008U
260
261#define XQSPIPSU_IER_TXNOT_FULL_SHIFT 2U
262#define XQSPIPSU_IER_TXNOT_FULL_WIDTH 1U
263#define XQSPIPSU_IER_TXNOT_FULL_MASK 0X00000004U
264
265#define XQSPIPSU_IER_POLL_TIME_EXPIRE_SHIFT 1U
266#define XQSPIPSU_IER_POLL_TIME_EXPIRE_WIDTH 1U
267#define XQSPIPSU_IER_POLL_TIME_EXPIRE_MASK 0X00000002U
278#define XQSPIPSU_IDR_OFFSET 0X0000000CU
279
280#define XQSPIPSU_IDR_RXEMPTY_SHIFT 11U
281#define XQSPIPSU_IDR_RXEMPTY_WIDTH 1U
282#define XQSPIPSU_IDR_RXEMPTY_MASK 0X00000800U
283
284#define XQSPIPSU_IDR_GENFIFOFULL_SHIFT 10U
285#define XQSPIPSU_IDR_GENFIFOFULL_WIDTH 1U
286#define XQSPIPSU_IDR_GENFIFOFULL_MASK 0X00000400U
287
288#define XQSPIPSU_IDR_GENFIFONOT_FULL_SHIFT 9U
289#define XQSPIPSU_IDR_GENFIFONOT_FULL_WIDTH 1U
290#define XQSPIPSU_IDR_GENFIFONOT_FULL_MASK 0X00000200U
291
292#define XQSPIPSU_IDR_TXEMPTY_SHIFT 8U
293#define XQSPIPSU_IDR_TXEMPTY_WIDTH 1U
294#define XQSPIPSU_IDR_TXEMPTY_MASK 0X00000100U
295
296#define XQSPIPSU_IDR_GENFIFOEMPTY_SHIFT 7U
297#define XQSPIPSU_IDR_GENFIFOEMPTY_WIDTH 1U
298#define XQSPIPSU_IDR_GENFIFOEMPTY_MASK 0X00000080U
299
300#define XQSPIPSU_IDR_RXFULL_SHIFT 5U
301#define XQSPIPSU_IDR_RXFULL_WIDTH 1U
302#define XQSPIPSU_IDR_RXFULL_MASK 0X00000020U
303
304#define XQSPIPSU_IDR_RXNEMPTY_SHIFT 4U
305#define XQSPIPSU_IDR_RXNEMPTY_WIDTH 1U
306#define XQSPIPSU_IDR_RXNEMPTY_MASK 0X00000010U
307
308#define XQSPIPSU_IDR_TXFULL_SHIFT 3U
309#define XQSPIPSU_IDR_TXFULL_WIDTH 1U
310#define XQSPIPSU_IDR_TXFULL_MASK 0X00000008U
311
312#define XQSPIPSU_IDR_TXNOT_FULL_SHIFT 2U
313#define XQSPIPSU_IDR_TXNOT_FULL_WIDTH 1U
314#define XQSPIPSU_IDR_TXNOT_FULL_MASK 0X00000004U
315
316#define XQSPIPSU_IDR_POLL_TIME_EXPIRE_SHIFT 1U
317#define XQSPIPSU_IDR_POLL_TIME_EXPIRE_WIDTH 1U
318#define XQSPIPSU_IDR_POLL_TIME_EXPIRE_MASK 0X00000002U
319
320#define XQSPIPSU_IDR_ALL_MASK 0X0FBEU
331#define XQSPIPSU_IMR_OFFSET 0X00000010U
332
333#define XQSPIPSU_IMR_RXEMPTY_SHIFT 11U
334#define XQSPIPSU_IMR_RXEMPTY_WIDTH 1U
335#define XQSPIPSU_IMR_RXEMPTY_MASK 0X00000800U
336
337#define XQSPIPSU_IMR_GENFIFOFULL_SHIFT 10U
338#define XQSPIPSU_IMR_GENFIFOFULL_WIDTH 1U
339#define XQSPIPSU_IMR_GENFIFOFULL_MASK 0X00000400U
340
341#define XQSPIPSU_IMR_GENFIFONOT_FULL_SHIFT 9U
342#define XQSPIPSU_IMR_GENFIFONOT_FULL_WIDTH 1U
343#define XQSPIPSU_IMR_GENFIFONOT_FULL_MASK 0X00000200U
344
345#define XQSPIPSU_IMR_TXEMPTY_SHIFT 8U
346#define XQSPIPSU_IMR_TXEMPTY_WIDTH 1U
347#define XQSPIPSU_IMR_TXEMPTY_MASK 0X00000100U
348
349#define XQSPIPSU_IMR_GENFIFOEMPTY_SHIFT 7U
350#define XQSPIPSU_IMR_GENFIFOEMPTY_WIDTH 1U
351#define XQSPIPSU_IMR_GENFIFOEMPTY_MASK 0X00000080U
352
353#define XQSPIPSU_IMR_RXFULL_SHIFT 5U
354#define XQSPIPSU_IMR_RXFULL_WIDTH 1U
355#define XQSPIPSU_IMR_RXFULL_MASK 0X00000020U
356
357#define XQSPIPSU_IMR_RXNEMPTY_SHIFT 4U
358#define XQSPIPSU_IMR_RXNEMPTY_WIDTH 1U
359#define XQSPIPSU_IMR_RXNEMPTY_MASK 0X00000010U
360
361#define XQSPIPSU_IMR_TXFULL_SHIFT 3U
362#define XQSPIPSU_IMR_TXFULL_WIDTH 1U
363#define XQSPIPSU_IMR_TXFULL_MASK 0X00000008U
364
365#define XQSPIPSU_IMR_TXNOT_FULL_SHIFT 2U
366#define XQSPIPSU_IMR_TXNOT_FULL_WIDTH 1U
367#define XQSPIPSU_IMR_TXNOT_FULL_MASK 0X00000004U
368
369#define XQSPIPSU_IMR_POLL_TIME_EXPIRE_SHIFT 1U
370#define XQSPIPSU_IMR_POLL_TIME_EXPIRE_WIDTH 1U
371#define XQSPIPSU_IMR_POLL_TIME_EXPIRE_MASK 0X00000002U
382#define XQSPIPSU_EN_OFFSET 0X00000014U
383
384#define XQSPIPSU_EN_SHIFT 0U
385#define XQSPIPSU_EN_WIDTH 1U
386#define XQSPIPSU_EN_MASK 0X00000001U
397#define XQSPIPSU_TXD_OFFSET 0X0000001CU
398
399#define XQSPIPSU_TXD_SHIFT 0U
400#define XQSPIPSU_TXD_WIDTH 32U
401#define XQSPIPSU_TXD_MASK 0XFFFFFFFFU
402
403#define XQSPIPSU_TXD_DEPTH 64
414#define XQSPIPSU_RXD_OFFSET 0X00000020U
415
416#define XQSPIPSU_RXD_SHIFT 0U
417#define XQSPIPSU_RXD_WIDTH 32U
418#define XQSPIPSU_RXD_MASK 0XFFFFFFFFU
429#define XQSPIPSU_TX_THRESHOLD_OFFSET 0X00000028U
430
431#define XQSPIPSU_TX_FIFO_THRESHOLD_SHIFT 0U
432#define XQSPIPSU_TX_FIFO_THRESHOLD_WIDTH 6U
433#define XQSPIPSU_TX_FIFO_THRESHOLD_MASK 0X0000003FU
434#define XQSPIPSU_TX_FIFO_THRESHOLD_RESET_VAL 0X01U
435
436#define XQSPIPSU_RX_THRESHOLD_OFFSET 0X0000002CU
437
438#define XQSPIPSU_RX_FIFO_THRESHOLD_SHIFT 0U
439#define XQSPIPSU_RX_FIFO_THRESHOLD_WIDTH 6U
440#define XQSPIPSU_RX_FIFO_THRESHOLD_MASK 0X0000003FU
441#define XQSPIPSU_RX_FIFO_THRESHOLD_RESET_VAL 0X01U
442
443#define XQSPIPSU_RXFIFO_THRESHOLD_OPT 32U
453#define XQSPIPSU_GPIO_OFFSET 0X00000030U
454
455#define XQSPIPSU_GPIO_WP_N_SHIFT 0U
456#define XQSPIPSU_GPIO_WP_N_WIDTH 1U
457#define XQSPIPSU_GPIO_WP_N_MASK 0X00000001U
468#define XQSPIPSU_LPBK_DLY_ADJ_OFFSET 0X00000038U
469
470#define XQSPIPSU_LPBK_DLY_ADJ_USE_LPBK_SHIFT 5U
471#define XQSPIPSU_LPBK_DLY_ADJ_USE_LPBK_WIDTH 1U
472#define XQSPIPSU_LPBK_DLY_ADJ_USE_LPBK_MASK 0X00000020U
473
474#define XQSPIPSU_LPBK_DLY_ADJ_DLY1_SHIFT 3U
475#define XQSPIPSU_LPBK_DLY_ADJ_DLY1_WIDTH 2U
476#define XQSPIPSU_LPBK_DLY_ADJ_DLY1_MASK 0X00000018U
477
478#define XQSPIPSU_LPBK_DLY_ADJ_DLY0_SHIFT 0U
479#define XQSPIPSU_LPBK_DLY_ADJ_DLY0_WIDTH 3U
480#define XQSPIPSU_LPBK_DLY_ADJ_DLY0_MASK 0X00000007U
491#define XQSPIPSU_GEN_FIFO_OFFSET 0X00000040U
492
493#define XQSPIPSU_GEN_FIFO_DATA_SHIFT 0U
494#define XQSPIPSU_GEN_FIFO_DATA_WIDTH 20U
495#define XQSPIPSU_GEN_FIFO_DATA_MASK 0X000FFFFFU
506#define XQSPIPSU_SEL_OFFSET 0X00000044U
507
508#define XQSPIPSU_SEL_SHIFT 0U
509#define XQSPIPSU_SEL_WIDTH 1U
510#if !defined (versal)
511#define XQSPIPSU_SEL_LQSPI_MASK 0X0U
512#endif
513#define XQSPIPSU_SEL_GQSPI_MASK 0X00000001U
524#define XQSPIPSU_FIFO_CTRL_OFFSET 0X0000004CU
525
526#define XQSPIPSU_FIFO_CTRL_RST_RX_FIFO_SHIFT 2U
527#define XQSPIPSU_FIFO_CTRL_RST_RX_FIFO_WIDTH 1U
528#define XQSPIPSU_FIFO_CTRL_RST_RX_FIFO_MASK 0X00000004U
529
530#define XQSPIPSU_FIFO_CTRL_RST_TX_FIFO_SHIFT 1U
531#define XQSPIPSU_FIFO_CTRL_RST_TX_FIFO_WIDTH 1U
532#define XQSPIPSU_FIFO_CTRL_RST_TX_FIFO_MASK 0X00000002U
533
534#define XQSPIPSU_FIFO_CTRL_RST_GEN_FIFO_SHIFT 0U
535#define XQSPIPSU_FIFO_CTRL_RST_GEN_FIFO_WIDTH 1U
536#define XQSPIPSU_FIFO_CTRL_RST_GEN_FIFO_MASK 0X00000001U
547#define XQSPIPSU_GF_THRESHOLD_OFFSET 0X00000050U
548
549#define XQSPIPSU_GEN_FIFO_THRESHOLD_SHIFT 0U
550#define XQSPIPSU_GEN_FIFO_THRESHOLD_WIDTH 5U
551#define XQSPIPSU_GEN_FIFO_THRESHOLD_MASK 0X0000001FU
552#define XQSPIPSU_GEN_FIFO_THRESHOLD_RESET_VAL 0X10U
563#define XQSPIPSU_POLL_CFG_OFFSET 0X00000054U
564
565#define XQSPIPSU_POLL_CFG_EN_MASK_UPPER_SHIFT 31U
566#define XQSPIPSU_POLL_CFG_EN_MASK_UPPER_WIDTH 1U
567#define XQSPIPSU_POLL_CFG_EN_MASK_UPPER_MASK 0X80000000U
568
569#define XQSPIPSU_POLL_CFG_EN_MASK_LOWER_SHIFT 30U
570#define XQSPIPSU_POLL_CFG_EN_MASK_LOWER_WIDTH 1U
571#define XQSPIPSU_POLL_CFG_EN_MASK_LOWER_MASK 0X40000000U
572
573#define XQSPIPSU_POLL_CFG_MASK_EN_SHIFT 8U
574#define XQSPIPSU_POLL_CFG_MASK_EN_WIDTH 8U
575#define XQSPIPSU_POLL_CFG_MASK_EN_MASK 0X0000FF00U
576
577#define XQSPIPSU_POLL_CFG_DATA_VALUE_SHIFT 0U
578#define XQSPIPSU_POLL_CFG_DATA_VALUE_WIDTH 8U
579#define XQSPIPSU_POLL_CFG_DATA_VALUE_MASK 0X000000FFU
580
581#define XQSPIPSU_P_TO_OFFSET 0X00000058U
582
583#define XQSPIPSU_P_TO_VALUE_SHIFT 0U
584#define XQSPIPSU_P_TO_VALUE_WIDTH 32U
585#define XQSPIPSU_P_TO_VALUE_MASK 0XFFFFFFFFU
596#define XQSPIPSU_XFER_STS_OFFSET 0X0000005CU
597
598#define XQSPIPSU_XFER_STS_PEND_BYTES_SHIFT 0U
599#define XQSPIPSU_XFER_STS_PEND_BYTES_WIDTH 32U
600#define XQSPIPSU_XFER_STS_PEND_BYTES_MASK 0XFFFFFFFFU
611#define XQSPIPSU_GF_SNAPSHOT_OFFSET 0X00000060U
612
613#define XQSPIPSU_GF_SNAPSHOT_SHIFT 0U
614#define XQSPIPSU_GF_SNAPSHOT_WIDTH 20U
615#define XQSPIPSU_GF_SNAPSHOT_MASK 0X000FFFFFU
625#define XQSPIPSU_RX_COPY_OFFSET 0X00000064U
626
627#define XQSPIPSU_RX_COPY_UPPER_SHIFT 8U
628#define XQSPIPSU_RX_COPY_UPPER_WIDTH 8U
629#define XQSPIPSU_RX_COPY_UPPER_MASK 0X0000FF00U
630
631#define XQSPIPSU_RX_COPY_LOWER_SHIFT 0U
632#define XQSPIPSU_RX_COPY_LOWER_WIDTH 8U
633#define XQSPIPSU_RX_COPY_LOWER_MASK 0X000000FFU
643#define XQSPIPSU_MOD_ID_OFFSET 0X000000FCU
644
645#define XQSPIPSU_MOD_ID_SHIFT 0U
646#define XQSPIPSU_MOD_ID_WIDTH 32U
647#define XQSPIPSU_MOD_ID_MASK 0XFFFFFFFFU
658#define XQSPIPSU_QSPIDMA_DST_ADDR_OFFSET 0X00000700U
659
660#define XQSPIPSU_QSPIDMA_DST_ADDR_SHIFT 2U
661#define XQSPIPSU_QSPIDMA_DST_ADDR_WIDTH 30U
662#define XQSPIPSU_QSPIDMA_DST_ADDR_MASK 0XFFFFFFFCU
663
664#define XQSPIPSU_QSPIDMA_DST_SIZE_OFFSET 0X00000704U
665
666#define XQSPIPSU_QSPIDMA_DST_SIZE_SHIFT 2U
667#define XQSPIPSU_QSPIDMA_DST_SIZE_WIDTH 27U
668#define XQSPIPSU_QSPIDMA_DST_SIZE_MASK 0X1FFFFFFCU
669
670#define XQSPIPSU_QSPIDMA_DST_STS_OFFSET 0X00000708U
671
672#define XQSPIPSU_QSPIDMA_DST_STS_DONE_CNT_SHIFT 13U
673#define XQSPIPSU_QSPIDMA_DST_STS_DONE_CNT_WIDTH 3U
674#define XQSPIPSU_QSPIDMA_DST_STS_DONE_CNT_MASK 0X0000E000U
675
676#define XQSPIPSU_QSPIDMA_DST_STS_DST_FIFO_LEVEL_SHIFT 5U
677#define XQSPIPSU_QSPIDMA_DST_STS_DST_FIFO_LEVEL_WIDTH 8U
678#define XQSPIPSU_QSPIDMA_DST_STS_DST_FIFO_LEVEL_MASK 0X00001FE0U
679
680#define XQSPIPSU_QSPIDMA_DST_STS_WR_OUTSTANDING_SHIFT 1U
681#define XQSPIPSU_QSPIDMA_DST_STS_WR_OUTSTANDING_WIDTH 4U
682#define XQSPIPSU_QSPIDMA_DST_STS_WR_OUTSTANDING_MASK 0X0000001EU
683
684#define XQSPIPSU_QSPIDMA_DST_STS_BUSY_SHIFT 0U
685#define XQSPIPSU_QSPIDMA_DST_STS_BUSY_WIDTH 1U
686#define XQSPIPSU_QSPIDMA_DST_STS_BUSY_MASK 0X00000001U
687
688#define XQSPIPSU_QSPIDMA_DST_STS_WTC 0xE000U
689
690#define XQSPIPSU_QSPIDMA_DST_CTRL_OFFSET 0X0000070CU
691
692#define XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_LVL_HIT_THRESHOLD_SHIFT 25U
693#define XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_LVL_HIT_THRESHOLD_WIDTH 7U
694#define XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_LVL_HIT_THRESHOLD_MASK 0XFE000000U
695
696#define XQSPIPSU_QSPIDMA_DST_CTRL_APB_ERR_RESP_SHIFT 24U
697#define XQSPIPSU_QSPIDMA_DST_CTRL_APB_ERR_RESP_WIDTH 1U
698#define XQSPIPSU_QSPIDMA_DST_CTRL_APB_ERR_RESP_MASK 0X01000000U
699
700#define XQSPIPSU_QSPIDMA_DST_CTRL_ENDIAN_SHIFT 23U
701#define XQSPIPSU_QSPIDMA_DST_CTRL_ENDIAN_WIDTH 1U
702#define XQSPIPSU_QSPIDMA_DST_CTRL_ENDIAN_MASK 0X00800000U
703
704#define XQSPIPSU_QSPIDMA_DST_CTRL_AXI_BRST_TYPE_SHIFT 22U
705#define XQSPIPSU_QSPIDMA_DST_CTRL_AXI_BRST_TYPE_WIDTH 1U
706#define XQSPIPSU_QSPIDMA_DST_CTRL_AXI_BRST_TYPE_MASK 0X00400000U
707
708#define XQSPIPSU_QSPIDMA_DST_CTRL_TO_VAL_SHIFT 10U
709#define XQSPIPSU_QSPIDMA_DST_CTRL_TO_VAL_WIDTH 12U
710#define XQSPIPSU_QSPIDMA_DST_CTRL_TO_VAL_MASK 0X003FFC00U
711
712#define XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_THRESHOLD_SHIFT 2U
713#define XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_THRESHOLD_WIDTH 8U
714#define XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_THRESHOLD_MASK 0X000003FCU
715
716#define XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_STRM_SHIFT 1U
717#define XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_STRM_WIDTH 1U
718#define XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_STRM_MASK 0X00000002U
719
720#define XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_MEM_SHIFT 0U
721#define XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_MEM_WIDTH 1U
722#define XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_MEM_MASK 0X00000001U
723
724#define XQSPIPSU_QSPIDMA_DST_CTRL_RESET_VAL 0x403FFA00U
725
726#define XQSPIPSU_QSPIDMA_DST_I_STS_OFFSET 0X00000714U
727
728#define XQSPIPSU_QSPIDMA_DST_I_STS_FIFO_OF_SHIFT 7U
729#define XQSPIPSU_QSPIDMA_DST_I_STS_FIFO_OF_WIDTH 1U
730#define XQSPIPSU_QSPIDMA_DST_I_STS_FIFO_OF_MASK 0X00000080U
731
732#define XQSPIPSU_QSPIDMA_DST_I_STS_INVALID_APB_SHIFT 6U
733#define XQSPIPSU_QSPIDMA_DST_I_STS_INVALID_APB_WIDTH 1U
734#define XQSPIPSU_QSPIDMA_DST_I_STS_INVALID_APB_MASK 0X00000040U
735
736#define XQSPIPSU_QSPIDMA_DST_I_STS_THRESHOLD_HIT_SHIFT 5U
737#define XQSPIPSU_QSPIDMA_DST_I_STS_THRESHOLD_HIT_WIDTH 1U
738#define XQSPIPSU_QSPIDMA_DST_I_STS_THRESHOLD_HIT_MASK 0X00000020U
739
740#define XQSPIPSU_QSPIDMA_DST_I_STS_TO_MEM_SHIFT 4U
741#define XQSPIPSU_QSPIDMA_DST_I_STS_TO_MEM_WIDTH 1U
742#define XQSPIPSU_QSPIDMA_DST_I_STS_TO_MEM_MASK 0X00000010U
743
744#define XQSPIPSU_QSPIDMA_DST_I_STS_TO_STRM_SHIFT 3U
745#define XQSPIPSU_QSPIDMA_DST_I_STS_TO_STRM_WIDTH 1U
746#define XQSPIPSU_QSPIDMA_DST_I_STS_TO_STRM_MASK 0X00000008U
747
748#define XQSPIPSU_QSPIDMA_DST_I_STS_AXI_BRESP_ERR_SHIFT 2U
749#define XQSPIPSU_QSPIDMA_DST_I_STS_AXI_BRESP_ERR_WIDTH 1U
750#define XQSPIPSU_QSPIDMA_DST_I_STS_AXI_BRESP_ERR_MASK 0X00000004U
751
752#define XQSPIPSU_QSPIDMA_DST_I_STS_DONE_SHIFT 1U
753#define XQSPIPSU_QSPIDMA_DST_I_STS_DONE_WIDTH 1U
754#define XQSPIPSU_QSPIDMA_DST_I_STS_DONE_MASK 0X00000002U
755
756#define XQSPIPSU_QSPIDMA_DST_INTR_ERR_MASK 0X000000FCU
757#define XQSPIPSU_QSPIDMA_DST_INTR_ALL_MASK 0X000000FEU
758
759#define XQSPIPSU_QSPIDMA_DST_I_EN_OFFSET 0X00000718U
760
761#define XQSPIPSU_QSPIDMA_DST_I_EN_FIFO_OF_SHIFT 7U
762#define XQSPIPSU_QSPIDMA_DST_I_EN_FIFO_OF_WIDTH 1U
763#define XQSPIPSU_QSPIDMA_DST_I_EN_FIFO_OF_MASK 0X00000080U
764
765#define XQSPIPSU_QSPIDMA_DST_I_EN_INVALID_APB_SHIFT 6U
766#define XQSPIPSU_QSPIDMA_DST_I_EN_INVALID_APB_WIDTH 1U
767#define XQSPIPSU_QSPIDMA_DST_I_EN_INVALID_APB_MASK 0X00000040U
768
769#define XQSPIPSU_QSPIDMA_DST_I_EN_THRESHOLD_HIT_SHIFT 5U
770#define XQSPIPSU_QSPIDMA_DST_I_EN_THRESHOLD_HIT_WIDTH 1U
771#define XQSPIPSU_QSPIDMA_DST_I_EN_THRESHOLD_HIT_MASK 0X00000020U
772
773#define XQSPIPSU_QSPIDMA_DST_I_EN_TO_MEM_SHIFT 4U
774#define XQSPIPSU_QSPIDMA_DST_I_EN_TO_MEM_WIDTH 1U
775#define XQSPIPSU_QSPIDMA_DST_I_EN_TO_MEM_MASK 0X00000010U
776
777#define XQSPIPSU_QSPIDMA_DST_I_EN_TO_STRM_SHIFT 3U
778#define XQSPIPSU_QSPIDMA_DST_I_EN_TO_STRM_WIDTH 1U
779#define XQSPIPSU_QSPIDMA_DST_I_EN_TO_STRM_MASK 0X00000008U
780
781#define XQSPIPSU_QSPIDMA_DST_I_EN_AXI_BRESP_ERR_SHIFT 2U
782#define XQSPIPSU_QSPIDMA_DST_I_EN_AXI_BRESP_ERR_WIDTH 1U
783#define XQSPIPSU_QSPIDMA_DST_I_EN_AXI_BRESP_ERR_MASK 0X00000004U
784
785#define XQSPIPSU_QSPIDMA_DST_I_EN_DONE_SHIFT 1U
786#define XQSPIPSU_QSPIDMA_DST_I_EN_DONE_WIDTH 1U
787#define XQSPIPSU_QSPIDMA_DST_I_EN_DONE_MASK 0X00000002U
788
789#define XQSPIPSU_QSPIDMA_DST_I_DIS_OFFSET 0X0000071CU
790
791#define XQSPIPSU_QSPIDMA_DST_I_DIS_FIFO_OF_SHIFT 7U
792#define XQSPIPSU_QSPIDMA_DST_I_DIS_FIFO_OF_WIDTH 1U
793#define XQSPIPSU_QSPIDMA_DST_I_DIS_FIFO_OF_MASK 0X00000080U
794
795#define XQSPIPSU_QSPIDMA_DST_I_DIS_INVALID_APB_SHIFT 6U
796#define XQSPIPSU_QSPIDMA_DST_I_DIS_INVALID_APB_WIDTH 1U
797#define XQSPIPSU_QSPIDMA_DST_I_DIS_INVALID_APB_MASK 0X00000040U
798
799#define XQSPIPSU_QSPIDMA_DST_I_DIS_THRESHOLD_HIT_SHIFT 5U
800#define XQSPIPSU_QSPIDMA_DST_I_DIS_THRESHOLD_HIT_WIDTH 1U
801#define XQSPIPSU_QSPIDMA_DST_I_DIS_THRESHOLD_HIT_MASK 0X00000020U
802
803#define XQSPIPSU_QSPIDMA_DST_I_DIS_TO_MEM_SHIFT 4U
804#define XQSPIPSU_QSPIDMA_DST_I_DIS_TO_MEM_WIDTH 1U
805#define XQSPIPSU_QSPIDMA_DST_I_DIS_TO_MEM_MASK 0X00000010U
806
807#define XQSPIPSU_QSPIDMA_DST_I_DIS_TO_STRM_SHIFT 3U
808#define XQSPIPSU_QSPIDMA_DST_I_DIS_TO_STRM_WIDTH 1U
809#define XQSPIPSU_QSPIDMA_DST_I_DIS_TO_STRM_MASK 0X00000008U
810
811#define XQSPIPSU_QSPIDMA_DST_I_DIS_AXI_BRESP_ERR_SHIFT 2U
812#define XQSPIPSU_QSPIDMA_DST_I_DIS_AXI_BRESP_ERR_WIDTH 1U
813#define XQSPIPSU_QSPIDMA_DST_I_DIS_AXI_BRESP_ERR_MASK 0X00000004U
814
815#define XQSPIPSU_QSPIDMA_DST_I_DIS_DONE_SHIFT 1U
816#define XQSPIPSU_QSPIDMA_DST_I_DIS_DONE_WIDTH 1U
817#define XQSPIPSU_QSPIDMA_DST_I_DIS_DONE_MASK 0X00000002U
818
819#define XQSPIPSU_QSPIDMA_DST_IMR_OFFSET 0X00000720U
820
821#define XQSPIPSU_QSPIDMA_DST_IMR_FIFO_OF_SHIFT 7U
822#define XQSPIPSU_QSPIDMA_DST_IMR_FIFO_OF_WIDTH 1U
823#define XQSPIPSU_QSPIDMA_DST_IMR_FIFO_OF_MASK 0X00000080U
824
825#define XQSPIPSU_QSPIDMA_DST_IMR_INVALID_APB_SHIFT 6U
826#define XQSPIPSU_QSPIDMA_DST_IMR_INVALID_APB_WIDTH 1U
827#define XQSPIPSU_QSPIDMA_DST_IMR_INVALID_APB_MASK 0X00000040U
828
829#define XQSPIPSU_QSPIDMA_DST_IMR_THRESHOLD_HIT_SHIFT 5U
830#define XQSPIPSU_QSPIDMA_DST_IMR_THRESHOLD_HIT_WIDTH 1U
831#define XQSPIPSU_QSPIDMA_DST_IMR_THRESHOLD_HIT_MASK 0X00000020U
832
833#define XQSPIPSU_QSPIDMA_DST_IMR_TO_MEM_SHIFT 4U
834#define XQSPIPSU_QSPIDMA_DST_IMR_TO_MEM_WIDTH 1U
835#define XQSPIPSU_QSPIDMA_DST_IMR_TO_MEM_MASK 0X00000010U
836
837#define XQSPIPSU_QSPIDMA_DST_IMR_TO_STRM_SHIFT 3U
838#define XQSPIPSU_QSPIDMA_DST_IMR_TO_STRM_WIDTH 1U
839#define XQSPIPSU_QSPIDMA_DST_IMR_TO_STRM_MASK 0X00000008U
840
841#define XQSPIPSU_QSPIDMA_DST_IMR_AXI_BRESP_ERR_SHIFT 2U
842#define XQSPIPSU_QSPIDMA_DST_IMR_AXI_BRESP_ERR_WIDTH 1U
843#define XQSPIPSU_QSPIDMA_DST_IMR_AXI_BRESP_ERR_MASK 0X00000004U
844
845#define XQSPIPSU_QSPIDMA_DST_IMR_DONE_SHIFT 1U
846#define XQSPIPSU_QSPIDMA_DST_IMR_DONE_WIDTH 1U
847#define XQSPIPSU_QSPIDMA_DST_IMR_DONE_MASK 0X00000002U
848
849#define XQSPIPSU_QSPIDMA_DST_CTRL2_OFFSET 0X00000724U
850
851#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMASA_SHIFT 27U
852#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMASA_WIDTH 1U
853#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMASA_MASK 0X08000000U
854
855#define XQSPIPSU_QSPIDMA_DST_CTRL2_AWCACHE_SHIFT 24U
856#define XQSPIPSU_QSPIDMA_DST_CTRL2_AWCACHE_WIDTH 3U
857#define XQSPIPSU_QSPIDMA_DST_CTRL2_AWCACHE_MASK 0X07000000U
858
859#define XQSPIPSU_QSPIDMA_DST_CTRL2_TO_EN_SHIFT 22U
860#define XQSPIPSU_QSPIDMA_DST_CTRL2_TO_EN_WIDTH 1U
861#define XQSPIPSU_QSPIDMA_DST_CTRL2_TO_EN_MASK 0X00400000U
862
863#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAB_SHIFT 19U
864#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAB_WIDTH 3U
865#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAB_MASK 0X00380000U
866
867#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAA_SHIFT 16U
868#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAA_WIDTH 3U
869#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAA_MASK 0X00070000U
870
871#define XQSPIPSU_QSPIDMA_DST_CTRL2_TO_PRE_SHIFT 4U
872#define XQSPIPSU_QSPIDMA_DST_CTRL2_TO_PRE_WIDTH 12U
873#define XQSPIPSU_QSPIDMA_DST_CTRL2_TO_PRE_MASK 0X0000FFF0U
874
875#define XQSPIPSU_QSPIDMA_DST_CTRL2_MAX_OUTS_CMDS_SHIFT 0U
876#define XQSPIPSU_QSPIDMA_DST_CTRL2_MAX_OUTS_CMDS_WIDTH 4U
877#define XQSPIPSU_QSPIDMA_DST_CTRL2_MAX_OUTS_CMDS_MASK 0X0000000FU
878
879#define XQSPIPSU_QSPIDMA_DST_ADDR_MSB_OFFSET 0X00000728U
880
881#define XQSPIPSU_QSPIDMA_DST_ADDR_MSB_SHIFT 0U
882#define XQSPIPSU_QSPIDMA_DST_ADDR_MSB_WIDTH 12U
883#define XQSPIPSU_QSPIDMA_DST_ADDR_MSB_MASK 0X00000FFFU
884
885#define XQSPIPSU_QSPIDMA_FUTURE_ECO_OFFSET 0X00000EFCU
886
887#define XQSPIPSU_QSPIDMA_FUTURE_ECO_VAL_SHIFT 0U
888#define XQSPIPSU_QSPIDMA_FUTURE_ECO_VAL_WIDTH 32U
889#define XQSPIPSU_QSPIDMA_FUTURE_ECO_VAL_MASK 0XFFFFFFFFU
900#define XQSPIPSU_GENFIFO_IMM_DATA_MASK 0xFFU
901#define XQSPIPSU_GENFIFO_DATA_XFER 0x100U
902#define XQSPIPSU_GENFIFO_EXP 0x200U
903#define XQSPIPSU_GENFIFO_MODE_SPI 0x400U
904#define XQSPIPSU_GENFIFO_MODE_DUALSPI 0x800U
905#define XQSPIPSU_GENFIFO_MODE_QUADSPI 0xC00U
906#define XQSPIPSU_GENFIFO_MODE_MASK 0xC00U /* And with ~MASK first */
907#define XQSPIPSU_GENFIFO_CS_LOWER 0x1000U
908#define XQSPIPSU_GENFIFO_CS_UPPER 0x2000U
909#define XQSPIPSU_GENFIFO_BUS_LOWER 0x4000U
910#define XQSPIPSU_GENFIFO_BUS_UPPER 0x8000U
911#define XQSPIPSU_GENFIFO_BUS_BOTH 0xC000U /* inverse is no bus */
912#define XQSPIPSU_GENFIFO_BUS_MASK 0xC000U /* And with ~MASK first */
913#define XQSPIPSU_GENFIFO_TX 0x10000U /* inverse is zero pump */
914#define XQSPIPSU_GENFIFO_RX 0x20000U /* inverse is RX discard */
915#define XQSPIPSU_GENFIFO_STRIPE 0x40000U
916#define XQSPIPSU_GENFIFO_POLL 0x80000U
926#define XQSPIPSU_DATA_DLY_ADJ_OFFSET 0X000000F8U
927
928#define XQSPIPSU_DATA_DLY_ADJ_USE_DATA_DLY_SHIFT 31U
929#define XQSPIPSU_DATA_DLY_ADJ_USE_DATA_DLY_WIDTH 1U
930#define XQSPIPSU_DATA_DLY_ADJ_USE_DATA_DLY_MASK 0X80000000U
931
932#define XQSPIPSU_DATA_DLY_ADJ_DLY_SHIFT 28U
933#define XQSPIPSU_DATA_DLY_ADJ_DLY_WIDTH 3U
934#define XQSPIPSU_DATA_DLY_ADJ_DLY_MASK 0X70000000U
945#if defined versal
946#define IOU_TAPDLY_BYPASS_OFFSET 0X0000003CU
947#else
948#define IOU_TAPDLY_BYPASS_OFFSET 0X00000390U
949#endif
950
951#define IOU_TAPDLY_BYPASS_LQSPI_RX_SHIFT 0X02U
952#if !defined (versal)
953#define IOU_TAPDLY_BYPASS_LQSPI_RX_WIDTH 0X01U
954#define IOU_TAPDLY_BYPASS_LQSPI_RX_MASK 0x00000004U
955#endif
956
957#if defined versal
958#define IOU_TAPDLY_RESET_STATE 0x4U
959#else
960#define IOU_TAPDLY_RESET_STATE 0x7U
961#endif
964/***************** Macros (Inline Functions) Definitions *********************/
965
966#define XQspiPsu_In32 Xil_In32
967#define XQspiPsu_Out32 Xil_Out32
969/****************************************************************************/
983#define XQspiPsu_ReadReg(BaseAddress, RegOffset) XQspiPsu_In32((BaseAddress) + (RegOffset))
984
985/***************************************************************************/
1001#define XQspiPsu_WriteReg(BaseAddress, RegOffset, RegisterValue) XQspiPsu_Out32((BaseAddress) + (RegOffset), (RegisterValue))
1002
1003
1004#ifdef __cplusplus
1005}
1006#endif
1007
1008
1009#endif