34#ifndef LIBCPU_POWERPC_TSEC_H
35#define LIBCPU_POWERPC_TSEC_H
40#include <bsp/tsec-config.h>
104 uint8_t reserved0x2_4000[0x24010-0x24000];
108 uint8_t reserved0x2_401c[0x24020-0x2401c];
114 uint8_t reserved0x2_4034[0x2408c-0x24034];
116 uint32_t fifo_tx_thr;
117 uint8_t reserved0x2_4090[0x24094-0x24090];
119 uint32_t fifo_tx_starve;
120 uint32_t fifo_tx_starve_shutoff;
121 uint8_t reserved0x2_40A0[0x24100-0x240A0];
125 uint8_t reserved0x2_4108[0x24110-0x24108];
127 uint8_t reserved0x2_4114[0x24124-0x24114];
129 uint8_t reserved0x2_4128[0x24184-0x24128];
131 uint8_t reserved0x2_4188[0x24204-0x24188];
133 uint8_t reserved0x2_4208[0x242B0-0x24208];
136 uint8_t reserved0x2_42B8[0x24300-0x242B8];
140 uint8_t reserved0x2_4308[0x2430C-0x24308];
143 uint8_t reserved0x2_4314[0x24324-0x24314];
145 uint8_t reserved0x2_4328[0x24340-0x24328];
147 uint8_t reserved0x2_4344[0x24384-0x24344];
149 uint8_t reserved0x2_4388[0x24404-0x24388];
151 uint8_t reserved0x2_4408[0x24500-0x24408];
158 uint8_t reserved0x2_4514[0x24520-0x24514];
165 uint8_t reserved0x2_4538[0x2453c-0x24538];
167 uint32_t macstnaddr[2];
168 uint8_t reserved0x2_4548[0x24680-0x24548];
171 uint32_t rmon_mib[TSEC_RMON_CNT];
176 uint8_t reserved0x2_4740[0x24800-0x24740];
180 uint8_t reserved0x2_4820[0x24880-0x24820];
182 uint8_t reserved0x2_48A0[0x24B00-0x248A0];
185 uint8_t reserved0x2_4B00[0x24BF8-0x24B00];
188 uint8_t reserved0x2_4C00[0x25000-0x24C00];
194#define TSEC_IEVENT_BABR (1<<(31- 0))
195#define TSEC_IEVENT_RXC (1<<(31- 1))
196#define TSEC_IEVENT_BSY (1<<(31- 2))
197#define TSEC_IEVENT_EBERR (1<<(31- 3))
198#define TSEC_IEVENT_MSRO (1<<(31- 5))
199#define TSEC_IEVENT_GTSC (1<<(31- 6))
200#define TSEC_IEVENT_BABT (1<<(31- 7))
201#define TSEC_IEVENT_TXC (1<<(31- 8))
202#define TSEC_IEVENT_TXE (1<<(31- 9))
203#define TSEC_IEVENT_TXB (1<<(31-10))
204#define TSEC_IEVENT_TXF (1<<(31-11))
205#define TSEC_IEVENT_LC (1<<(31-13))
206#define TSEC_IEVENT_CRL_XDA (1<<(31-14))
207#define TSEC_IEVENT_XFUN (1<<(31-15))
208#define TSEC_IEVENT_RXB (1<<(31-16))
209#define TSEC_IEVENT_MMRD (1<<(31-21))
210#define TSEC_IEVENT_MMWR (1<<(31-22))
211#define TSEC_IEVENT_GRSC (1<<(31-23))
212#define TSEC_IEVENT_RXF (1<<(31-24))
217#define TSEC_DMACTL_TDSEN (1<<(31-24))
218#define TSEC_DMACTL_TBDSEN (1<<(31-25))
219#define TSEC_DMACTL_GRS (1<<(31-27))
220#define TSEC_DMACTL_GTS (1<<(31-28))
221#define TSEC_DMACTL_WWR (1<<(31-30))
222#define TSEC_DMACTL_WOP (1<<(31-31))
227#define TSEC_TSTAT_THLT (1<<(31-0))
232#define TSEC_RSTAT_QHLT (1<<(31-8))
236#define TSEC_ECNTRL_CLRCNT (1 << (31-17))
237#define TSEC_ECNTRL_AUTOZ (1 << (31-18))
238#define TSEC_ECNTRL_STEN (1 << (31-19))
239#define TSEC_ECNTRL_TBIM (1 << (31-26))
240#define TSEC_ECNTRL_RPM (1 << (31-27))
241#define TSEC_ECNTRL_R100M (1 << (31-28))
245#define TSEC_EDIS_BSYDIS (1 << (31- 2))
246#define TSEC_EDIS_EBERRDIS (1 << (31- 3))
247#define TSEC_EDIS_TXEDIS (1 << (31- 9))
248#define TSEC_EDIS_LCDIS (1 << (31-13))
249#define TSEC_EDIS_CRLXDADIS (1 << (31-14))
250#define TSEC_EDIS_FUNDIS (1 << (31-15))
255#define TSEC_RCTRL_BC_REJ (1 << (31-27))
256#define TSEC_RCTRL_PROM (1 << (31-28))
257#define TSEC_RCTRL_RSF (1 << (31-29))
262#define TSEC_TXIC_ICEN (1 << (31- 0))
263#define TSEC_TXIC_ICFCT(n) (((n)&0xff) << (31-10))
264#define TSEC_TXIC_ICTT(n) (((n)&0xffff) << (31-31))
269#define TSEC_RXIC_ICEN (1 << (31- 0))
270#define TSEC_RXIC_ICFCT(n) (((n)&0xff) << (31-10))
271#define TSEC_RXIC_ICTT(n) (((n)&0xffff) << (31-31))
276#define TSEC_MACCFG1_SOFTRST (1 << (31- 0))
277#define TSEC_MACCFG1_RES_RXMC (1 << (31-12))
278#define TSEC_MACCFG1_RES_TXMC (1 << (31-13))
279#define TSEC_MACCFG1_RES_RXFUN (1 << (31-14))
280#define TSEC_MACCFG1_RES_TXFUN (1 << (31-15))
281#define TSEC_MACCFG1_LOOPBACK (1 << (31-23))
282#define TSEC_MACCFG1_RX_FLOW (1 << (31-26))
283#define TSEC_MACCFG1_TX_FLOW (1 << (31-27))
284#define TSEC_MACCFG1_SYNVRXEN (1 << (31-28))
285#define TSEC_MACCFG1_RXEN (1 << (31-29))
286#define TSEC_MACCFG1_SYNVTXEN (1 << (31-30))
287#define TSEC_MACCFG1_TXEN (1 << (31-31))
292#define TSEC_MACCFG2_PRELEN(n) (((n)&0x0f) << (31-19))
294#define TSEC_MACCFG2_IFMODE_MSK (3 << (31-23))
295#define TSEC_MACCFG2_IFMODE_NIB (1 << (31-23))
296#define TSEC_MACCFG2_IFMODE_BYT (2 << (31-23))
298#define TSEC_MACCFG2_HUGE_FRAME (1 << (31-26))
299#define TSEC_MACCFG2_LENGTH_CHK (1 << (31-27))
300#define TSEC_MACCFG2_PAD_CRC (1 << (31-29))
301#define TSEC_MACCFG2_CRC_EN (1 << (31-30))
302#define TSEC_MACCFG2_FULLDUPLEX (1 << (31-31))
307#define TSEC_MIIMADD_PHY(n) (((n) & 0x3f)<<(31- 23))
308#define TSEC_MIIMADD_REGADDR(n) (((n) & 0x3f)<<(31- 31))
313#define TSEC_MIIMCOM_SCAN (1 << (31-30))
314#define TSEC_MIIMCOM_READ (1 << (31-31))
319#define TSEC_MIIMIND_NVAL (1 << (31-29))
320#define TSEC_MIIMIND_SCAN (1 << (31-30))
321#define TSEC_MIIMIND_BUSY (1 << (31-31))
326#define TSEC_ATTR_RDSEN (1 << (31-24))
327#define TSEC_ATTR_RBDSEN (1 << (31-25))
330 volatile uint16_t status;
331 volatile uint16_t length;
332 volatile void *buffer;
338#define BD_EMPTY (1<<15)
339#define BD_RO1 (1<<14)
340#define BD_WRAP (1<<13)
341#define BD_INTERRUPT (1<<12)
342#define BD_LAST (1<<11)
343#define BD_CONTROL_CHAR (1<<11)
344#define BD_FIRST_IN_FRAME (1<<10)
345#define BD_MISS (1<<8)
346#define BD_BROADCAST (1<<7)
347#define BD_MULTICAST (1<<6)
348#define BD_LONG (1<<5)
349#define BD_NONALIGNED (1<<4)
350#define BD_SHORT (1<<3)
351#define BD_CRC_ERROR (1<<2)
352#define BD_OVERRUN (1<<1)
353#define BD_COLLISION (1<<0)
359#define BD_READY (1<<15)
360#define BD_PAD_CRC (1<<14)
362#define BD_TX_CRC (1<<10)
363#define BD_DEFER (1<<9)
365#define BD_HFE_ (1<<7)
366#define BD_LATE_COLLISION (1<<7)
367#define BD_RETRY_LIMIT (1<<6)
368#define BD_RETRY_COUNT(x) (((x)&0x3C)>>2)
369#define BD_UNDERRUN (1<<1)
370#define BD_TXTRUNC (1<<0)
372struct rtems_bsdnet_ifconfig;
385int tsec_driver_attach_detach(
386 struct rtems_bsdnet_ifconfig *
config,
ISR_Vector_number rtems_vector_number
This integer type represents interrupt vector numbers.
Definition: intr.h:102
Definition: deflate.c:114