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uint32_t | memory_address_base |
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uint32_t | cs0_start_address |
|
uint32_t | cs0_stop_address |
|
uint32_t | cs1_start_address |
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uint32_t | cs1_stop_address |
|
uint32_t | cs2_start_address |
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uint32_t | cs2_stop_address |
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uint32_t | cs3_start_address |
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uint32_t | cs3_stop_address |
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uint32_t | cs4_start_address |
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uint32_t | cs4_stop_address |
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uint32_t | cs5_start_address |
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uint32_t | cs5_stop_address |
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uint32_t | sdram_chip_select_0 |
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uint32_t | sdram_chip_select_1 |
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uint8_t | reserved_0 [16] |
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uint32_t | boot_start_address |
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uint32_t | boot_stop_address |
|
uint16_t | ipbi_control |
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uint16_t | wait_state_enable |
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uint32_t | cs6_start_address |
|
uint32_t | cs6_stop_address |
|
uint32_t | cs7_start_address |
|
uint32_t | cs7_stop_address |
|
uint8_t | reserved_1 [152] |
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The documentation for this struct was generated from the following file: