RTEMS 6.1-rc5
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stm32h7xx_ll_fmc.h
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1
19/* Define to prevent recursive inclusion -------------------------------------*/
20#ifndef STM32H7xx_LL_FMC_H
21#define STM32H7xx_LL_FMC_H
22
23#ifdef __cplusplus
24extern "C" {
25#endif
26
27/* Includes ------------------------------------------------------------------*/
28#include "stm32h7xx_hal_def.h"
29
42#define IS_FMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FMC_NORSRAM_BANK1) || \
43 ((__BANK__) == FMC_NORSRAM_BANK2) || \
44 ((__BANK__) == FMC_NORSRAM_BANK3) || \
45 ((__BANK__) == FMC_NORSRAM_BANK4))
46#define IS_FMC_MUX(__MUX__) (((__MUX__) == FMC_DATA_ADDRESS_MUX_DISABLE) || \
47 ((__MUX__) == FMC_DATA_ADDRESS_MUX_ENABLE))
48#define IS_FMC_MEMORY(__MEMORY__) (((__MEMORY__) == FMC_MEMORY_TYPE_SRAM) || \
49 ((__MEMORY__) == FMC_MEMORY_TYPE_PSRAM)|| \
50 ((__MEMORY__) == FMC_MEMORY_TYPE_NOR))
51#define IS_FMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_8) || \
52 ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_16) || \
53 ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_32))
54#define IS_FMC_PAGESIZE(__SIZE__) (((__SIZE__) == FMC_PAGE_SIZE_NONE) || \
55 ((__SIZE__) == FMC_PAGE_SIZE_128) || \
56 ((__SIZE__) == FMC_PAGE_SIZE_256) || \
57 ((__SIZE__) == FMC_PAGE_SIZE_512) || \
58 ((__SIZE__) == FMC_PAGE_SIZE_1024))
59#define IS_FMC_WRITE_FIFO(__FIFO__) (((__FIFO__) == FMC_WRITE_FIFO_DISABLE) || \
60 ((__FIFO__) == FMC_WRITE_FIFO_ENABLE))
61#define IS_FMC_ACCESS_MODE(__MODE__) (((__MODE__) == FMC_ACCESS_MODE_A) || \
62 ((__MODE__) == FMC_ACCESS_MODE_B) || \
63 ((__MODE__) == FMC_ACCESS_MODE_C) || \
64 ((__MODE__) == FMC_ACCESS_MODE_D))
65#define IS_FMC_BURSTMODE(__STATE__) (((__STATE__) == FMC_BURST_ACCESS_MODE_DISABLE) || \
66 ((__STATE__) == FMC_BURST_ACCESS_MODE_ENABLE))
67#define IS_FMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_LOW) || \
68 ((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_HIGH))
69#define IS_FMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FMC_WAIT_TIMING_BEFORE_WS) || \
70 ((__ACTIVE__) == FMC_WAIT_TIMING_DURING_WS))
71#define IS_FMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FMC_WRITE_OPERATION_DISABLE) || \
72 ((__OPERATION__) == FMC_WRITE_OPERATION_ENABLE))
73#define IS_FMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FMC_WAIT_SIGNAL_DISABLE) || \
74 ((__SIGNAL__) == FMC_WAIT_SIGNAL_ENABLE))
75#define IS_FMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FMC_EXTENDED_MODE_DISABLE) || \
76 ((__MODE__) == FMC_EXTENDED_MODE_ENABLE))
77#define IS_FMC_ASYNWAIT(__STATE__) (((__STATE__) == FMC_ASYNCHRONOUS_WAIT_DISABLE) || \
78 ((__STATE__) == FMC_ASYNCHRONOUS_WAIT_ENABLE))
79#define IS_FMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1U) && ((__LATENCY__) <= 17U))
80#define IS_FMC_WRITE_BURST(__BURST__) (((__BURST__) == FMC_WRITE_BURST_DISABLE) || \
81 ((__BURST__) == FMC_WRITE_BURST_ENABLE))
82#define IS_FMC_CONTINOUS_CLOCK(__CCLOCK__) (((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \
83 ((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
84#define IS_FMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15U)
85#define IS_FMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 15U))
86#define IS_FMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 255U))
87#define IS_FMC_DATAHOLD_DURATION(__DATAHOLD__) ((__DATAHOLD__) <= 3U)
88#define IS_FMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15U)
89#define IS_FMC_CLK_DIV(__DIV__) (((__DIV__) > 1U) && ((__DIV__) <= 16U))
90#define IS_FMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_DEVICE)
91#define IS_FMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_EXTENDED_DEVICE)
92
93
94#define IS_FMC_NAND_BANK(__BANK__) ((__BANK__) == FMC_NAND_BANK3)
95#define IS_FMC_WAIT_FEATURE(__FEATURE__) (((__FEATURE__) == FMC_NAND_WAIT_FEATURE_DISABLE) || \
96 ((__FEATURE__) == FMC_NAND_WAIT_FEATURE_ENABLE))
97#define IS_FMC_NAND_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NAND_MEM_BUS_WIDTH_8) || \
98 ((__WIDTH__) == FMC_NAND_MEM_BUS_WIDTH_16))
99#define IS_FMC_ECC_STATE(__STATE__) (((__STATE__) == FMC_NAND_ECC_DISABLE) || \
100 ((__STATE__) == FMC_NAND_ECC_ENABLE))
101
102#define IS_FMC_ECCPAGE_SIZE(__SIZE__) (((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_256BYTE) || \
103 ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_512BYTE) || \
104 ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \
105 ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \
106 ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \
107 ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE))
108#define IS_FMC_TCLR_TIME(__TIME__) ((__TIME__) <= 255U)
109#define IS_FMC_TAR_TIME(__TIME__) ((__TIME__) <= 255U)
110#define IS_FMC_SETUP_TIME(__TIME__) ((__TIME__) <= 254U)
111#define IS_FMC_WAIT_TIME(__TIME__) ((__TIME__) <= 254U)
112#define IS_FMC_HOLD_TIME(__TIME__) ((__TIME__) <= 254U)
113#define IS_FMC_HIZ_TIME(__TIME__) ((__TIME__) <= 254U)
114#define IS_FMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NAND_DEVICE)
115
116
117#define IS_FMC_SDMEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_SDRAM_MEM_BUS_WIDTH_8) || \
118 ((__WIDTH__) == FMC_SDRAM_MEM_BUS_WIDTH_16) || \
119 ((__WIDTH__) == FMC_SDRAM_MEM_BUS_WIDTH_32))
120#define IS_FMC_WRITE_PROTECTION(__WRITE__) (((__WRITE__) == FMC_SDRAM_WRITE_PROTECTION_DISABLE) || \
121 ((__WRITE__) == FMC_SDRAM_WRITE_PROTECTION_ENABLE))
122#define IS_FMC_SDCLOCK_PERIOD(__PERIOD__) (((__PERIOD__) == FMC_SDRAM_CLOCK_DISABLE) || \
123 ((__PERIOD__) == FMC_SDRAM_CLOCK_PERIOD_2) || \
124 ((__PERIOD__) == FMC_SDRAM_CLOCK_PERIOD_3))
125#define IS_FMC_READ_BURST(__RBURST__) (((__RBURST__) == FMC_SDRAM_RBURST_DISABLE) || \
126 ((__RBURST__) == FMC_SDRAM_RBURST_ENABLE))
127#define IS_FMC_READPIPE_DELAY(__DELAY__) (((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_0) || \
128 ((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_1) || \
129 ((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_2))
130#define IS_FMC_COMMAND_MODE(__COMMAND__) (((__COMMAND__) == FMC_SDRAM_CMD_NORMAL_MODE) || \
131 ((__COMMAND__) == FMC_SDRAM_CMD_CLK_ENABLE) || \
132 ((__COMMAND__) == FMC_SDRAM_CMD_PALL) || \
133 ((__COMMAND__) == FMC_SDRAM_CMD_AUTOREFRESH_MODE) || \
134 ((__COMMAND__) == FMC_SDRAM_CMD_LOAD_MODE) || \
135 ((__COMMAND__) == FMC_SDRAM_CMD_SELFREFRESH_MODE) || \
136 ((__COMMAND__) == FMC_SDRAM_CMD_POWERDOWN_MODE))
137#define IS_FMC_COMMAND_TARGET(__TARGET__) (((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK1) || \
138 ((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK2) || \
139 ((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK1_2))
140#define IS_FMC_LOADTOACTIVE_DELAY(__DELAY__) (((__DELAY__) > 0U) && ((__DELAY__) <= 16U))
141#define IS_FMC_EXITSELFREFRESH_DELAY(__DELAY__) (((__DELAY__) > 0U) && ((__DELAY__) <= 16U))
142#define IS_FMC_SELFREFRESH_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 16U))
143#define IS_FMC_ROWCYCLE_DELAY(__DELAY__) (((__DELAY__) > 0U) && ((__DELAY__) <= 16U))
144#define IS_FMC_WRITE_RECOVERY_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 16U))
145#define IS_FMC_RP_DELAY(__DELAY__) (((__DELAY__) > 0U) && ((__DELAY__) <= 16U))
146#define IS_FMC_RCD_DELAY(__DELAY__) (((__DELAY__) > 0U) && ((__DELAY__) <= 16U))
147#define IS_FMC_AUTOREFRESH_NUMBER(__NUMBER__) (((__NUMBER__) > 0U) && ((__NUMBER__) <= 15U))
148#define IS_FMC_MODE_REGISTER(__CONTENT__) ((__CONTENT__) <= 8191U)
149#define IS_FMC_REFRESH_RATE(__RATE__) ((__RATE__) <= 8191U)
150#define IS_FMC_SDRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_SDRAM_DEVICE)
151#define IS_FMC_SDRAM_BANK(__BANK__) (((__BANK__) == FMC_SDRAM_BANK1) || \
152 ((__BANK__) == FMC_SDRAM_BANK2))
153#define IS_FMC_COLUMNBITS_NUMBER(__COLUMN__) (((__COLUMN__) == FMC_SDRAM_COLUMN_BITS_NUM_8) || \
154 ((__COLUMN__) == FMC_SDRAM_COLUMN_BITS_NUM_9) || \
155 ((__COLUMN__) == FMC_SDRAM_COLUMN_BITS_NUM_10) || \
156 ((__COLUMN__) == FMC_SDRAM_COLUMN_BITS_NUM_11))
157#define IS_FMC_ROWBITS_NUMBER(__ROW__) (((__ROW__) == FMC_SDRAM_ROW_BITS_NUM_11) || \
158 ((__ROW__) == FMC_SDRAM_ROW_BITS_NUM_12) || \
159 ((__ROW__) == FMC_SDRAM_ROW_BITS_NUM_13))
160#define IS_FMC_INTERNALBANK_NUMBER(__NUMBER__) (((__NUMBER__) == FMC_SDRAM_INTERN_BANKS_NUM_2) || \
161 ((__NUMBER__) == FMC_SDRAM_INTERN_BANKS_NUM_4))
162#define IS_FMC_CAS_LATENCY(__LATENCY__) (((__LATENCY__) == FMC_SDRAM_CAS_LATENCY_1) || \
163 ((__LATENCY__) == FMC_SDRAM_CAS_LATENCY_2) || \
164 ((__LATENCY__) == FMC_SDRAM_CAS_LATENCY_3))
165
166
171/* Exported typedef ----------------------------------------------------------*/
172
178#define FMC_NORSRAM_TypeDef FMC_Bank1_TypeDef
179#define FMC_NORSRAM_EXTENDED_TypeDef FMC_Bank1E_TypeDef
180#define FMC_NAND_TypeDef FMC_Bank3_TypeDef
181#define FMC_SDRAM_TypeDef FMC_Bank5_6_TypeDef
182
183#define FMC_NORSRAM_DEVICE FMC_Bank1_R
184#define FMC_NORSRAM_EXTENDED_DEVICE FMC_Bank1E_R
185#define FMC_NAND_DEVICE FMC_Bank3_R
186#define FMC_SDRAM_DEVICE FMC_Bank5_6_R
187
191typedef struct
192{
193 uint32_t NSBank;
196 uint32_t DataAddressMux;
200 uint32_t MemoryType;
204 uint32_t MemoryDataWidth;
207 uint32_t BurstAccessMode;
211 uint32_t WaitSignalPolarity;
215 uint32_t WaitSignalActive;
220 uint32_t WriteOperation;
223 uint32_t WaitSignal;
227 uint32_t ExtendedMode;
230 uint32_t AsynchronousWait;
234 uint32_t WriteBurst;
237 uint32_t ContinuousClock;
242 uint32_t WriteFifo;
247 uint32_t PageSize;
249} FMC_NORSRAM_InitTypeDef;
250
254typedef struct
255{
256 uint32_t AddressSetupTime;
261 uint32_t AddressHoldTime;
266 uint32_t DataSetupTime;
272 uint32_t BusTurnAroundDuration;
277 uint32_t CLKDivision;
283 uint32_t DataLatency;
291 uint32_t AccessMode;
293} FMC_NORSRAM_TimingTypeDef;
294
298typedef struct
299{
300 uint32_t NandBank;
303 uint32_t Waitfeature;
306 uint32_t MemoryDataWidth;
309 uint32_t EccComputation;
312 uint32_t ECCPageSize;
315 uint32_t TCLRSetupTime;
319 uint32_t TARSetupTime;
322} FMC_NAND_InitTypeDef;
323
327typedef struct
328{
329 uint32_t SetupTime;
335 uint32_t WaitSetupTime;
341 uint32_t HoldSetupTime;
348 uint32_t HiZSetupTime;
353} FMC_NAND_PCC_TimingTypeDef;
354
355
359typedef struct
360{
361 uint32_t SDBank;
364 uint32_t ColumnBitsNumber;
367 uint32_t RowBitsNumber;
370 uint32_t MemoryDataWidth;
373 uint32_t InternalBankNumber;
376 uint32_t CASLatency;
379 uint32_t WriteProtection;
382 uint32_t SDClockPeriod;
386 uint32_t ReadBurst;
390 uint32_t ReadPipeDelay;
392} FMC_SDRAM_InitTypeDef;
393
397typedef struct
398{
399 uint32_t LoadToActiveDelay;
403 uint32_t ExitSelfRefreshDelay;
407 uint32_t SelfRefreshTime;
411 uint32_t RowCycleDelay;
416 uint32_t WriteRecoveryTime;
419 uint32_t RPDelay;
423 uint32_t RCDDelay;
426} FMC_SDRAM_TimingTypeDef;
427
431typedef struct
432{
433 uint32_t CommandMode;
436 uint32_t CommandTarget;
439 uint32_t AutoRefreshNumber;
443 uint32_t ModeRegisterDefinition;
444} FMC_SDRAM_CommandTypeDef;
449/* Exported constants --------------------------------------------------------*/
463#define FMC_NORSRAM_BANK1 (0x00000000U)
464#define FMC_NORSRAM_BANK2 (0x00000002U)
465#define FMC_NORSRAM_BANK3 (0x00000004U)
466#define FMC_NORSRAM_BANK4 (0x00000006U)
475#define FMC_DATA_ADDRESS_MUX_DISABLE (0x00000000U)
476#define FMC_DATA_ADDRESS_MUX_ENABLE (0x00000002U)
485#define FMC_MEMORY_TYPE_SRAM (0x00000000U)
486#define FMC_MEMORY_TYPE_PSRAM (0x00000004U)
487#define FMC_MEMORY_TYPE_NOR (0x00000008U)
496#define FMC_NORSRAM_MEM_BUS_WIDTH_8 (0x00000000U)
497#define FMC_NORSRAM_MEM_BUS_WIDTH_16 (0x00000010U)
498#define FMC_NORSRAM_MEM_BUS_WIDTH_32 (0x00000020U)
507#define FMC_NORSRAM_FLASH_ACCESS_ENABLE (0x00000040U)
508#define FMC_NORSRAM_FLASH_ACCESS_DISABLE (0x00000000U)
517#define FMC_BURST_ACCESS_MODE_DISABLE (0x00000000U)
518#define FMC_BURST_ACCESS_MODE_ENABLE (0x00000100U)
527#define FMC_WAIT_SIGNAL_POLARITY_LOW (0x00000000U)
528#define FMC_WAIT_SIGNAL_POLARITY_HIGH (0x00000200U)
537#define FMC_WAIT_TIMING_BEFORE_WS (0x00000000U)
538#define FMC_WAIT_TIMING_DURING_WS (0x00000800U)
547#define FMC_WRITE_OPERATION_DISABLE (0x00000000U)
548#define FMC_WRITE_OPERATION_ENABLE (0x00001000U)
557#define FMC_WAIT_SIGNAL_DISABLE (0x00000000U)
558#define FMC_WAIT_SIGNAL_ENABLE (0x00002000U)
567#define FMC_EXTENDED_MODE_DISABLE (0x00000000U)
568#define FMC_EXTENDED_MODE_ENABLE (0x00004000U)
577#define FMC_ASYNCHRONOUS_WAIT_DISABLE (0x00000000U)
578#define FMC_ASYNCHRONOUS_WAIT_ENABLE (0x00008000U)
587#define FMC_PAGE_SIZE_NONE (0x00000000U)
588#define FMC_PAGE_SIZE_128 FMC_BCRx_CPSIZE_0
589#define FMC_PAGE_SIZE_256 FMC_BCRx_CPSIZE_1
590#define FMC_PAGE_SIZE_512 (FMC_BCRx_CPSIZE_0\
591 | FMC_BCRx_CPSIZE_1)
592#define FMC_PAGE_SIZE_1024 FMC_BCRx_CPSIZE_2
601#define FMC_WRITE_BURST_DISABLE (0x00000000U)
602#define FMC_WRITE_BURST_ENABLE (0x00080000U)
611#define FMC_CONTINUOUS_CLOCK_SYNC_ONLY (0x00000000U)
612#define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC (0x00100000U)
617#if defined(FMC_BCR1_WFDIS)
622#define FMC_WRITE_FIFO_DISABLE FMC_BCR1_WFDIS
623#define FMC_WRITE_FIFO_ENABLE (0x00000000U)
624#endif /* FMC_BCR1_WFDIS */
633#define FMC_ACCESS_MODE_A (0x00000000U)
634#define FMC_ACCESS_MODE_B (0x10000000U)
635#define FMC_ACCESS_MODE_C (0x20000000U)
636#define FMC_ACCESS_MODE_D (0x30000000U)
654#define FMC_NAND_BANK3 (0x00000100U)
663#define FMC_NAND_WAIT_FEATURE_DISABLE (0x00000000U)
664#define FMC_NAND_WAIT_FEATURE_ENABLE (0x00000002U)
673#define FMC_PCR_MEMORY_TYPE_NAND (0x00000008U)
682#define FMC_NAND_MEM_BUS_WIDTH_8 (0x00000000U)
683#define FMC_NAND_MEM_BUS_WIDTH_16 (0x00000010U)
692#define FMC_NAND_ECC_DISABLE (0x00000000U)
693#define FMC_NAND_ECC_ENABLE (0x00000040U)
702#define FMC_NAND_ECC_PAGE_SIZE_256BYTE (0x00000000U)
703#define FMC_NAND_ECC_PAGE_SIZE_512BYTE (0x00020000U)
704#define FMC_NAND_ECC_PAGE_SIZE_1024BYTE (0x00040000U)
705#define FMC_NAND_ECC_PAGE_SIZE_2048BYTE (0x00060000U)
706#define FMC_NAND_ECC_PAGE_SIZE_4096BYTE (0x00080000U)
707#define FMC_NAND_ECC_PAGE_SIZE_8192BYTE (0x000A0000U)
724#define FMC_SDRAM_BANK1 (0x00000000U)
725#define FMC_SDRAM_BANK2 (0x00000001U)
734#define FMC_SDRAM_COLUMN_BITS_NUM_8 (0x00000000U)
735#define FMC_SDRAM_COLUMN_BITS_NUM_9 (0x00000001U)
736#define FMC_SDRAM_COLUMN_BITS_NUM_10 (0x00000002U)
737#define FMC_SDRAM_COLUMN_BITS_NUM_11 (0x00000003U)
746#define FMC_SDRAM_ROW_BITS_NUM_11 (0x00000000U)
747#define FMC_SDRAM_ROW_BITS_NUM_12 (0x00000004U)
748#define FMC_SDRAM_ROW_BITS_NUM_13 (0x00000008U)
757#define FMC_SDRAM_MEM_BUS_WIDTH_8 (0x00000000U)
758#define FMC_SDRAM_MEM_BUS_WIDTH_16 (0x00000010U)
759#define FMC_SDRAM_MEM_BUS_WIDTH_32 (0x00000020U)
768#define FMC_SDRAM_INTERN_BANKS_NUM_2 (0x00000000U)
769#define FMC_SDRAM_INTERN_BANKS_NUM_4 (0x00000040U)
778#define FMC_SDRAM_CAS_LATENCY_1 (0x00000080U)
779#define FMC_SDRAM_CAS_LATENCY_2 (0x00000100U)
780#define FMC_SDRAM_CAS_LATENCY_3 (0x00000180U)
789#define FMC_SDRAM_WRITE_PROTECTION_DISABLE (0x00000000U)
790#define FMC_SDRAM_WRITE_PROTECTION_ENABLE (0x00000200U)
799#define FMC_SDRAM_CLOCK_DISABLE (0x00000000U)
800#define FMC_SDRAM_CLOCK_PERIOD_2 (0x00000800U)
801#define FMC_SDRAM_CLOCK_PERIOD_3 (0x00000C00U)
810#define FMC_SDRAM_RBURST_DISABLE (0x00000000U)
811#define FMC_SDRAM_RBURST_ENABLE (0x00001000U)
820#define FMC_SDRAM_RPIPE_DELAY_0 (0x00000000U)
821#define FMC_SDRAM_RPIPE_DELAY_1 (0x00002000U)
822#define FMC_SDRAM_RPIPE_DELAY_2 (0x00004000U)
831#define FMC_SDRAM_CMD_NORMAL_MODE (0x00000000U)
832#define FMC_SDRAM_CMD_CLK_ENABLE (0x00000001U)
833#define FMC_SDRAM_CMD_PALL (0x00000002U)
834#define FMC_SDRAM_CMD_AUTOREFRESH_MODE (0x00000003U)
835#define FMC_SDRAM_CMD_LOAD_MODE (0x00000004U)
836#define FMC_SDRAM_CMD_SELFREFRESH_MODE (0x00000005U)
837#define FMC_SDRAM_CMD_POWERDOWN_MODE (0x00000006U)
846#define FMC_SDRAM_CMD_TARGET_BANK2 FMC_SDCMR_CTB2
847#define FMC_SDRAM_CMD_TARGET_BANK1 FMC_SDCMR_CTB1
848#define FMC_SDRAM_CMD_TARGET_BANK1_2 (0x00000018U)
857#define FMC_SDRAM_NORMAL_MODE (0x00000000U)
858#define FMC_SDRAM_SELF_REFRESH_MODE FMC_SDSR_MODES1_0
859#define FMC_SDRAM_POWER_DOWN_MODE FMC_SDSR_MODES1_1
873#define FMC_IT_RISING_EDGE (0x00000008U)
874#define FMC_IT_LEVEL (0x00000010U)
875#define FMC_IT_FALLING_EDGE (0x00000020U)
876#define FMC_IT_REFRESH_ERROR (0x00004000U)
885#define FMC_FLAG_RISING_EDGE (0x00000001U)
886#define FMC_FLAG_LEVEL (0x00000002U)
887#define FMC_FLAG_FALLING_EDGE (0x00000004U)
888#define FMC_FLAG_FEMPT (0x00000040U)
889#define FMC_SDRAM_FLAG_REFRESH_IT FMC_SDSR_RE
890#define FMC_SDRAM_FLAG_BUSY FMC_SDSR_BUSY
891#define FMC_SDRAM_FLAG_REFRESH_ERROR FMC_SDRTR_CRE
904/* Private macro -------------------------------------------------------------*/
913#define __FMC_ENABLE() (FMC_Bank1_R->BTCR[0] |= FMC_BCR1_FMCEN)
914
919#define __FMC_DISABLE() (FMC_Bank1_R->BTCR[0] &= ~FMC_BCR1_FMCEN)
932#define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\
933 |= FMC_BCRx_MBKEN)
934
941#define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\
942 &= ~FMC_BCRx_MBKEN)
943
959#define __FMC_NAND_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR |= FMC_PCR_PBKEN)
960
967#define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) CLEAR_BIT((__INSTANCE__)->PCR, FMC_PCR_PBKEN)
968
989#define __FMC_NAND_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR |= (__INTERRUPT__))
990
1001#define __FMC_NAND_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR &= ~(__INTERRUPT__))
1002
1015#define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__INSTANCE__)->SR &(__FLAG__)) == (__FLAG__))
1016
1028#define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR &= ~(__FLAG__))
1029
1049#define __FMC_SDRAM_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR |= (__INTERRUPT__))
1050
1059#define __FMC_SDRAM_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR &= ~(__INTERRUPT__))
1060
1071#define __FMC_SDRAM_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SDSR &(__FLAG__)) == (__FLAG__))
1072
1081#define __FMC_SDRAM_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SDRTR |= (__FLAG__))
1082
1094/* Private functions ---------------------------------------------------------*/
1108HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device,
1109 FMC_NORSRAM_InitTypeDef *Init);
1110HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device,
1111 FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
1112HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device,
1113 FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank,
1114 uint32_t ExtendedMode);
1115HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device,
1116 FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);
1125HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
1126HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
1142HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init);
1143HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device,
1144 FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
1145HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device,
1146 FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
1147HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank);
1156HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank);
1157HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank);
1158HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank,
1159 uint32_t Timeout);
1176HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init);
1177HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device,
1178 FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank);
1179HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
1188HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
1189HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
1190HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device,
1191 FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout);
1192HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate);
1193HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device,
1194 uint32_t AutoRefreshNumber);
1195uint32_t FMC_SDRAM_GetModeStatus(const FMC_SDRAM_TypeDef *Device, uint32_t Bank);
1215#ifdef __cplusplus
1216}
1217#endif
1218
1219#endif /* STM32H7xx_LL_FMC_H */
stm32h7xx_hal_def.h
This file contains HAL common defines, enumeration, macros and structures definitions.
HAL_StatusTypeDef
HAL_StatusTypeDef
HAL Status structures definition.
Definition: stm32h7xx_hal_def.h:47
FMC_NAND_InitTypeDef
FMC NAND Configuration Structure definition.
Definition: stm32h7xx_ll_fmc.h:299
FMC_NAND_InitTypeDef::TCLRSetupTime
uint32_t TCLRSetupTime
Definition: stm32h7xx_ll_fmc.h:315
FMC_NAND_InitTypeDef::TARSetupTime
uint32_t TARSetupTime
Definition: stm32h7xx_ll_fmc.h:319
FMC_NAND_InitTypeDef::ECCPageSize
uint32_t ECCPageSize
Definition: stm32h7xx_ll_fmc.h:312
FMC_NAND_InitTypeDef::EccComputation
uint32_t EccComputation
Definition: stm32h7xx_ll_fmc.h:309
FMC_NAND_InitTypeDef::NandBank
uint32_t NandBank
Definition: stm32h7xx_ll_fmc.h:300
FMC_NAND_InitTypeDef::Waitfeature
uint32_t Waitfeature
Definition: stm32h7xx_ll_fmc.h:303
FMC_NAND_InitTypeDef::MemoryDataWidth
uint32_t MemoryDataWidth
Definition: stm32h7xx_ll_fmc.h:306
FMC_NAND_PCC_TimingTypeDef
FMC NAND Timing parameters structure definition.
Definition: stm32h7xx_ll_fmc.h:328
FMC_NAND_PCC_TimingTypeDef::HiZSetupTime
uint32_t HiZSetupTime
Definition: stm32h7xx_ll_fmc.h:348
FMC_NAND_PCC_TimingTypeDef::HoldSetupTime
uint32_t HoldSetupTime
Definition: stm32h7xx_ll_fmc.h:341
FMC_NAND_PCC_TimingTypeDef::SetupTime
uint32_t SetupTime
Definition: stm32h7xx_ll_fmc.h:329
FMC_NAND_PCC_TimingTypeDef::WaitSetupTime
uint32_t WaitSetupTime
Definition: stm32h7xx_ll_fmc.h:335
FMC_NORSRAM_InitTypeDef
FMC NORSRAM Configuration Structure definition.
Definition: stm32h7xx_ll_fmc.h:192
FMC_NORSRAM_InitTypeDef::MemoryDataWidth
uint32_t MemoryDataWidth
Definition: stm32h7xx_ll_fmc.h:204
FMC_NORSRAM_InitTypeDef::WriteBurst
uint32_t WriteBurst
Definition: stm32h7xx_ll_fmc.h:234
FMC_NORSRAM_InitTypeDef::PageSize
uint32_t PageSize
Definition: stm32h7xx_ll_fmc.h:247
FMC_NORSRAM_InitTypeDef::BurstAccessMode
uint32_t BurstAccessMode
Definition: stm32h7xx_ll_fmc.h:207
FMC_NORSRAM_InitTypeDef::ExtendedMode
uint32_t ExtendedMode
Definition: stm32h7xx_ll_fmc.h:227
FMC_NORSRAM_InitTypeDef::MemoryType
uint32_t MemoryType
Definition: stm32h7xx_ll_fmc.h:200
FMC_NORSRAM_InitTypeDef::DataAddressMux
uint32_t DataAddressMux
Definition: stm32h7xx_ll_fmc.h:196
FMC_NORSRAM_InitTypeDef::WriteFifo
uint32_t WriteFifo
Definition: stm32h7xx_ll_fmc.h:242
FMC_NORSRAM_InitTypeDef::AsynchronousWait
uint32_t AsynchronousWait
Definition: stm32h7xx_ll_fmc.h:230
FMC_NORSRAM_InitTypeDef::WriteOperation
uint32_t WriteOperation
Definition: stm32h7xx_ll_fmc.h:220
FMC_NORSRAM_InitTypeDef::WaitSignalActive
uint32_t WaitSignalActive
Definition: stm32h7xx_ll_fmc.h:215
FMC_NORSRAM_InitTypeDef::WaitSignal
uint32_t WaitSignal
Definition: stm32h7xx_ll_fmc.h:223
FMC_NORSRAM_InitTypeDef::WaitSignalPolarity
uint32_t WaitSignalPolarity
Definition: stm32h7xx_ll_fmc.h:211
FMC_NORSRAM_InitTypeDef::NSBank
uint32_t NSBank
Definition: stm32h7xx_ll_fmc.h:193
FMC_NORSRAM_InitTypeDef::ContinuousClock
uint32_t ContinuousClock
Definition: stm32h7xx_ll_fmc.h:237
FMC_NORSRAM_TimingTypeDef
FMC NORSRAM Timing parameters structure definition.
Definition: stm32h7xx_ll_fmc.h:255
FMC_NORSRAM_TimingTypeDef::CLKDivision
uint32_t CLKDivision
Definition: stm32h7xx_ll_fmc.h:277
FMC_NORSRAM_TimingTypeDef::AddressSetupTime
uint32_t AddressSetupTime
Definition: stm32h7xx_ll_fmc.h:256
FMC_NORSRAM_TimingTypeDef::BusTurnAroundDuration
uint32_t BusTurnAroundDuration
Definition: stm32h7xx_ll_fmc.h:272
FMC_NORSRAM_TimingTypeDef::DataSetupTime
uint32_t DataSetupTime
Definition: stm32h7xx_ll_fmc.h:266
FMC_NORSRAM_TimingTypeDef::AccessMode
uint32_t AccessMode
Definition: stm32h7xx_ll_fmc.h:291
FMC_NORSRAM_TimingTypeDef::AddressHoldTime
uint32_t AddressHoldTime
Definition: stm32h7xx_ll_fmc.h:261
FMC_NORSRAM_TimingTypeDef::DataLatency
uint32_t DataLatency
Definition: stm32h7xx_ll_fmc.h:283
FMC_SDRAM_CommandTypeDef
SDRAM command parameters structure definition.
Definition: stm32h7xx_ll_fmc.h:432
FMC_SDRAM_CommandTypeDef::CommandTarget
uint32_t CommandTarget
Definition: stm32h7xx_ll_fmc.h:436
FMC_SDRAM_CommandTypeDef::AutoRefreshNumber
uint32_t AutoRefreshNumber
Definition: stm32h7xx_ll_fmc.h:439
FMC_SDRAM_CommandTypeDef::ModeRegisterDefinition
uint32_t ModeRegisterDefinition
Definition: stm32h7xx_ll_fmc.h:443
FMC_SDRAM_CommandTypeDef::CommandMode
uint32_t CommandMode
Definition: stm32h7xx_ll_fmc.h:433
FMC_SDRAM_InitTypeDef
FMC SDRAM Configuration Structure definition.
Definition: stm32h7xx_ll_fmc.h:360
FMC_SDRAM_InitTypeDef::InternalBankNumber
uint32_t InternalBankNumber
Definition: stm32h7xx_ll_fmc.h:373
FMC_SDRAM_InitTypeDef::ColumnBitsNumber
uint32_t ColumnBitsNumber
Definition: stm32h7xx_ll_fmc.h:364
FMC_SDRAM_InitTypeDef::ReadPipeDelay
uint32_t ReadPipeDelay
Definition: stm32h7xx_ll_fmc.h:390
FMC_SDRAM_InitTypeDef::MemoryDataWidth
uint32_t MemoryDataWidth
Definition: stm32h7xx_ll_fmc.h:370
FMC_SDRAM_InitTypeDef::WriteProtection
uint32_t WriteProtection
Definition: stm32h7xx_ll_fmc.h:379
FMC_SDRAM_InitTypeDef::RowBitsNumber
uint32_t RowBitsNumber
Definition: stm32h7xx_ll_fmc.h:367
FMC_SDRAM_InitTypeDef::CASLatency
uint32_t CASLatency
Definition: stm32h7xx_ll_fmc.h:376
FMC_SDRAM_InitTypeDef::ReadBurst
uint32_t ReadBurst
Definition: stm32h7xx_ll_fmc.h:386
FMC_SDRAM_InitTypeDef::SDBank
uint32_t SDBank
Definition: stm32h7xx_ll_fmc.h:361
FMC_SDRAM_InitTypeDef::SDClockPeriod
uint32_t SDClockPeriod
Definition: stm32h7xx_ll_fmc.h:382
FMC_SDRAM_TimingTypeDef
FMC SDRAM Timing parameters structure definition.
Definition: stm32h7xx_ll_fmc.h:398
FMC_SDRAM_TimingTypeDef::ExitSelfRefreshDelay
uint32_t ExitSelfRefreshDelay
Definition: stm32h7xx_ll_fmc.h:403
FMC_SDRAM_TimingTypeDef::RPDelay
uint32_t RPDelay
Definition: stm32h7xx_ll_fmc.h:419
FMC_SDRAM_TimingTypeDef::SelfRefreshTime
uint32_t SelfRefreshTime
Definition: stm32h7xx_ll_fmc.h:407
FMC_SDRAM_TimingTypeDef::RCDDelay
uint32_t RCDDelay
Definition: stm32h7xx_ll_fmc.h:423
FMC_SDRAM_TimingTypeDef::WriteRecoveryTime
uint32_t WriteRecoveryTime
Definition: stm32h7xx_ll_fmc.h:416
FMC_SDRAM_TimingTypeDef::LoadToActiveDelay
uint32_t LoadToActiveDelay
Definition: stm32h7xx_ll_fmc.h:399
FMC_SDRAM_TimingTypeDef::RowCycleDelay
uint32_t RowCycleDelay
Definition: stm32h7xx_ll_fmc.h:411
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