RTEMS 6.1-rc5
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stm32h7xx_hal_smbus.h
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1
19/* Define to prevent recursive inclusion -------------------------------------*/
20#ifndef STM32H7xx_HAL_SMBUS_H
21#define STM32H7xx_HAL_SMBUS_H
22
23#ifdef __cplusplus
24extern "C" {
25#endif
26
27/* Includes ------------------------------------------------------------------*/
28#include "stm32h7xx_hal_def.h"
29
38/* Exported types ------------------------------------------------------------*/
49typedef struct
50{
51 uint32_t Timing;
54 uint32_t AnalogFilter;
57 uint32_t OwnAddress1;
60 uint32_t AddressingMode;
63 uint32_t DualAddressMode;
66 uint32_t OwnAddress2;
69 uint32_t OwnAddress2Masks;
73 uint32_t GeneralCallMode;
76 uint32_t NoStretchMode;
79 uint32_t PacketErrorCheckMode;
82 uint32_t PeripheralMode;
85 uint32_t SMBusTimeout;
89} SMBUS_InitTypeDef;
99#define HAL_SMBUS_STATE_RESET (0x00000000U)
100#define HAL_SMBUS_STATE_READY (0x00000001U)
101#define HAL_SMBUS_STATE_BUSY (0x00000002U)
102#define HAL_SMBUS_STATE_MASTER_BUSY_TX (0x00000012U)
103#define HAL_SMBUS_STATE_MASTER_BUSY_RX (0x00000022U)
104#define HAL_SMBUS_STATE_SLAVE_BUSY_TX (0x00000032U)
105#define HAL_SMBUS_STATE_SLAVE_BUSY_RX (0x00000042U)
106#define HAL_SMBUS_STATE_LISTEN (0x00000008U)
116#define HAL_SMBUS_ERROR_NONE (0x00000000U)
117#define HAL_SMBUS_ERROR_BERR (0x00000001U)
118#define HAL_SMBUS_ERROR_ARLO (0x00000002U)
119#define HAL_SMBUS_ERROR_ACKF (0x00000004U)
120#define HAL_SMBUS_ERROR_OVR (0x00000008U)
121#define HAL_SMBUS_ERROR_HALTIMEOUT (0x00000010U)
122#define HAL_SMBUS_ERROR_BUSTIMEOUT (0x00000020U)
123#define HAL_SMBUS_ERROR_ALERT (0x00000040U)
124#define HAL_SMBUS_ERROR_PECERR (0x00000080U)
125#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
126#define HAL_SMBUS_ERROR_INVALID_CALLBACK (0x00000100U)
127#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
128#define HAL_SMBUS_ERROR_INVALID_PARAM (0x00000200U)
138#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
139typedef struct __SMBUS_HandleTypeDef
140#else
141typedef struct
142#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
143{
144 I2C_TypeDef *Instance;
146 SMBUS_InitTypeDef Init;
148 uint8_t *pBuffPtr;
150 uint16_t XferSize;
152 __IO uint16_t XferCount;
154 __IO uint32_t XferOptions;
156 __IO uint32_t PreviousState;
158 HAL_LockTypeDef Lock;
160 __IO uint32_t State;
162 __IO uint32_t ErrorCode;
164#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
165 void (* MasterTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
167 void (* MasterRxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
169 void (* SlaveTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
171 void (* SlaveRxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
173 void (* ListenCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
175 void (* ErrorCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
178 void (* AddrCallback)(struct __SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode);
181 void (* MspInitCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
183 void (* MspDeInitCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
186#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
187} SMBUS_HandleTypeDef;
188
189#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
193typedef enum
194{
195 HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID = 0x00U,
196 HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID = 0x01U,
197 HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID = 0x02U,
198 HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID = 0x03U,
199 HAL_SMBUS_LISTEN_COMPLETE_CB_ID = 0x04U,
200 HAL_SMBUS_ERROR_CB_ID = 0x05U,
202 HAL_SMBUS_MSPINIT_CB_ID = 0x06U,
203 HAL_SMBUS_MSPDEINIT_CB_ID = 0x07U
205} HAL_SMBUS_CallbackIDTypeDef;
206
210typedef void (*pSMBUS_CallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus);
212typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection,
213 uint16_t AddrMatchCode);
216#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
224/* Exported constants --------------------------------------------------------*/
225
235#define SMBUS_ANALOGFILTER_ENABLE (0x00000000U)
236#define SMBUS_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF
245#define SMBUS_ADDRESSINGMODE_7BIT (0x00000001U)
246#define SMBUS_ADDRESSINGMODE_10BIT (0x00000002U)
256#define SMBUS_DUALADDRESS_DISABLE (0x00000000U)
257#define SMBUS_DUALADDRESS_ENABLE I2C_OAR2_OA2EN
267#define SMBUS_OA2_NOMASK ((uint8_t)0x00U)
268#define SMBUS_OA2_MASK01 ((uint8_t)0x01U)
269#define SMBUS_OA2_MASK02 ((uint8_t)0x02U)
270#define SMBUS_OA2_MASK03 ((uint8_t)0x03U)
271#define SMBUS_OA2_MASK04 ((uint8_t)0x04U)
272#define SMBUS_OA2_MASK05 ((uint8_t)0x05U)
273#define SMBUS_OA2_MASK06 ((uint8_t)0x06U)
274#define SMBUS_OA2_MASK07 ((uint8_t)0x07U)
284#define SMBUS_GENERALCALL_DISABLE (0x00000000U)
285#define SMBUS_GENERALCALL_ENABLE I2C_CR1_GCEN
294#define SMBUS_NOSTRETCH_DISABLE (0x00000000U)
295#define SMBUS_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH
304#define SMBUS_PEC_DISABLE (0x00000000U)
305#define SMBUS_PEC_ENABLE I2C_CR1_PECEN
314#define SMBUS_PERIPHERAL_MODE_SMBUS_HOST I2C_CR1_SMBHEN
315#define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE (0x00000000U)
316#define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP I2C_CR1_SMBDEN
326#define SMBUS_SOFTEND_MODE (0x00000000U)
327#define SMBUS_RELOAD_MODE I2C_CR2_RELOAD
328#define SMBUS_AUTOEND_MODE I2C_CR2_AUTOEND
329#define SMBUS_SENDPEC_MODE I2C_CR2_PECBYTE
339#define SMBUS_NO_STARTSTOP (0x00000000U)
340#define SMBUS_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP)
341#define SMBUS_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
342#define SMBUS_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
352/* List of XferOptions in usage of :
353 * 1- Restart condition when direction change
354 * 2- No Restart condition in other use cases
355 */
356#define SMBUS_FIRST_FRAME SMBUS_SOFTEND_MODE
357#define SMBUS_NEXT_FRAME ((uint32_t)(SMBUS_RELOAD_MODE | SMBUS_SOFTEND_MODE))
358#define SMBUS_FIRST_AND_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE
359#define SMBUS_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE
360#define SMBUS_FIRST_FRAME_WITH_PEC ((uint32_t)(SMBUS_SOFTEND_MODE | SMBUS_SENDPEC_MODE))
361#define SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
362#define SMBUS_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
363
364/* List of XferOptions in usage of :
365 * 1- Restart condition in all use cases (direction change or not)
366 */
367#define SMBUS_OTHER_FRAME_NO_PEC (0x000000AAU)
368#define SMBUS_OTHER_FRAME_WITH_PEC (0x0000AA00U)
369#define SMBUS_OTHER_AND_LAST_FRAME_NO_PEC (0x00AA0000U)
370#define SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC (0xAA000000U)
382#define SMBUS_IT_ERRI I2C_CR1_ERRIE
383#define SMBUS_IT_TCI I2C_CR1_TCIE
384#define SMBUS_IT_STOPI I2C_CR1_STOPIE
385#define SMBUS_IT_NACKI I2C_CR1_NACKIE
386#define SMBUS_IT_ADDRI I2C_CR1_ADDRIE
387#define SMBUS_IT_RXI I2C_CR1_RXIE
388#define SMBUS_IT_TXI I2C_CR1_TXIE
389#define SMBUS_IT_TX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | \
390 SMBUS_IT_NACKI | SMBUS_IT_TXI)
391#define SMBUS_IT_RX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_NACKI | \
392 SMBUS_IT_RXI)
393#define SMBUS_IT_ALERT (SMBUS_IT_ERRI)
394#define SMBUS_IT_ADDR (SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI)
407#define SMBUS_FLAG_TXE I2C_ISR_TXE
408#define SMBUS_FLAG_TXIS I2C_ISR_TXIS
409#define SMBUS_FLAG_RXNE I2C_ISR_RXNE
410#define SMBUS_FLAG_ADDR I2C_ISR_ADDR
411#define SMBUS_FLAG_AF I2C_ISR_NACKF
412#define SMBUS_FLAG_STOPF I2C_ISR_STOPF
413#define SMBUS_FLAG_TC I2C_ISR_TC
414#define SMBUS_FLAG_TCR I2C_ISR_TCR
415#define SMBUS_FLAG_BERR I2C_ISR_BERR
416#define SMBUS_FLAG_ARLO I2C_ISR_ARLO
417#define SMBUS_FLAG_OVR I2C_ISR_OVR
418#define SMBUS_FLAG_PECERR I2C_ISR_PECERR
419#define SMBUS_FLAG_TIMEOUT I2C_ISR_TIMEOUT
420#define SMBUS_FLAG_ALERT I2C_ISR_ALERT
421#define SMBUS_FLAG_BUSY I2C_ISR_BUSY
422#define SMBUS_FLAG_DIR I2C_ISR_DIR
431/* Exported macros ------------------------------------------------------------*/
441#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
442#define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) do{ \
443 (__HANDLE__)->State = HAL_SMBUS_STATE_RESET; \
444 (__HANDLE__)->MspInitCallback = NULL; \
445 (__HANDLE__)->MspDeInitCallback = NULL; \
446 } while(0)
447#else
448#define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SMBUS_STATE_RESET)
449#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
450
465#define __HAL_SMBUS_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
466
481#define __HAL_SMBUS_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
482
497#define __HAL_SMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
498 ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
499
523#define SMBUS_FLAG_MASK (0x0001FFFFU)
524#define __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__) \
525 (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == \
526 ((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET)
527
545#define __HAL_SMBUS_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == SMBUS_FLAG_TXE) ? \
546 ((__HANDLE__)->Instance->ISR |= (__FLAG__)) : \
547 ((__HANDLE__)->Instance->ICR = (__FLAG__)))
548
553#define __HAL_SMBUS_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
554
559#define __HAL_SMBUS_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
560
565#define __HAL_SMBUS_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
566
572/* Private constants ---------------------------------------------------------*/
573
574/* Private macros ------------------------------------------------------------*/
580#define IS_SMBUS_ANALOG_FILTER(FILTER) (((FILTER) == SMBUS_ANALOGFILTER_ENABLE) || \
581 ((FILTER) == SMBUS_ANALOGFILTER_DISABLE))
582
583#define IS_SMBUS_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU)
584
585#define IS_SMBUS_ADDRESSING_MODE(MODE) (((MODE) == SMBUS_ADDRESSINGMODE_7BIT) || \
586 ((MODE) == SMBUS_ADDRESSINGMODE_10BIT))
587
588#define IS_SMBUS_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == SMBUS_DUALADDRESS_DISABLE) || \
589 ((ADDRESS) == SMBUS_DUALADDRESS_ENABLE))
590
591#define IS_SMBUS_OWN_ADDRESS2_MASK(MASK) (((MASK) == SMBUS_OA2_NOMASK) || \
592 ((MASK) == SMBUS_OA2_MASK01) || \
593 ((MASK) == SMBUS_OA2_MASK02) || \
594 ((MASK) == SMBUS_OA2_MASK03) || \
595 ((MASK) == SMBUS_OA2_MASK04) || \
596 ((MASK) == SMBUS_OA2_MASK05) || \
597 ((MASK) == SMBUS_OA2_MASK06) || \
598 ((MASK) == SMBUS_OA2_MASK07))
599
600#define IS_SMBUS_GENERAL_CALL(CALL) (((CALL) == SMBUS_GENERALCALL_DISABLE) || \
601 ((CALL) == SMBUS_GENERALCALL_ENABLE))
602
603#define IS_SMBUS_NO_STRETCH(STRETCH) (((STRETCH) == SMBUS_NOSTRETCH_DISABLE) || \
604 ((STRETCH) == SMBUS_NOSTRETCH_ENABLE))
605
606#define IS_SMBUS_PEC(PEC) (((PEC) == SMBUS_PEC_DISABLE) || \
607 ((PEC) == SMBUS_PEC_ENABLE))
608
609#define IS_SMBUS_PERIPHERAL_MODE(MODE) (((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_HOST) || \
610 ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || \
611 ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP))
612
613#define IS_SMBUS_TRANSFER_MODE(MODE) (((MODE) == SMBUS_RELOAD_MODE) || \
614 ((MODE) == SMBUS_AUTOEND_MODE) || \
615 ((MODE) == SMBUS_SOFTEND_MODE) || \
616 ((MODE) == SMBUS_SENDPEC_MODE) || \
617 ((MODE) == (SMBUS_RELOAD_MODE | SMBUS_SENDPEC_MODE)) || \
618 ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) || \
619 ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_RELOAD_MODE)) || \
620 ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE | \
621 SMBUS_RELOAD_MODE )))
622
623
624#define IS_SMBUS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == SMBUS_GENERATE_STOP) || \
625 ((REQUEST) == SMBUS_GENERATE_START_READ) || \
626 ((REQUEST) == SMBUS_GENERATE_START_WRITE) || \
627 ((REQUEST) == SMBUS_NO_STARTSTOP))
628
629
630#define IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST) (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) || \
631 ((REQUEST) == SMBUS_FIRST_FRAME) || \
632 ((REQUEST) == SMBUS_NEXT_FRAME) || \
633 ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || \
634 ((REQUEST) == SMBUS_LAST_FRAME_NO_PEC) || \
635 ((REQUEST) == SMBUS_FIRST_FRAME_WITH_PEC) || \
636 ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || \
637 ((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC))
638
639#define IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == SMBUS_OTHER_FRAME_NO_PEC) || \
640 ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC) || \
641 ((REQUEST) == SMBUS_OTHER_FRAME_WITH_PEC) || \
642 ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC))
643
644#define SMBUS_RESET_CR1(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= \
645 (uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | I2C_CR1_SMBDEN | \
646 I2C_CR1_PECEN)))
647#define SMBUS_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= \
648 (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | \
649 I2C_CR2_NBYTES | I2C_CR2_RELOAD | \
650 I2C_CR2_RD_WRN)))
651
652#define SMBUS_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == SMBUS_ADDRESSINGMODE_7BIT) ? \
653 (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \
654 (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & \
655 (~I2C_CR2_RD_WRN)) : \
656 (uint32_t)((((uint32_t)(__ADDRESS__) & \
657 (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | \
658 (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))
659
660#define SMBUS_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 17U)
661#define SMBUS_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U)
662#define SMBUS_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
663#define SMBUS_GET_PEC_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_PECBYTE)
664#define SMBUS_GET_ALERT_ENABLED(__HANDLE__) ((__HANDLE__)->Instance->CR1 & I2C_CR1_ALERTEN)
665
666#define SMBUS_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & SMBUS_FLAG_MASK)) == \
667 ((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET)
668#define SMBUS_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)
669
670#define IS_SMBUS_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU)
671#define IS_SMBUS_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU)
672
677/* Include SMBUS HAL Extended module */
678#include "stm32h7xx_hal_smbus_ex.h"
679
680/* Exported functions --------------------------------------------------------*/
689/* Initialization and de-initialization functions ****************************/
690HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus);
691HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus);
692void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus);
693void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus);
694HAL_StatusTypeDef HAL_SMBUS_ConfigAnalogFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t AnalogFilter);
695HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t DigitalFilter);
696
697/* Callbacks Register/UnRegister functions ***********************************/
698#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
699HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus,
700 HAL_SMBUS_CallbackIDTypeDef CallbackID,
701 pSMBUS_CallbackTypeDef pCallback);
702HAL_StatusTypeDef HAL_SMBUS_UnRegisterCallback(SMBUS_HandleTypeDef *hsmbus,
703 HAL_SMBUS_CallbackIDTypeDef CallbackID);
704
705HAL_StatusTypeDef HAL_SMBUS_RegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus,
706 pSMBUS_AddrCallbackTypeDef pCallback);
707HAL_StatusTypeDef HAL_SMBUS_UnRegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus);
708#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
717/* IO operation functions *****************************************************/
721/******* Blocking mode: Polling */
722HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials,
723 uint32_t Timeout);
731/******* Non-Blocking mode: Interrupt */
732HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress,
733 uint8_t *pData, uint16_t Size, uint32_t XferOptions);
734HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress,
735 uint8_t *pData, uint16_t Size, uint32_t XferOptions);
736HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress);
737HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size,
738 uint32_t XferOptions);
739HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size,
740 uint32_t XferOptions);
741
742HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus);
743HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus);
744HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT(SMBUS_HandleTypeDef *hsmbus);
745HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus);
753/******* SMBUS IRQHandler and Callbacks used in non blocking modes (Interrupt) */
754void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus);
755void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus);
756void HAL_SMBUS_MasterTxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
757void HAL_SMBUS_MasterRxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
758void HAL_SMBUS_SlaveTxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
759void HAL_SMBUS_SlaveRxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
760void HAL_SMBUS_AddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode);
761void HAL_SMBUS_ListenCpltCallback(SMBUS_HandleTypeDef *hsmbus);
762void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus);
763
772/* Peripheral State and Errors functions **************************************************/
773uint32_t HAL_SMBUS_GetState(const SMBUS_HandleTypeDef *hsmbus);
774uint32_t HAL_SMBUS_GetError(const SMBUS_HandleTypeDef *hsmbus);
775
784/* Private Functions ---------------------------------------------------------*/
789/* Private functions are defined in stm32h7xx_hal_smbus.c file */
806#ifdef __cplusplus
807}
808#endif
809
810
811#endif /* STM32H7xx_HAL_SMBUS_H */
__IO
#define __IO
Definition: core_cm4.h:239
stm32h7xx_hal_def.h
This file contains HAL common defines, enumeration, macros and structures definitions.
HAL_StatusTypeDef
HAL_StatusTypeDef
HAL Status structures definition.
Definition: stm32h7xx_hal_def.h:47
HAL_LockTypeDef
HAL_LockTypeDef
HAL Lock structures definition.
Definition: stm32h7xx_hal_def.h:58
stm32h7xx_hal_smbus_ex.h
Header file of SMBUS HAL Extended module.
I2C_TypeDef
Inter-integrated Circuit Interface.
Definition: stm32h723xx.h:1133
SMBUS_HandleTypeDef
Definition: stm32h7xx_hal_smbus.h:143
SMBUS_HandleTypeDef::PreviousState
__IO uint32_t PreviousState
Definition: stm32h7xx_hal_smbus.h:156
SMBUS_HandleTypeDef::ErrorCode
__IO uint32_t ErrorCode
Definition: stm32h7xx_hal_smbus.h:162
SMBUS_HandleTypeDef::Init
SMBUS_InitTypeDef Init
Definition: stm32h7xx_hal_smbus.h:146
SMBUS_HandleTypeDef::XferSize
uint16_t XferSize
Definition: stm32h7xx_hal_smbus.h:150
SMBUS_HandleTypeDef::XferOptions
__IO uint32_t XferOptions
Definition: stm32h7xx_hal_smbus.h:154
SMBUS_HandleTypeDef::State
__IO uint32_t State
Definition: stm32h7xx_hal_smbus.h:160
SMBUS_HandleTypeDef::pBuffPtr
uint8_t * pBuffPtr
Definition: stm32h7xx_hal_smbus.h:148
SMBUS_HandleTypeDef::Lock
HAL_LockTypeDef Lock
Definition: stm32h7xx_hal_smbus.h:158
SMBUS_HandleTypeDef::XferCount
__IO uint16_t XferCount
Definition: stm32h7xx_hal_smbus.h:152
SMBUS_HandleTypeDef::Instance
I2C_TypeDef * Instance
Definition: stm32h7xx_hal_smbus.h:144
SMBUS_InitTypeDef
Definition: stm32h7xx_hal_smbus.h:50
SMBUS_InitTypeDef::OwnAddress2Masks
uint32_t OwnAddress2Masks
Definition: stm32h7xx_hal_smbus.h:69
SMBUS_InitTypeDef::Timing
uint32_t Timing
Definition: stm32h7xx_hal_smbus.h:51
SMBUS_InitTypeDef::PacketErrorCheckMode
uint32_t PacketErrorCheckMode
Definition: stm32h7xx_hal_smbus.h:79
SMBUS_InitTypeDef::AddressingMode
uint32_t AddressingMode
Definition: stm32h7xx_hal_smbus.h:60
SMBUS_InitTypeDef::SMBusTimeout
uint32_t SMBusTimeout
Definition: stm32h7xx_hal_smbus.h:85
SMBUS_InitTypeDef::AnalogFilter
uint32_t AnalogFilter
Definition: stm32h7xx_hal_smbus.h:54
SMBUS_InitTypeDef::OwnAddress2
uint32_t OwnAddress2
Definition: stm32h7xx_hal_smbus.h:66
SMBUS_InitTypeDef::GeneralCallMode
uint32_t GeneralCallMode
Definition: stm32h7xx_hal_smbus.h:73
SMBUS_InitTypeDef::DualAddressMode
uint32_t DualAddressMode
Definition: stm32h7xx_hal_smbus.h:63
SMBUS_InitTypeDef::PeripheralMode
uint32_t PeripheralMode
Definition: stm32h7xx_hal_smbus.h:82
SMBUS_InitTypeDef::NoStretchMode
uint32_t NoStretchMode
Definition: stm32h7xx_hal_smbus.h:76
SMBUS_InitTypeDef::OwnAddress1
uint32_t OwnAddress1
Definition: stm32h7xx_hal_smbus.h:57
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