RTEMS 6.1-rc5
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stm32h7xx_hal_pwr.h
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1
19/* Define to prevent recursive inclusion -------------------------------------*/
20#ifndef STM32H7xx_HAL_PWR_H
21#define STM32H7xx_HAL_PWR_H
22
23#ifdef __cplusplus
24 extern "C" {
25#endif /* __cplusplus */
26
27/* Includes ------------------------------------------------------------------*/
28#include "stm32h7xx_hal_def.h"
29
38/* Exported types ------------------------------------------------------------*/
39
48typedef struct
49{
50 uint32_t PVDLevel;
55 uint32_t Mode;
59}PWR_PVDTypeDef;
60
65/* Exported constants --------------------------------------------------------*/
75#define PWR_PVDLEVEL_0 PWR_CR1_PLS_LEV0
77#define PWR_PVDLEVEL_1 PWR_CR1_PLS_LEV1
79#define PWR_PVDLEVEL_2 PWR_CR1_PLS_LEV2
81#define PWR_PVDLEVEL_3 PWR_CR1_PLS_LEV3
83#define PWR_PVDLEVEL_4 PWR_CR1_PLS_LEV4
85#define PWR_PVDLEVEL_5 PWR_CR1_PLS_LEV5
87#define PWR_PVDLEVEL_6 PWR_CR1_PLS_LEV6
89#define PWR_PVDLEVEL_7 PWR_CR1_PLS_LEV7
99#define PWR_PVD_MODE_NORMAL (0x00000000U)
100#define PWR_PVD_MODE_IT_RISING (0x00010001U)
101#define PWR_PVD_MODE_IT_FALLING (0x00010002U)
102#define PWR_PVD_MODE_IT_RISING_FALLING (0x00010003U)
103#define PWR_PVD_MODE_EVENT_RISING (0x00020001U)
104#define PWR_PVD_MODE_EVENT_FALLING (0x00020002U)
105#define PWR_PVD_MODE_EVENT_RISING_FALLING (0x00020003U)
114#define PWR_MAINREGULATOR_ON (0U)
115#define PWR_LOWPOWERREGULATOR_ON PWR_CR1_LPDS
124#define PWR_SLEEPENTRY_WFI (0x01U)
125#define PWR_SLEEPENTRY_WFE (0x02U)
134#define PWR_STOPENTRY_WFI (0x01U)
135#define PWR_STOPENTRY_WFE (0x02U)
144#if defined(PWR_SRDCR_VOS)
145#define PWR_REGULATOR_VOLTAGE_SCALE0 (PWR_SRDCR_VOS_1 | PWR_SRDCR_VOS_0)
146#define PWR_REGULATOR_VOLTAGE_SCALE1 (PWR_SRDCR_VOS_1)
147#define PWR_REGULATOR_VOLTAGE_SCALE2 (PWR_SRDCR_VOS_0)
148#define PWR_REGULATOR_VOLTAGE_SCALE3 (0U)
149#else
150#define PWR_REGULATOR_VOLTAGE_SCALE0 (0U)
151#define PWR_REGULATOR_VOLTAGE_SCALE1 (PWR_D3CR_VOS_1 | PWR_D3CR_VOS_0)
152#define PWR_REGULATOR_VOLTAGE_SCALE2 (PWR_D3CR_VOS_1)
153#define PWR_REGULATOR_VOLTAGE_SCALE3 (PWR_D3CR_VOS_0)
154#endif /* PWR_SRDCR_VOS */
163/* PWR CPU flag */
164#define PWR_FLAG_STOP (0x01U)
165#if defined (PWR_CPUCR_SBF_D2)
166#define PWR_FLAG_SB_D1 (0x02U)
167#define PWR_FLAG_SB_D2 (0x03U)
168#endif /* defined (PWR_CPUCR_SBF_D2) */
169#define PWR_FLAG_SB (0x04U)
170#if defined (DUAL_CORE)
171#define PWR_FLAG_CPU_HOLD (0x05U)
172#define PWR_FLAG_CPU2_HOLD (0x06U)
173#define PWR_FLAG2_STOP (0x07U)
174#define PWR_FLAG2_SB_D1 (0x08U)
175#define PWR_FLAG2_SB_D2 (0x09U)
176#define PWR_FLAG2_SB (0x0AU)
177#endif /* defined (DUAL_CORE) */
178#define PWR_FLAG_PVDO (0x0BU)
179#define PWR_FLAG_AVDO (0x0CU)
180#define PWR_FLAG_ACTVOSRDY (0x0DU)
181#define PWR_FLAG_ACTVOS (0x0EU)
182#define PWR_FLAG_BRR (0x0FU)
183#define PWR_FLAG_VOSRDY (0x10U)
184#if defined (SMPS)
185#define PWR_FLAG_SMPSEXTRDY (0x11U)
186#else
187#define PWR_FLAG_SCUEN (0x11U)
188#endif /* defined (SMPS) */
189#if defined (PWR_CSR1_MMCVDO)
190#define PWR_FLAG_MMCVDO (0x12U)
191#endif /* defined (PWR_CSR1_MMCVDO) */
192#define PWR_FLAG_USB33RDY (0x13U)
193#define PWR_FLAG_TEMPH (0x14U)
194#define PWR_FLAG_TEMPL (0x15U)
195#define PWR_FLAG_VBATH (0x16U)
196#define PWR_FLAG_VBATL (0x17U)
197
198/* PWR Wake up flag */
199#define PWR_FLAG_WKUP1 PWR_WKUPCR_WKUPC1
200#define PWR_FLAG_WKUP2 PWR_WKUPCR_WKUPC2
201#define PWR_FLAG_WKUP3 PWR_WKUPCR_WKUPC3
202#define PWR_FLAG_WKUP4 PWR_WKUPCR_WKUPC4
203#define PWR_FLAG_WKUP5 PWR_WKUPCR_WKUPC5
204#define PWR_FLAG_WKUP6 PWR_WKUPCR_WKUPC6
213#define PWR_EWUP_MASK (0x0FFF3F3FU)
221/* Exported macro ------------------------------------------------------------*/
258#if defined (PWR_SRDCR_VOS) /* STM32H7Axxx and STM32H7Bxxx lines */
259#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) \
260do { \
261 __IO uint32_t tmpreg = 0x00; \
262 /* Configure the Voltage Scaling */ \
263 MODIFY_REG(PWR->SRDCR, PWR_SRDCR_VOS, (__REGULATOR__)); \
264 /* Delay after setting the voltage scaling */ \
265 tmpreg = READ_BIT(PWR->SRDCR, PWR_SRDCR_VOS); \
266 UNUSED(tmpreg); \
267} while(0)
268#else /* 3 power domains devices */
269#if defined(SYSCFG_PWRCR_ODEN) /* STM32H74xxx and STM32H75xxx lines */
270#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) \
271do { \
272 __IO uint32_t tmpreg = 0x00; \
273 /* Check the voltage scaling to be configured */ \
274 if((__REGULATOR__) == PWR_REGULATOR_VOLTAGE_SCALE0) \
275 { \
276 /* Configure the Voltage Scaling 1 */ \
277 MODIFY_REG(PWR->D3CR, PWR_D3CR_VOS, PWR_REGULATOR_VOLTAGE_SCALE1); \
278 /* Delay after setting the voltage scaling */ \
279 tmpreg = READ_BIT(PWR->D3CR, PWR_D3CR_VOS); \
280 /* Enable the PWR overdrive */ \
281 SET_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN); \
282 /* Delay after setting the syscfg boost setting */ \
283 tmpreg = READ_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN); \
284 } \
285 else \
286 { \
287 /* Disable the PWR overdrive */ \
288 CLEAR_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN); \
289 /* Delay after setting the syscfg boost setting */ \
290 tmpreg = READ_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN); \
291 /* Configure the Voltage Scaling x */ \
292 MODIFY_REG(PWR->D3CR, PWR_D3CR_VOS, (__REGULATOR__)); \
293 /* Delay after setting the voltage scaling */ \
294 tmpreg = READ_BIT(PWR->D3CR, PWR_D3CR_VOS); \
295 } \
296 UNUSED(tmpreg); \
297} while(0)
298#else /* STM32H72xxx and STM32H73xxx lines */
299#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) \
300do { \
301 __IO uint32_t tmpreg = 0x00; \
302 /* Configure the Voltage Scaling */ \
303 MODIFY_REG (PWR->D3CR, PWR_D3CR_VOS, (__REGULATOR__)); \
304 /* Delay after setting the voltage scaling */ \
305 tmpreg = READ_BIT(PWR->D3CR, PWR_D3CR_VOS); \
306 UNUSED(tmpreg); \
307} while(0)
308#endif /* defined(SYSCFG_PWRCR_ODEN) */
309#endif /* defined (PWR_SRDCR_VOS) */
310
388#if defined (DUAL_CORE) /* Dual core lines */
389#define __HAL_PWR_GET_FLAG(__FLAG__) \
390(((__FLAG__) == PWR_FLAG_PVDO) ? ((PWR->CSR1 & PWR_CSR1_PVDO) == PWR_CSR1_PVDO) :\
391 ((__FLAG__) == PWR_FLAG_AVDO) ? ((PWR->CSR1 & PWR_CSR1_AVDO) == PWR_CSR1_AVDO) :\
392 ((__FLAG__) == PWR_FLAG_ACTVOSRDY) ? ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == PWR_CSR1_ACTVOSRDY) :\
393 ((__FLAG__) == PWR_FLAG_VOSRDY) ? ((PWR->D3CR & PWR_D3CR_VOSRDY) == PWR_D3CR_VOSRDY) :\
394 ((__FLAG__) == PWR_FLAG_SMPSEXTRDY) ? ((PWR->CR3 & PWR_CR3_SMPSEXTRDY) == PWR_CR3_SMPSEXTRDY) :\
395 ((__FLAG__) == PWR_FLAG_BRR) ? ((PWR->CR2 & PWR_CR2_BRRDY) == PWR_CR2_BRRDY) :\
396 ((__FLAG__) == PWR_FLAG_CPU_HOLD) ? ((PWR->CPU2CR & PWR_CPU2CR_HOLD1F) == PWR_CPU2CR_HOLD1F) :\
397 ((__FLAG__) == PWR_FLAG_CPU2_HOLD) ? ((PWR->CPUCR & PWR_CPUCR_HOLD2F) == PWR_CPUCR_HOLD2F) :\
398 ((__FLAG__) == PWR_FLAG_SB) ? ((PWR->CPUCR & PWR_CPUCR_SBF) == PWR_CPUCR_SBF) :\
399 ((__FLAG__) == PWR_FLAG2_SB) ? ((PWR->CPU2CR & PWR_CPU2CR_SBF) == PWR_CPU2CR_SBF) :\
400 ((__FLAG__) == PWR_FLAG_STOP) ? ((PWR->CPUCR & PWR_CPUCR_STOPF) == PWR_CPUCR_STOPF) :\
401 ((__FLAG__) == PWR_FLAG2_STOP) ? ((PWR->CPU2CR & PWR_CPU2CR_STOPF) == PWR_CPU2CR_STOPF) :\
402 ((__FLAG__) == PWR_FLAG_SB_D1) ? ((PWR->CPUCR & PWR_CPUCR_SBF_D1) == PWR_CPUCR_SBF_D1) :\
403 ((__FLAG__) == PWR_FLAG2_SB_D1) ? ((PWR->CPU2CR & PWR_CPU2CR_SBF_D1) == PWR_CPU2CR_SBF_D1) :\
404 ((__FLAG__) == PWR_FLAG_SB_D2) ? ((PWR->CPUCR & PWR_CPUCR_SBF_D2) == PWR_CPUCR_SBF_D2) :\
405 ((__FLAG__) == PWR_FLAG2_SB_D2) ? ((PWR->CPU2CR & PWR_CPU2CR_SBF_D2) == PWR_CPU2CR_SBF_D2) :\
406 ((__FLAG__) == PWR_FLAG_USB33RDY) ? ((PWR->CR3 & PWR_CR3_USB33RDY) == PWR_CR3_USB33RDY) :\
407 ((__FLAG__) == PWR_FLAG_TEMPH) ? ((PWR->CR2 & PWR_CR2_TEMPH) == PWR_CR2_TEMPH) :\
408 ((__FLAG__) == PWR_FLAG_TEMPL) ? ((PWR->CR2 & PWR_CR2_TEMPL) == PWR_CR2_TEMPL) :\
409 ((__FLAG__) == PWR_FLAG_VBATH) ? ((PWR->CR2 & PWR_CR2_VBATH) == PWR_CR2_VBATH) :\
410 ((PWR->CR2 & PWR_CR2_VBATL) == PWR_CR2_VBATL))
411#else /* Single core lines */
412#if defined (PWR_CPUCR_SBF_D2) /* STM32H72x, STM32H73x, STM32H74x and STM32H75x lines */
413#if defined (SMPS) /* STM32H725 and STM32H735 lines */
414#define __HAL_PWR_GET_FLAG(__FLAG__) \
415(((__FLAG__) == PWR_FLAG_PVDO) ? ((PWR->CSR1 & PWR_CSR1_PVDO) == PWR_CSR1_PVDO) :\
416 ((__FLAG__) == PWR_FLAG_AVDO) ? ((PWR->CSR1 & PWR_CSR1_AVDO) == PWR_CSR1_AVDO) :\
417 ((__FLAG__) == PWR_FLAG_ACTVOSRDY) ? ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == PWR_CSR1_ACTVOSRDY) :\
418 ((__FLAG__) == PWR_FLAG_VOSRDY) ? ((PWR->D3CR & PWR_D3CR_VOSRDY) == PWR_D3CR_VOSRDY) :\
419 ((__FLAG__) == PWR_FLAG_SMPSEXTRDY) ? ((PWR->CR3 & PWR_FLAG_SMPSEXTRDY) == PWR_FLAG_SMPSEXTRDY) :\
420 ((__FLAG__) == PWR_FLAG_BRR) ? ((PWR->CR2 & PWR_CR2_BRRDY) == PWR_CR2_BRRDY) :\
421 ((__FLAG__) == PWR_FLAG_SB) ? ((PWR->CPUCR & PWR_CPUCR_SBF) == PWR_CPUCR_SBF) :\
422 ((__FLAG__) == PWR_FLAG_STOP) ? ((PWR->CPUCR & PWR_CPUCR_STOPF) == PWR_CPUCR_STOPF) :\
423 ((__FLAG__) == PWR_FLAG_SB_D1) ? ((PWR->CPUCR & PWR_CPUCR_SBF_D1) == PWR_CPUCR_SBF_D1) :\
424 ((__FLAG__) == PWR_FLAG_SB_D2) ? ((PWR->CPUCR & PWR_CPUCR_SBF_D2) == PWR_CPUCR_SBF_D2) :\
425 ((__FLAG__) == PWR_FLAG_USB33RDY) ? ((PWR->CR3 & PWR_CR3_USB33RDY) == PWR_CR3_USB33RDY) :\
426 ((__FLAG__) == PWR_FLAG_TEMPH) ? ((PWR->CR2 & PWR_CR2_TEMPH) == PWR_CR2_TEMPH) :\
427 ((__FLAG__) == PWR_FLAG_TEMPL) ? ((PWR->CR2 & PWR_CR2_TEMPL) == PWR_CR2_TEMPL) :\
428 ((__FLAG__) == PWR_FLAG_VBATH) ? ((PWR->CR2 & PWR_CR2_VBATH) == PWR_CR2_VBATH) :\
429 ((PWR->CR2 & PWR_CR2_VBATL) == PWR_CR2_VBATL))
430#else /* STM32H723, STM32H733, STM32H742, STM32H743, STM32H750 and STM32H753 lines */
431#define __HAL_PWR_GET_FLAG(__FLAG__) \
432(((__FLAG__) == PWR_FLAG_PVDO) ? ((PWR->CSR1 & PWR_CSR1_PVDO) == PWR_CSR1_PVDO) :\
433 ((__FLAG__) == PWR_FLAG_AVDO) ? ((PWR->CSR1 & PWR_CSR1_AVDO) == PWR_CSR1_AVDO) :\
434 ((__FLAG__) == PWR_FLAG_ACTVOSRDY) ? ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == PWR_CSR1_ACTVOSRDY) :\
435 ((__FLAG__) == PWR_FLAG_VOSRDY) ? ((PWR->D3CR & PWR_D3CR_VOSRDY) == PWR_D3CR_VOSRDY) :\
436 ((__FLAG__) == PWR_FLAG_SCUEN) ? ((PWR->CR3 & PWR_CR3_SCUEN) == PWR_CR3_SCUEN) :\
437 ((__FLAG__) == PWR_FLAG_BRR) ? ((PWR->CR2 & PWR_CR2_BRRDY) == PWR_CR2_BRRDY) :\
438 ((__FLAG__) == PWR_FLAG_SB) ? ((PWR->CPUCR & PWR_CPUCR_SBF) == PWR_CPUCR_SBF) :\
439 ((__FLAG__) == PWR_FLAG_STOP) ? ((PWR->CPUCR & PWR_CPUCR_STOPF) == PWR_CPUCR_STOPF) :\
440 ((__FLAG__) == PWR_FLAG_SB_D1) ? ((PWR->CPUCR & PWR_CPUCR_SBF_D1) == PWR_CPUCR_SBF_D1) :\
441 ((__FLAG__) == PWR_FLAG_SB_D2) ? ((PWR->CPUCR & PWR_CPUCR_SBF_D2) == PWR_CPUCR_SBF_D2) :\
442 ((__FLAG__) == PWR_FLAG_USB33RDY) ? ((PWR->CR3 & PWR_CR3_USB33RDY) == PWR_CR3_USB33RDY) :\
443 ((__FLAG__) == PWR_FLAG_TEMPH) ? ((PWR->CR2 & PWR_CR2_TEMPH) == PWR_CR2_TEMPH) :\
444 ((__FLAG__) == PWR_FLAG_TEMPL) ? ((PWR->CR2 & PWR_CR2_TEMPL) == PWR_CR2_TEMPL) :\
445 ((__FLAG__) == PWR_FLAG_VBATH) ? ((PWR->CR2 & PWR_CR2_VBATH) == PWR_CR2_VBATH) :\
446 ((PWR->CR2 & PWR_CR2_VBATL) == PWR_CR2_VBATL))
447#endif /* defined (SMPS) */
448#else /* STM32H7Axxx and STM32H7Bxxx lines */
449#if defined (SMPS) /* STM32H7AxxQ and STM32H7BxxQ lines */
450#define __HAL_PWR_GET_FLAG(__FLAG__) \
451(((__FLAG__) == PWR_FLAG_PVDO) ? ((PWR->CSR1 & PWR_CSR1_PVDO) == PWR_CSR1_PVDO) :\
452 ((__FLAG__) == PWR_FLAG_AVDO) ? ((PWR->CSR1 & PWR_CSR1_AVDO) == PWR_CSR1_AVDO) :\
453 ((__FLAG__) == PWR_FLAG_ACTVOSRDY) ? ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == PWR_CSR1_ACTVOSRDY) :\
454 ((__FLAG__) == PWR_FLAG_BRR) ? ((PWR->CR2 & PWR_CR2_BRRDY) == PWR_CR2_BRRDY) :\
455 ((__FLAG__) == PWR_FLAG_VOSRDY) ? ((PWR->SRDCR & PWR_SRDCR_VOSRDY) == PWR_SRDCR_VOSRDY) :\
456 ((__FLAG__) == PWR_FLAG_STOP) ? ((PWR->CPUCR & PWR_CPUCR_STOPF) == PWR_CPUCR_STOPF) :\
457 ((__FLAG__) == PWR_FLAG_SB) ? ((PWR->CPUCR & PWR_CPUCR_SBF) == PWR_CPUCR_SBF) :\
458 ((__FLAG__) == PWR_FLAG_MMCVDO) ? ((PWR->CSR1 & PWR_CSR1_MMCVDO) == PWR_CSR1_MMCVDO) :\
459 ((__FLAG__) == PWR_FLAG_SMPSEXTRDY) ? ((PWR->CR3 & PWR_CR3_SMPSEXTRDY) == PWR_CR3_SMPSEXTRDY) :\
460 ((__FLAG__) == PWR_FLAG_USB33RDY) ? ((PWR->CR3 & PWR_CR3_USB33RDY) == PWR_CR3_USB33RDY) :\
461 ((__FLAG__) == PWR_FLAG_TEMPH) ? ((PWR->CR2 & PWR_CR2_TEMPH) == PWR_CR2_TEMPH) :\
462 ((__FLAG__) == PWR_FLAG_TEMPL) ? ((PWR->CR2 & PWR_CR2_TEMPL) == PWR_CR2_TEMPL) :\
463 ((__FLAG__) == PWR_FLAG_VBATH) ? ((PWR->CR2 & PWR_CR2_VBATH) == PWR_CR2_VBATH) :\
464 ((PWR->CR2 & PWR_CR2_VBATL) == PWR_CR2_VBATL))
465#else /* STM32H7Axx and STM32H7Bxx lines */
466#define __HAL_PWR_GET_FLAG(__FLAG__) \
467(((__FLAG__) == PWR_FLAG_PVDO) ? ((PWR->CSR1 & PWR_CSR1_PVDO) == PWR_CSR1_PVDO) :\
468 ((__FLAG__) == PWR_FLAG_AVDO) ? ((PWR->CSR1 & PWR_CSR1_AVDO) == PWR_CSR1_AVDO) :\
469 ((__FLAG__) == PWR_FLAG_ACTVOSRDY) ? ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == PWR_CSR1_ACTVOSRDY) :\
470 ((__FLAG__) == PWR_FLAG_BRR) ? ((PWR->CR2 & PWR_CR2_BRRDY) == PWR_CR2_BRRDY) :\
471 ((__FLAG__) == PWR_FLAG_VOSRDY) ? ((PWR->SRDCR & PWR_SRDCR_VOSRDY) == PWR_SRDCR_VOSRDY) :\
472 ((__FLAG__) == PWR_FLAG_SCUEN) ? ((PWR->CR3 & PWR_CR3_SCUEN) == PWR_CR3_SCUEN) :\
473 ((__FLAG__) == PWR_FLAG_STOP) ? ((PWR->CPUCR & PWR_CPUCR_STOPF) == PWR_CPUCR_STOPF) :\
474 ((__FLAG__) == PWR_FLAG_SB) ? ((PWR->CPUCR & PWR_CPUCR_SBF) == PWR_CPUCR_SBF) :\
475 ((__FLAG__) == PWR_FLAG_MMCVDO) ? ((PWR->CSR1 & PWR_CSR1_MMCVDO) == PWR_CSR1_MMCVDO) :\
476 ((__FLAG__) == PWR_FLAG_USB33RDY) ? ((PWR->CR3 & PWR_CR3_USB33RDY) == PWR_CR3_USB33RDY) :\
477 ((__FLAG__) == PWR_FLAG_TEMPH) ? ((PWR->CR2 & PWR_CR2_TEMPH) == PWR_CR2_TEMPH) :\
478 ((__FLAG__) == PWR_FLAG_TEMPL) ? ((PWR->CR2 & PWR_CR2_TEMPL) == PWR_CR2_TEMPL) :\
479 ((__FLAG__) == PWR_FLAG_VBATH) ? ((PWR->CR2 & PWR_CR2_VBATH) == PWR_CR2_VBATH) :\
480 ((PWR->CR2 & PWR_CR2_VBATL) == PWR_CR2_VBATL))
481#endif /* SMPS */
482#endif /* PWR_CPUCR_SBF_D2 */
483#endif /* DUAL_CORE */
484
498#define __HAL_PWR_GET_WAKEUPFLAG(__FLAG__) ((PWR->WKUPFR & (__FLAG__)) ? 0 : 1)
499
500#if defined (DUAL_CORE)
511#define __HAL_PWR_CLEAR_FLAG(__FLAG__) \
512do { \
513 SET_BIT(PWR->CPUCR, PWR_CPUCR_CSSF); \
514 SET_BIT(PWR->CPU2CR, PWR_CPU2CR_CSSF); \
515} while(0)
516#else
527#define __HAL_PWR_CLEAR_FLAG(__FLAG__) SET_BIT(PWR->CPUCR, PWR_CPUCR_CSSF)
528#endif /* defined (DUAL_CORE) */
529
543#define __HAL_PWR_CLEAR_WAKEUPFLAG(__FLAG__) SET_BIT(PWR->WKUPCR, (__FLAG__))
544
549#define __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD)
550
551#if defined (DUAL_CORE)
556#define __HAL_PWR_PVD_EXTID2_ENABLE_IT() SET_BIT(EXTI_D2->IMR1, PWR_EXTI_LINE_PVD)
557#endif /* defined (DUAL_CORE) */
558
563#define __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD)
564
565#if defined (DUAL_CORE)
570#define __HAL_PWR_PVD_EXTID2_DISABLE_IT() CLEAR_BIT(EXTI_D2->IMR1, PWR_EXTI_LINE_PVD)
571#endif /* defined (DUAL_CORE) */
572
577#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, PWR_EXTI_LINE_PVD)
578
579#if defined (DUAL_CORE)
584#define __HAL_PWR_PVD_EXTID2_ENABLE_EVENT() SET_BIT(EXTI_D2->EMR1, PWR_EXTI_LINE_PVD)
585#endif /* defined (DUAL_CORE) */
586
591#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, PWR_EXTI_LINE_PVD)
592
593#if defined (DUAL_CORE)
598#define __HAL_PWR_PVD_EXTID2_DISABLE_EVENT() CLEAR_BIT(EXTI_D2->EMR1, PWR_EXTI_LINE_PVD)
599#endif /* defined (DUAL_CORE) */
600
605#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)
606
611#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)
612
617#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)
618
623#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)
624
629#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() \
630do { \
631 __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); \
632 __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); \
633} while(0);
634
639#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() \
640do { \
641 __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \
642 __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \
643} while(0);
644
649#define __HAL_PWR_PVD_EXTI_GET_FLAG() ((READ_BIT(EXTI->PR1, PWR_EXTI_LINE_PVD) == PWR_EXTI_LINE_PVD) ? 1UL : 0UL)
650
651#if defined (DUAL_CORE)
656#define __HAL_PWR_PVD_EXTID2_GET_FLAG() ((READ_BIT(EXTI_D2->PR1, PWR_EXTI_LINE_PVD) == PWR_EXTI_LINE_PVD) ? 1UL : 0UL)
657#endif /* defined (DUAL_CORE) */
658
663#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() SET_BIT(EXTI->PR1, PWR_EXTI_LINE_PVD)
664
665#if defined (DUAL_CORE)
670#define __HAL_PWR_PVD_EXTID2_CLEAR_FLAG() SET_BIT(EXTI_D2->PR1, PWR_EXTI_LINE_PVD)
671#endif /* defined (DUAL_CORE) */
672
677#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_PVD)
682/* Include PWR HAL Extension module */
683#include "stm32h7xx_hal_pwr_ex.h"
684
685/* Exported functions --------------------------------------------------------*/
693/* Initialization and de-initialization functions *****************************/
694void HAL_PWR_DeInit (void);
695void HAL_PWR_EnableBkUpAccess (void);
696void HAL_PWR_DisableBkUpAccess (void);
704/* Peripheral Control functions **********************************************/
705/* PVD configuration */
706void HAL_PWR_ConfigPVD (PWR_PVDTypeDef *sConfigPVD);
707void HAL_PWR_EnablePVD (void);
708void HAL_PWR_DisablePVD (void);
709
710/* WakeUp pins configuration */
711void HAL_PWR_EnableWakeUpPin (uint32_t WakeUpPinPolarity);
712void HAL_PWR_DisableWakeUpPin (uint32_t WakeUpPinx);
713
714/* Low Power modes entry */
715void HAL_PWR_EnterSTOPMode (uint32_t Regulator, uint8_t STOPEntry);
716void HAL_PWR_EnterSLEEPMode (uint32_t Regulator, uint8_t SLEEPEntry);
717void HAL_PWR_EnterSTANDBYMode (void);
718
719/* Power PVD IRQ Handler */
720void HAL_PWR_PVD_IRQHandler (void);
721void HAL_PWR_PVDCallback (void);
722
723/* Cortex System Control functions *******************************************/
724void HAL_PWR_EnableSleepOnExit (void);
725void HAL_PWR_DisableSleepOnExit (void);
726void HAL_PWR_EnableSEVOnPend (void);
727void HAL_PWR_DisableSEVOnPend (void);
736/* Private types -------------------------------------------------------------*/
737/* Private variables ---------------------------------------------------------*/
738/* Private constants ---------------------------------------------------------*/
748#define PWR_EXTI_LINE_PVD EXTI_IMR1_IM16
757/* Private macros ------------------------------------------------------------*/
767/* Check PVD level parameter */
768#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) ||\
769 ((LEVEL) == PWR_PVDLEVEL_1) ||\
770 ((LEVEL) == PWR_PVDLEVEL_2) ||\
771 ((LEVEL) == PWR_PVDLEVEL_3) ||\
772 ((LEVEL) == PWR_PVDLEVEL_4) ||\
773 ((LEVEL) == PWR_PVDLEVEL_5) ||\
774 ((LEVEL) == PWR_PVDLEVEL_6) ||\
775 ((LEVEL) == PWR_PVDLEVEL_7))
776
777/* Check PVD mode parameter */
778#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING) ||\
779 ((MODE) == PWR_PVD_MODE_IT_FALLING) ||\
780 ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) ||\
781 ((MODE) == PWR_PVD_MODE_EVENT_RISING) ||\
782 ((MODE) == PWR_PVD_MODE_EVENT_FALLING) ||\
783 ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) ||\
784 ((MODE) == PWR_PVD_MODE_NORMAL))
785
786/* Check low power regulator parameter */
787#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) ||\
788 ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
789
790/* Check low power mode entry parameter */
791#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) ||\
792 ((ENTRY) == PWR_SLEEPENTRY_WFE))
793
794/* Check low power mode entry parameter */
795#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) ||\
796 ((ENTRY) == PWR_STOPENTRY_WFE))
797
798/* Check voltage scale level parameter */
799#define IS_PWR_REGULATOR_VOLTAGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE0) || \
800 ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \
801 ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE2) || \
802 ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE3))
819#ifdef __cplusplus
820}
821#endif /* __cplusplus */
822
823#endif /* STM32H7xx_HAL_PWR_H */
824
stm32h7xx_hal_def.h
This file contains HAL common defines, enumeration, macros and structures definitions.
stm32h7xx_hal_pwr_ex.h
Header file of PWR HAL Extension module.
PWR_PVDTypeDef
PWR PVD configuration structure definition.
Definition: stm32h7xx_hal_pwr.h:49
PWR_PVDTypeDef::PVDLevel
uint32_t PVDLevel
Definition: stm32h7xx_hal_pwr.h:50
PWR_PVDTypeDef::Mode
uint32_t Mode
Definition: stm32h7xx_hal_pwr.h:55
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