RTEMS 6.1-rc5
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stm32h7xx_hal_ospi.h
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1
19/* Define to prevent recursive inclusion -------------------------------------*/
20#ifndef STM32H7xx_HAL_OSPI_H
21#define STM32H7xx_HAL_OSPI_H
22
23#ifdef __cplusplus
24extern "C" {
25#endif
26
27/* Includes ------------------------------------------------------------------*/
28#include "stm32h7xx_hal_def.h"
29
30#if defined(OCTOSPI) || defined(OCTOSPI1) || defined(OCTOSPI2)
31
40/* Exported types ------------------------------------------------------------*/
49typedef struct
50{
51 uint32_t FifoThreshold;
55 uint32_t DualQuad;
58 uint32_t MemoryType;
60 uint32_t DeviceSize;
64 uint32_t ChipSelectHighTime;
67 uint32_t FreeRunningClock;
69 uint32_t ClockMode;
71 uint32_t WrapSize;
73 uint32_t ClockPrescaler;
76 uint32_t SampleShifting;
79 uint32_t DelayHoldQuarterCycle;
81 uint32_t ChipSelectBoundary;
84 uint32_t DelayBlockBypass;
87 uint32_t MaxTran;
91 uint32_t Refresh;
94} OSPI_InitTypeDef;
95
99#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
100typedef struct __OSPI_HandleTypeDef
101#else
102typedef struct
103#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */
104{
105 OCTOSPI_TypeDef *Instance;
106 OSPI_InitTypeDef Init;
107 uint8_t *pBuffPtr;
108 __IO uint32_t XferSize;
109 __IO uint32_t XferCount;
110 MDMA_HandleTypeDef *hmdma;
111 __IO uint32_t State;
112 __IO uint32_t ErrorCode;
113 uint32_t Timeout;
114#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
115 void (* ErrorCallback)(struct __OSPI_HandleTypeDef *hospi);
116 void (* AbortCpltCallback)(struct __OSPI_HandleTypeDef *hospi);
117 void (* FifoThresholdCallback)(struct __OSPI_HandleTypeDef *hospi);
118 void (* CmdCpltCallback)(struct __OSPI_HandleTypeDef *hospi);
119 void (* RxCpltCallback)(struct __OSPI_HandleTypeDef *hospi);
120 void (* TxCpltCallback)(struct __OSPI_HandleTypeDef *hospi);
121 void (* RxHalfCpltCallback)(struct __OSPI_HandleTypeDef *hospi);
122 void (* TxHalfCpltCallback)(struct __OSPI_HandleTypeDef *hospi);
123 void (* StatusMatchCallback)(struct __OSPI_HandleTypeDef *hospi);
124 void (* TimeOutCallback)(struct __OSPI_HandleTypeDef *hospi);
125
126 void (* MspInitCallback)(struct __OSPI_HandleTypeDef *hospi);
127 void (* MspDeInitCallback)(struct __OSPI_HandleTypeDef *hospi);
128#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */
129} OSPI_HandleTypeDef;
130
134typedef struct
135{
136 uint32_t OperationType;
140 uint32_t FlashId;
143 uint32_t Instruction;
145 uint32_t InstructionMode;
147 uint32_t InstructionSize;
149 uint32_t InstructionDtrMode;
151 uint32_t Address;
153 uint32_t AddressMode;
155 uint32_t AddressSize;
157 uint32_t AddressDtrMode;
159 uint32_t AlternateBytes;
161 uint32_t AlternateBytesMode;
163 uint32_t AlternateBytesSize;
165 uint32_t AlternateBytesDtrMode;
167 uint32_t DataMode;
169 uint32_t NbData;
172 uint32_t DataDtrMode;
174 uint32_t DummyCycles;
176 uint32_t DQSMode;
178 uint32_t SIOOMode;
180} OSPI_RegularCmdTypeDef;
181
185typedef struct
186{
187 uint32_t RWRecoveryTime;
189 uint32_t AccessTime;
191 uint32_t WriteZeroLatency;
193 uint32_t LatencyMode;
195} OSPI_HyperbusCfgTypeDef;
196
200typedef struct
201{
202 uint32_t AddressSpace;
204 uint32_t Address;
206 uint32_t AddressSize;
208 uint32_t NbData;
212 uint32_t DQSMode;
214} OSPI_HyperbusCmdTypeDef;
215
219typedef struct
220{
221 uint32_t Match;
223 uint32_t Mask;
225 uint32_t MatchMode;
227 uint32_t AutomaticStop;
229 uint32_t Interval;
231} OSPI_AutoPollingTypeDef;
232
236typedef struct
237{
238 uint32_t TimeOutActivation;
240 uint32_t TimeOutPeriod;
242} OSPI_MemoryMappedTypeDef;
243
247typedef struct
248{
249 uint32_t ClkPort;
251 uint32_t DQSPort;
253 uint32_t NCSPort;
255 uint32_t IOLowPort;
257 uint32_t IOHighPort;
259 uint32_t Req2AckTime;
262} OSPIM_CfgTypeDef;
263
264#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
268typedef enum
269{
270 HAL_OSPI_ERROR_CB_ID = 0x00U,
271 HAL_OSPI_ABORT_CB_ID = 0x01U,
272 HAL_OSPI_FIFO_THRESHOLD_CB_ID = 0x02U,
273 HAL_OSPI_CMD_CPLT_CB_ID = 0x03U,
274 HAL_OSPI_RX_CPLT_CB_ID = 0x04U,
275 HAL_OSPI_TX_CPLT_CB_ID = 0x05U,
276 HAL_OSPI_RX_HALF_CPLT_CB_ID = 0x06U,
277 HAL_OSPI_TX_HALF_CPLT_CB_ID = 0x07U,
278 HAL_OSPI_STATUS_MATCH_CB_ID = 0x08U,
279 HAL_OSPI_TIMEOUT_CB_ID = 0x09U,
281 HAL_OSPI_MSP_INIT_CB_ID = 0x0AU,
282 HAL_OSPI_MSP_DEINIT_CB_ID = 0x0BU
283} HAL_OSPI_CallbackIDTypeDef;
284
288typedef void (*pOSPI_CallbackTypeDef)(OSPI_HandleTypeDef *hospi);
289#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */
294/* Exported constants --------------------------------------------------------*/
304#define HAL_OSPI_STATE_RESET ((uint32_t)0x00000000U)
305#define HAL_OSPI_STATE_HYPERBUS_INIT ((uint32_t)0x00000001U)
306#define HAL_OSPI_STATE_READY ((uint32_t)0x00000002U)
307#define HAL_OSPI_STATE_CMD_CFG ((uint32_t)0x00000004U)
308#define HAL_OSPI_STATE_READ_CMD_CFG ((uint32_t)0x00000014U)
309#define HAL_OSPI_STATE_WRITE_CMD_CFG ((uint32_t)0x00000024U)
310#define HAL_OSPI_STATE_BUSY_CMD ((uint32_t)0x00000008U)
311#define HAL_OSPI_STATE_BUSY_TX ((uint32_t)0x00000018U)
312#define HAL_OSPI_STATE_BUSY_RX ((uint32_t)0x00000028U)
313#define HAL_OSPI_STATE_BUSY_AUTO_POLLING ((uint32_t)0x00000048U)
314#define HAL_OSPI_STATE_BUSY_MEM_MAPPED ((uint32_t)0x00000088U)
315#define HAL_OSPI_STATE_ABORT ((uint32_t)0x00000100U)
316#define HAL_OSPI_STATE_ERROR ((uint32_t)0x00000200U)
325#define HAL_OSPI_ERROR_NONE ((uint32_t)0x00000000U)
326#define HAL_OSPI_ERROR_TIMEOUT ((uint32_t)0x00000001U)
327#define HAL_OSPI_ERROR_TRANSFER ((uint32_t)0x00000002U)
328#define HAL_OSPI_ERROR_DMA ((uint32_t)0x00000004U)
329#define HAL_OSPI_ERROR_INVALID_PARAM ((uint32_t)0x00000008U)
330#define HAL_OSPI_ERROR_INVALID_SEQUENCE ((uint32_t)0x00000010U)
331#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
332#define HAL_OSPI_ERROR_INVALID_CALLBACK ((uint32_t)0x00000020U)
333#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)*/
342#define HAL_OSPI_DUALQUAD_DISABLE ((uint32_t)0x00000000U)
343#define HAL_OSPI_DUALQUAD_ENABLE ((uint32_t)OCTOSPI_CR_DQM)
352#define HAL_OSPI_MEMTYPE_MICRON ((uint32_t)0x00000000U)
353#define HAL_OSPI_MEMTYPE_MACRONIX ((uint32_t)OCTOSPI_DCR1_MTYP_0)
354#define HAL_OSPI_MEMTYPE_APMEMORY ((uint32_t)OCTOSPI_DCR1_MTYP_1)
355#define HAL_OSPI_MEMTYPE_MACRONIX_RAM ((uint32_t)(OCTOSPI_DCR1_MTYP_1 | OCTOSPI_DCR1_MTYP_0))
356#define HAL_OSPI_MEMTYPE_HYPERBUS ((uint32_t)OCTOSPI_DCR1_MTYP_2)
365#define HAL_OSPI_FREERUNCLK_DISABLE ((uint32_t)0x00000000U)
366#define HAL_OSPI_FREERUNCLK_ENABLE ((uint32_t)OCTOSPI_DCR1_FRCK)
375#define HAL_OSPI_CLOCK_MODE_0 ((uint32_t)0x00000000U)
376#define HAL_OSPI_CLOCK_MODE_3 ((uint32_t)OCTOSPI_DCR1_CKMODE)
385#define HAL_OSPI_WRAP_NOT_SUPPORTED ((uint32_t)0x00000000U)
386#define HAL_OSPI_WRAP_16_BYTES ((uint32_t)OCTOSPI_DCR2_WRAPSIZE_1)
387#define HAL_OSPI_WRAP_32_BYTES ((uint32_t)(OCTOSPI_DCR2_WRAPSIZE_0 | OCTOSPI_DCR2_WRAPSIZE_1))
388#define HAL_OSPI_WRAP_64_BYTES ((uint32_t)OCTOSPI_DCR2_WRAPSIZE_2)
389#define HAL_OSPI_WRAP_128_BYTES ((uint32_t)(OCTOSPI_DCR2_WRAPSIZE_0 | OCTOSPI_DCR2_WRAPSIZE_2))
398#define HAL_OSPI_SAMPLE_SHIFTING_NONE ((uint32_t)0x00000000U)
399#define HAL_OSPI_SAMPLE_SHIFTING_HALFCYCLE ((uint32_t)OCTOSPI_TCR_SSHIFT)
408#define HAL_OSPI_DHQC_DISABLE ((uint32_t)0x00000000U)
409#define HAL_OSPI_DHQC_ENABLE ((uint32_t)OCTOSPI_TCR_DHQC)
418#define HAL_OSPI_DELAY_BLOCK_USED ((uint32_t)0x00000000U)
419#define HAL_OSPI_DELAY_BLOCK_BYPASSED ((uint32_t)OCTOSPI_DCR1_DLYBYP)
428#define HAL_OSPI_OPTYPE_COMMON_CFG ((uint32_t)0x00000000U)
429#define HAL_OSPI_OPTYPE_READ_CFG ((uint32_t)0x00000001U)
430#define HAL_OSPI_OPTYPE_WRITE_CFG ((uint32_t)0x00000002U)
431#define HAL_OSPI_OPTYPE_WRAP_CFG ((uint32_t)0x00000003U)
440#define HAL_OSPI_FLASH_ID_1 ((uint32_t)0x00000000U)
441#define HAL_OSPI_FLASH_ID_2 ((uint32_t)OCTOSPI_CR_FSEL)
450#define HAL_OSPI_INSTRUCTION_NONE ((uint32_t)0x00000000U)
451#define HAL_OSPI_INSTRUCTION_1_LINE ((uint32_t)OCTOSPI_CCR_IMODE_0)
452#define HAL_OSPI_INSTRUCTION_2_LINES ((uint32_t)OCTOSPI_CCR_IMODE_1)
453#define HAL_OSPI_INSTRUCTION_4_LINES ((uint32_t)(OCTOSPI_CCR_IMODE_0 | OCTOSPI_CCR_IMODE_1))
454#define HAL_OSPI_INSTRUCTION_8_LINES ((uint32_t)OCTOSPI_CCR_IMODE_2)
463#define HAL_OSPI_INSTRUCTION_8_BITS ((uint32_t)0x00000000U)
464#define HAL_OSPI_INSTRUCTION_16_BITS ((uint32_t)OCTOSPI_CCR_ISIZE_0)
465#define HAL_OSPI_INSTRUCTION_24_BITS ((uint32_t)OCTOSPI_CCR_ISIZE_1)
466#define HAL_OSPI_INSTRUCTION_32_BITS ((uint32_t)OCTOSPI_CCR_ISIZE)
475#define HAL_OSPI_INSTRUCTION_DTR_DISABLE ((uint32_t)0x00000000U)
476#define HAL_OSPI_INSTRUCTION_DTR_ENABLE ((uint32_t)OCTOSPI_CCR_IDTR)
485#define HAL_OSPI_ADDRESS_NONE ((uint32_t)0x00000000U)
486#define HAL_OSPI_ADDRESS_1_LINE ((uint32_t)OCTOSPI_CCR_ADMODE_0)
487#define HAL_OSPI_ADDRESS_2_LINES ((uint32_t)OCTOSPI_CCR_ADMODE_1)
488#define HAL_OSPI_ADDRESS_4_LINES ((uint32_t)(OCTOSPI_CCR_ADMODE_0 | OCTOSPI_CCR_ADMODE_1))
489#define HAL_OSPI_ADDRESS_8_LINES ((uint32_t)OCTOSPI_CCR_ADMODE_2)
498#define HAL_OSPI_ADDRESS_8_BITS ((uint32_t)0x00000000U)
499#define HAL_OSPI_ADDRESS_16_BITS ((uint32_t)OCTOSPI_CCR_ADSIZE_0)
500#define HAL_OSPI_ADDRESS_24_BITS ((uint32_t)OCTOSPI_CCR_ADSIZE_1)
501#define HAL_OSPI_ADDRESS_32_BITS ((uint32_t)OCTOSPI_CCR_ADSIZE)
510#define HAL_OSPI_ADDRESS_DTR_DISABLE ((uint32_t)0x00000000U)
511#define HAL_OSPI_ADDRESS_DTR_ENABLE ((uint32_t)OCTOSPI_CCR_ADDTR)
520#define HAL_OSPI_ALTERNATE_BYTES_NONE ((uint32_t)0x00000000U)
521#define HAL_OSPI_ALTERNATE_BYTES_1_LINE ((uint32_t)OCTOSPI_CCR_ABMODE_0)
522#define HAL_OSPI_ALTERNATE_BYTES_2_LINES ((uint32_t)OCTOSPI_CCR_ABMODE_1)
523#define HAL_OSPI_ALTERNATE_BYTES_4_LINES ((uint32_t)(OCTOSPI_CCR_ABMODE_0 | OCTOSPI_CCR_ABMODE_1))
524#define HAL_OSPI_ALTERNATE_BYTES_8_LINES ((uint32_t)OCTOSPI_CCR_ABMODE_2)
533#define HAL_OSPI_ALTERNATE_BYTES_8_BITS ((uint32_t)0x00000000U)
534#define HAL_OSPI_ALTERNATE_BYTES_16_BITS ((uint32_t)OCTOSPI_CCR_ABSIZE_0)
535#define HAL_OSPI_ALTERNATE_BYTES_24_BITS ((uint32_t)OCTOSPI_CCR_ABSIZE_1)
536#define HAL_OSPI_ALTERNATE_BYTES_32_BITS ((uint32_t)OCTOSPI_CCR_ABSIZE)
545#define HAL_OSPI_ALTERNATE_BYTES_DTR_DISABLE ((uint32_t)0x00000000U)
546#define HAL_OSPI_ALTERNATE_BYTES_DTR_ENABLE ((uint32_t)OCTOSPI_CCR_ABDTR)
555#define HAL_OSPI_DATA_NONE ((uint32_t)0x00000000U)
556#define HAL_OSPI_DATA_1_LINE ((uint32_t)OCTOSPI_CCR_DMODE_0)
557#define HAL_OSPI_DATA_2_LINES ((uint32_t)OCTOSPI_CCR_DMODE_1)
558#define HAL_OSPI_DATA_4_LINES ((uint32_t)(OCTOSPI_CCR_DMODE_0 | OCTOSPI_CCR_DMODE_1))
559#define HAL_OSPI_DATA_8_LINES ((uint32_t)OCTOSPI_CCR_DMODE_2)
568#define HAL_OSPI_DATA_DTR_DISABLE ((uint32_t)0x00000000U)
569#define HAL_OSPI_DATA_DTR_ENABLE ((uint32_t)OCTOSPI_CCR_DDTR)
578#define HAL_OSPI_DQS_DISABLE ((uint32_t)0x00000000U)
579#define HAL_OSPI_DQS_ENABLE ((uint32_t)OCTOSPI_CCR_DQSE)
588#define HAL_OSPI_SIOO_INST_EVERY_CMD ((uint32_t)0x00000000U)
589#define HAL_OSPI_SIOO_INST_ONLY_FIRST_CMD ((uint32_t)OCTOSPI_CCR_SIOO)
598#define HAL_OSPI_LATENCY_ON_WRITE ((uint32_t)0x00000000U)
599#define HAL_OSPI_NO_LATENCY_ON_WRITE ((uint32_t)OCTOSPI_HLCR_WZL)
608#define HAL_OSPI_VARIABLE_LATENCY ((uint32_t)0x00000000U)
609#define HAL_OSPI_FIXED_LATENCY ((uint32_t)OCTOSPI_HLCR_LM)
618#define HAL_OSPI_MEMORY_ADDRESS_SPACE ((uint32_t)0x00000000U)
619#define HAL_OSPI_REGISTER_ADDRESS_SPACE ((uint32_t)OCTOSPI_DCR1_MTYP_0)
628#define HAL_OSPI_MATCH_MODE_AND ((uint32_t)0x00000000U)
629#define HAL_OSPI_MATCH_MODE_OR ((uint32_t)OCTOSPI_CR_PMM)
638#define HAL_OSPI_AUTOMATIC_STOP_DISABLE ((uint32_t)0x00000000U)
639#define HAL_OSPI_AUTOMATIC_STOP_ENABLE ((uint32_t)OCTOSPI_CR_APMS)
648#define HAL_OSPI_TIMEOUT_COUNTER_DISABLE ((uint32_t)0x00000000U)
649#define HAL_OSPI_TIMEOUT_COUNTER_ENABLE ((uint32_t)OCTOSPI_CR_TCEN)
658#define HAL_OSPI_FLAG_BUSY OCTOSPI_SR_BUSY
659#define HAL_OSPI_FLAG_TO OCTOSPI_SR_TOF
660#define HAL_OSPI_FLAG_SM OCTOSPI_SR_SMF
661#define HAL_OSPI_FLAG_FT OCTOSPI_SR_FTF
662#define HAL_OSPI_FLAG_TC OCTOSPI_SR_TCF
663#define HAL_OSPI_FLAG_TE OCTOSPI_SR_TEF
672#define HAL_OSPI_IT_TO OCTOSPI_CR_TOIE
673#define HAL_OSPI_IT_SM OCTOSPI_CR_SMIE
674#define HAL_OSPI_IT_FT OCTOSPI_CR_FTIE
675#define HAL_OSPI_IT_TC OCTOSPI_CR_TCIE
676#define HAL_OSPI_IT_TE OCTOSPI_CR_TEIE
685#define HAL_OSPI_TIMEOUT_DEFAULT_VALUE ((uint32_t)5000U) /* 5 s */
694#define HAL_OSPIM_IOPORT_NONE ((uint32_t)0x00000000U)
695#define HAL_OSPIM_IOPORT_1_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x1U))
696#define HAL_OSPIM_IOPORT_1_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x1U))
697#define HAL_OSPIM_IOPORT_2_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x2U))
698#define HAL_OSPIM_IOPORT_2_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x2U))
699#define HAL_OSPIM_IOPORT_3_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x3U))
700#define HAL_OSPIM_IOPORT_3_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x3U))
701#define HAL_OSPIM_IOPORT_4_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x4U))
702#define HAL_OSPIM_IOPORT_4_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x4U))
703#define HAL_OSPIM_IOPORT_5_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x5U))
704#define HAL_OSPIM_IOPORT_5_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x5U))
705#define HAL_OSPIM_IOPORT_6_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x6U))
706#define HAL_OSPIM_IOPORT_6_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x6U))
707#define HAL_OSPIM_IOPORT_7_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x7U))
708#define HAL_OSPIM_IOPORT_7_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x7U))
709#define HAL_OSPIM_IOPORT_8_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x8U))
710#define HAL_OSPIM_IOPORT_8_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x8U))
718/* Exported macros -----------------------------------------------------------*/
727#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
728#define __HAL_OSPI_RESET_HANDLE_STATE(__HANDLE__) do { \
729 (__HANDLE__)->State = HAL_OSPI_STATE_RESET; \
730 (__HANDLE__)->MspInitCallback = NULL; \
731 (__HANDLE__)->MspDeInitCallback = NULL; \
732 } while(0)
733#else
734#define __HAL_OSPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_OSPI_STATE_RESET)
735#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */
736
741#define __HAL_OSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, OCTOSPI_CR_EN)
742
747#define __HAL_OSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, OCTOSPI_CR_EN)
748
760#define __HAL_OSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
761
762
774#define __HAL_OSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
775
787#define __HAL_OSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))\
788 == (__INTERRUPT__))
789
803#define __HAL_OSPI_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) \
804 != 0U) ? SET : RESET)
805
816#define __HAL_OSPI_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__))
817
822/* Exported functions --------------------------------------------------------*/
827/* Initialization/de-initialization functions ********************************/
831HAL_StatusTypeDef HAL_OSPI_Init(OSPI_HandleTypeDef *hospi);
832void HAL_OSPI_MspInit(OSPI_HandleTypeDef *hospi);
833HAL_StatusTypeDef HAL_OSPI_DeInit(OSPI_HandleTypeDef *hospi);
834void HAL_OSPI_MspDeInit(OSPI_HandleTypeDef *hospi);
835
840/* IO operation functions *****************************************************/
844/* OSPI IRQ handler function */
845void HAL_OSPI_IRQHandler(OSPI_HandleTypeDef *hospi);
846
847/* OSPI command configuration functions */
848HAL_StatusTypeDef HAL_OSPI_Command(OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTypeDef *cmd, uint32_t Timeout);
849HAL_StatusTypeDef HAL_OSPI_Command_IT(OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTypeDef *cmd);
850HAL_StatusTypeDef HAL_OSPI_HyperbusCfg(OSPI_HandleTypeDef *hospi, OSPI_HyperbusCfgTypeDef *cfg, uint32_t Timeout);
851HAL_StatusTypeDef HAL_OSPI_HyperbusCmd(OSPI_HandleTypeDef *hospi, OSPI_HyperbusCmdTypeDef *cmd, uint32_t Timeout);
852
853/* OSPI indirect mode functions */
854HAL_StatusTypeDef HAL_OSPI_Transmit(OSPI_HandleTypeDef *hospi, uint8_t *pData, uint32_t Timeout);
855HAL_StatusTypeDef HAL_OSPI_Receive(OSPI_HandleTypeDef *hospi, uint8_t *pData, uint32_t Timeout);
856HAL_StatusTypeDef HAL_OSPI_Transmit_IT(OSPI_HandleTypeDef *hospi, uint8_t *pData);
857HAL_StatusTypeDef HAL_OSPI_Receive_IT(OSPI_HandleTypeDef *hospi, uint8_t *pData);
858HAL_StatusTypeDef HAL_OSPI_Transmit_DMA(OSPI_HandleTypeDef *hospi, uint8_t *pData);
859HAL_StatusTypeDef HAL_OSPI_Receive_DMA(OSPI_HandleTypeDef *hospi, uint8_t *pData);
860
861/* OSPI status flag polling mode functions */
862HAL_StatusTypeDef HAL_OSPI_AutoPolling(OSPI_HandleTypeDef *hospi, OSPI_AutoPollingTypeDef *cfg, uint32_t Timeout);
863HAL_StatusTypeDef HAL_OSPI_AutoPolling_IT(OSPI_HandleTypeDef *hospi, OSPI_AutoPollingTypeDef *cfg);
864
865/* OSPI memory-mapped mode functions */
866HAL_StatusTypeDef HAL_OSPI_MemoryMapped(OSPI_HandleTypeDef *hospi, OSPI_MemoryMappedTypeDef *cfg);
867
868/* Callback functions in non-blocking modes ***********************************/
869void HAL_OSPI_ErrorCallback(OSPI_HandleTypeDef *hospi);
870void HAL_OSPI_AbortCpltCallback(OSPI_HandleTypeDef *hospi);
871void HAL_OSPI_FifoThresholdCallback(OSPI_HandleTypeDef *hospi);
872
873/* OSPI indirect mode functions */
874void HAL_OSPI_CmdCpltCallback(OSPI_HandleTypeDef *hospi);
875void HAL_OSPI_RxCpltCallback(OSPI_HandleTypeDef *hospi);
876void HAL_OSPI_TxCpltCallback(OSPI_HandleTypeDef *hospi);
877void HAL_OSPI_RxHalfCpltCallback(OSPI_HandleTypeDef *hospi);
878void HAL_OSPI_TxHalfCpltCallback(OSPI_HandleTypeDef *hospi);
879
880/* OSPI status flag polling mode functions */
881void HAL_OSPI_StatusMatchCallback(OSPI_HandleTypeDef *hospi);
882
883/* OSPI memory-mapped mode functions */
884void HAL_OSPI_TimeOutCallback(OSPI_HandleTypeDef *hospi);
885
886#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
887/* OSPI callback registering/unregistering */
888HAL_StatusTypeDef HAL_OSPI_RegisterCallback(OSPI_HandleTypeDef *hospi, HAL_OSPI_CallbackIDTypeDef CallbackID,
889 pOSPI_CallbackTypeDef pCallback);
890HAL_StatusTypeDef HAL_OSPI_UnRegisterCallback(OSPI_HandleTypeDef *hospi, HAL_OSPI_CallbackIDTypeDef CallbackID);
891#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */
896/* Peripheral Control and State functions ************************************/
900HAL_StatusTypeDef HAL_OSPI_Abort(OSPI_HandleTypeDef *hospi);
901HAL_StatusTypeDef HAL_OSPI_Abort_IT(OSPI_HandleTypeDef *hospi);
902HAL_StatusTypeDef HAL_OSPI_SetFifoThreshold(OSPI_HandleTypeDef *hospi, uint32_t Threshold);
903uint32_t HAL_OSPI_GetFifoThreshold(const OSPI_HandleTypeDef *hospi);
904HAL_StatusTypeDef HAL_OSPI_SetTimeout(OSPI_HandleTypeDef *hospi, uint32_t Timeout);
905uint32_t HAL_OSPI_GetError(const OSPI_HandleTypeDef *hospi);
906uint32_t HAL_OSPI_GetState(const OSPI_HandleTypeDef *hospi);
907
912/* OSPI IO Manager configuration function ************************************/
916HAL_StatusTypeDef HAL_OSPIM_Config(OSPI_HandleTypeDef *hospi, OSPIM_CfgTypeDef *cfg, uint32_t Timeout);
917
925/* End of exported functions -------------------------------------------------*/
926
927/* Private macros ------------------------------------------------------------*/
931#define IS_OSPI_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) >= 1U) && ((THRESHOLD) <= 32U))
932
933#define IS_OSPI_DUALQUAD_MODE(MODE) (((MODE) == HAL_OSPI_DUALQUAD_DISABLE) || \
934 ((MODE) == HAL_OSPI_DUALQUAD_ENABLE))
935
936#define IS_OSPI_MEMORY_TYPE(TYPE) (((TYPE) == HAL_OSPI_MEMTYPE_MICRON) || \
937 ((TYPE) == HAL_OSPI_MEMTYPE_MACRONIX) || \
938 ((TYPE) == HAL_OSPI_MEMTYPE_APMEMORY) || \
939 ((TYPE) == HAL_OSPI_MEMTYPE_MACRONIX_RAM) || \
940 ((TYPE) == HAL_OSPI_MEMTYPE_HYPERBUS))
941
942#define IS_OSPI_DEVICE_SIZE(SIZE) (((SIZE) >= 1U) && ((SIZE) <= 32U))
943
944#define IS_OSPI_CS_HIGH_TIME(TIME) (((TIME) >= 1U) && ((TIME) <= 8U))
945
946#define IS_OSPI_FREE_RUN_CLK(CLK) (((CLK) == HAL_OSPI_FREERUNCLK_DISABLE) || \
947 ((CLK) == HAL_OSPI_FREERUNCLK_ENABLE))
948
949#define IS_OSPI_CLOCK_MODE(MODE) (((MODE) == HAL_OSPI_CLOCK_MODE_0) || \
950 ((MODE) == HAL_OSPI_CLOCK_MODE_3))
951
952#define IS_OSPI_WRAP_SIZE(SIZE) (((SIZE) == HAL_OSPI_WRAP_NOT_SUPPORTED) || \
953 ((SIZE) == HAL_OSPI_WRAP_16_BYTES) || \
954 ((SIZE) == HAL_OSPI_WRAP_32_BYTES) || \
955 ((SIZE) == HAL_OSPI_WRAP_64_BYTES) || \
956 ((SIZE) == HAL_OSPI_WRAP_128_BYTES))
957
958#define IS_OSPI_CLK_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 256U))
959
960#define IS_OSPI_SAMPLE_SHIFTING(CYCLE) (((CYCLE) == HAL_OSPI_SAMPLE_SHIFTING_NONE) || \
961 ((CYCLE) == HAL_OSPI_SAMPLE_SHIFTING_HALFCYCLE))
962
963#define IS_OSPI_DHQC(CYCLE) (((CYCLE) == HAL_OSPI_DHQC_DISABLE) || \
964 ((CYCLE) == HAL_OSPI_DHQC_ENABLE))
965
966#define IS_OSPI_OPERATION_TYPE(TYPE) (((TYPE) == HAL_OSPI_OPTYPE_COMMON_CFG) || \
967 ((TYPE) == HAL_OSPI_OPTYPE_READ_CFG) || \
968 ((TYPE) == HAL_OSPI_OPTYPE_WRITE_CFG) || \
969 ((TYPE) == HAL_OSPI_OPTYPE_WRAP_CFG))
970
971#define IS_OSPI_FLASH_ID(FLASHID) (((FLASHID) == HAL_OSPI_FLASH_ID_1) || \
972 ((FLASHID) == HAL_OSPI_FLASH_ID_2))
973
974#define IS_OSPI_INSTRUCTION_MODE(MODE) (((MODE) == HAL_OSPI_INSTRUCTION_NONE) || \
975 ((MODE) == HAL_OSPI_INSTRUCTION_1_LINE) || \
976 ((MODE) == HAL_OSPI_INSTRUCTION_2_LINES) || \
977 ((MODE) == HAL_OSPI_INSTRUCTION_4_LINES) || \
978 ((MODE) == HAL_OSPI_INSTRUCTION_8_LINES))
979
980#define IS_OSPI_INSTRUCTION_SIZE(SIZE) (((SIZE) == HAL_OSPI_INSTRUCTION_8_BITS) || \
981 ((SIZE) == HAL_OSPI_INSTRUCTION_16_BITS) || \
982 ((SIZE) == HAL_OSPI_INSTRUCTION_24_BITS) || \
983 ((SIZE) == HAL_OSPI_INSTRUCTION_32_BITS))
984
985#define IS_OSPI_INSTRUCTION_DTR_MODE(MODE) (((MODE) == HAL_OSPI_INSTRUCTION_DTR_DISABLE) || \
986 ((MODE) == HAL_OSPI_INSTRUCTION_DTR_ENABLE))
987
988#define IS_OSPI_ADDRESS_MODE(MODE) (((MODE) == HAL_OSPI_ADDRESS_NONE) || \
989 ((MODE) == HAL_OSPI_ADDRESS_1_LINE) || \
990 ((MODE) == HAL_OSPI_ADDRESS_2_LINES) || \
991 ((MODE) == HAL_OSPI_ADDRESS_4_LINES) || \
992 ((MODE) == HAL_OSPI_ADDRESS_8_LINES))
993
994#define IS_OSPI_ADDRESS_SIZE(SIZE) (((SIZE) == HAL_OSPI_ADDRESS_8_BITS) || \
995 ((SIZE) == HAL_OSPI_ADDRESS_16_BITS) || \
996 ((SIZE) == HAL_OSPI_ADDRESS_24_BITS) || \
997 ((SIZE) == HAL_OSPI_ADDRESS_32_BITS))
998
999#define IS_OSPI_ADDRESS_DTR_MODE(MODE) (((MODE) == HAL_OSPI_ADDRESS_DTR_DISABLE) || \
1000 ((MODE) == HAL_OSPI_ADDRESS_DTR_ENABLE))
1001
1002#define IS_OSPI_ALT_BYTES_MODE(MODE) (((MODE) == HAL_OSPI_ALTERNATE_BYTES_NONE) || \
1003 ((MODE) == HAL_OSPI_ALTERNATE_BYTES_1_LINE) || \
1004 ((MODE) == HAL_OSPI_ALTERNATE_BYTES_2_LINES) || \
1005 ((MODE) == HAL_OSPI_ALTERNATE_BYTES_4_LINES) || \
1006 ((MODE) == HAL_OSPI_ALTERNATE_BYTES_8_LINES))
1007
1008#define IS_OSPI_ALT_BYTES_SIZE(SIZE) (((SIZE) == HAL_OSPI_ALTERNATE_BYTES_8_BITS) || \
1009 ((SIZE) == HAL_OSPI_ALTERNATE_BYTES_16_BITS) || \
1010 ((SIZE) == HAL_OSPI_ALTERNATE_BYTES_24_BITS) || \
1011 ((SIZE) == HAL_OSPI_ALTERNATE_BYTES_32_BITS))
1012
1013#define IS_OSPI_ALT_BYTES_DTR_MODE(MODE) (((MODE) == HAL_OSPI_ALTERNATE_BYTES_DTR_DISABLE) || \
1014 ((MODE) == HAL_OSPI_ALTERNATE_BYTES_DTR_ENABLE))
1015
1016#define IS_OSPI_DATA_MODE(MODE) (((MODE) == HAL_OSPI_DATA_NONE) || \
1017 ((MODE) == HAL_OSPI_DATA_1_LINE) || \
1018 ((MODE) == HAL_OSPI_DATA_2_LINES) || \
1019 ((MODE) == HAL_OSPI_DATA_4_LINES) || \
1020 ((MODE) == HAL_OSPI_DATA_8_LINES))
1021
1022#define IS_OSPI_NUMBER_DATA(NUMBER) ((NUMBER) >= 1U)
1023
1024#define IS_OSPI_DATA_DTR_MODE(MODE) (((MODE) == HAL_OSPI_DATA_DTR_DISABLE) || \
1025 ((MODE) == HAL_OSPI_DATA_DTR_ENABLE))
1026
1027#define IS_OSPI_DUMMY_CYCLES(NUMBER) ((NUMBER) <= 31U)
1028
1029#define IS_OSPI_DQS_MODE(MODE) (((MODE) == HAL_OSPI_DQS_DISABLE) || \
1030 ((MODE) == HAL_OSPI_DQS_ENABLE))
1031
1032#define IS_OSPI_SIOO_MODE(MODE) (((MODE) == HAL_OSPI_SIOO_INST_EVERY_CMD) || \
1033 ((MODE) == HAL_OSPI_SIOO_INST_ONLY_FIRST_CMD))
1034
1035#define IS_OSPI_RW_RECOVERY_TIME(NUMBER) ((NUMBER) <= 255U)
1036
1037#define IS_OSPI_ACCESS_TIME(NUMBER) ((NUMBER) <= 255U)
1038
1039#define IS_OSPI_WRITE_ZERO_LATENCY(MODE) (((MODE) == HAL_OSPI_LATENCY_ON_WRITE) || \
1040 ((MODE) == HAL_OSPI_NO_LATENCY_ON_WRITE))
1041
1042#define IS_OSPI_LATENCY_MODE(MODE) (((MODE) == HAL_OSPI_VARIABLE_LATENCY) || \
1043 ((MODE) == HAL_OSPI_FIXED_LATENCY))
1044
1045#define IS_OSPI_ADDRESS_SPACE(SPACE) (((SPACE) == HAL_OSPI_MEMORY_ADDRESS_SPACE) || \
1046 ((SPACE) == HAL_OSPI_REGISTER_ADDRESS_SPACE))
1047
1048#define IS_OSPI_MATCH_MODE(MODE) (((MODE) == HAL_OSPI_MATCH_MODE_AND) || \
1049 ((MODE) == HAL_OSPI_MATCH_MODE_OR))
1050
1051#define IS_OSPI_AUTOMATIC_STOP(MODE) (((MODE) == HAL_OSPI_AUTOMATIC_STOP_ENABLE) || \
1052 ((MODE) == HAL_OSPI_AUTOMATIC_STOP_DISABLE))
1053
1054#define IS_OSPI_INTERVAL(INTERVAL) ((INTERVAL) <= 0xFFFFU)
1055
1056#define IS_OSPI_STATUS_BYTES_SIZE(SIZE) (((SIZE) >= 1U) && ((SIZE) <= 4U))
1057
1058#define IS_OSPI_TIMEOUT_ACTIVATION(MODE) (((MODE) == HAL_OSPI_TIMEOUT_COUNTER_DISABLE) || \
1059 ((MODE) == HAL_OSPI_TIMEOUT_COUNTER_ENABLE))
1060
1061#define IS_OSPI_TIMEOUT_PERIOD(PERIOD) ((PERIOD) <= 0xFFFFU)
1062
1063#define IS_OSPI_CS_BOUNDARY(BOUNDARY) ((BOUNDARY) <= 31U)
1064
1065#define IS_OSPI_DLYBYP(MODE) (((MODE) == HAL_OSPI_DELAY_BLOCK_USED) || \
1066 ((MODE) == HAL_OSPI_DELAY_BLOCK_BYPASSED))
1067
1068#define IS_OSPI_MAXTRAN(NB_BYTES) ((NB_BYTES) <= 255U)
1069
1070#define IS_OSPIM_PORT(NUMBER) (((NUMBER) >= 1U) && ((NUMBER) <= 8U))
1071
1072#define IS_OSPIM_DQS_PORT(NUMBER) ((NUMBER) <= 8U)
1073
1074#define IS_OSPIM_IO_PORT(PORT) (((PORT) == HAL_OSPIM_IOPORT_NONE) || \
1075 ((PORT) == HAL_OSPIM_IOPORT_1_LOW) || \
1076 ((PORT) == HAL_OSPIM_IOPORT_1_HIGH) || \
1077 ((PORT) == HAL_OSPIM_IOPORT_2_LOW) || \
1078 ((PORT) == HAL_OSPIM_IOPORT_2_HIGH) || \
1079 ((PORT) == HAL_OSPIM_IOPORT_3_LOW) || \
1080 ((PORT) == HAL_OSPIM_IOPORT_3_HIGH) || \
1081 ((PORT) == HAL_OSPIM_IOPORT_4_LOW) || \
1082 ((PORT) == HAL_OSPIM_IOPORT_4_HIGH) || \
1083 ((PORT) == HAL_OSPIM_IOPORT_5_LOW) || \
1084 ((PORT) == HAL_OSPIM_IOPORT_5_HIGH) || \
1085 ((PORT) == HAL_OSPIM_IOPORT_6_LOW) || \
1086 ((PORT) == HAL_OSPIM_IOPORT_6_HIGH) || \
1087 ((PORT) == HAL_OSPIM_IOPORT_7_LOW) || \
1088 ((PORT) == HAL_OSPIM_IOPORT_7_HIGH) || \
1089 ((PORT) == HAL_OSPIM_IOPORT_8_LOW) || \
1090 ((PORT) == HAL_OSPIM_IOPORT_8_HIGH))
1091
1092#define IS_OSPIM_REQ2ACKTIME(TIME) (((TIME) >= 1U) && ((TIME) <= 256U))
1097/* End of private macros -----------------------------------------------------*/
1098
1107#endif /* OCTOSPI || OCTOSPI1 || OCTOSPI2 */
1108
1109#ifdef __cplusplus
1110}
1111#endif
1112
1113#endif /* STM32H7xx_HAL_OSPI_H */
__IO
#define __IO
Definition: core_cm4.h:239
stm32h7xx_hal_def.h
This file contains HAL common defines, enumeration, macros and structures definitions.
HAL_StatusTypeDef
HAL_StatusTypeDef
HAL Status structures definition.
Definition: stm32h7xx_hal_def.h:47
OCTOSPI_TypeDef
OCTO Serial Peripheral Interface.
Definition: stm32h723xx.h:1887
__MDMA_HandleTypeDef
MDMA handle Structure definition.
Definition: stm32h7xx_hal_mdma.h:204
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