html/doxygen/stm32h7xx__hal__eth_8h_source.html

/* Define to prevent recursive inclusion -------------------------------------*/

#ifndef STM32H7xx_HAL_ETH_H

#define STM32H7xx_HAL_ETH_H


#ifdef __cplusplus

extern "C" {

#endif


/* Includes ------------------------------------------------------------------*/

#include "stm32h7xx_hal_def.h"


#if defined(ETH)


/* Exported types ------------------------------------------------------------*/

#ifndef ETH_TX_DESC_CNT

#define ETH_TX_DESC_CNT         4U

#endif /* ETH_TX_DESC_CNT */


#ifndef ETH_RX_DESC_CNT

#define ETH_RX_DESC_CNT         4U

#endif /* ETH_RX_DESC_CNT */


#ifndef ETH_SWRESET_TIMEOUT

#define ETH_SWRESET_TIMEOUT     500U

#endif /* ETH_SWRESET_TIMEOUT */


#ifndef ETH_MDIO_BUS_TIMEOUT

#define ETH_MDIO_BUS_TIMEOUT    1000U

#endif /* ETH_MDIO_BUS_TIMEOUT */


#ifndef ETH_MAC_US_TICK

#define ETH_MAC_US_TICK         1000000U

#endif /* ETH_MAC_US_TICK */


/*********************** Descriptors struct def section ************************/

typedef struct

{

  __IO uint32_t DESC0;

  __IO uint32_t DESC1;

  __IO uint32_t DESC2;

  __IO uint32_t DESC3;

  uint32_t BackupAddr0; /* used to store rx buffer 1 address */

  uint32_t BackupAddr1; /* used to store rx buffer 2 address */

} ETH_DMADescTypeDef;

typedef struct __ETH_BufferTypeDef

{

  uint8_t *buffer;                /*<! buffer address */


  uint32_t len;                   /*<! buffer length */


  struct __ETH_BufferTypeDef *next; /*<! Pointer to the next buffer in the list */

} ETH_BufferTypeDef;

typedef struct

{

  uint32_t  TxDesc[ETH_TX_DESC_CNT];        /*<! Tx DMA descriptors addresses */


  uint32_t  CurTxDesc;                      /*<! Current Tx descriptor index for packet transmission */


  uint32_t *PacketAddress[ETH_TX_DESC_CNT];  /*<! Ethernet packet addresses array */


  uint32_t *CurrentPacketAddress;           /*<! Current transmit NX_PACKET addresses */


  uint32_t BuffersInUse;                   /*<! Buffers in Use */


  uint32_t releaseIndex;                  /*<! Release index */

} ETH_TxDescListTypeDef;

typedef struct

{

  uint32_t Attributes;

  uint32_t Length;

  ETH_BufferTypeDef *TxBuffer;

  uint32_t SrcAddrCtrl;

  uint32_t CRCPadCtrl;

  uint32_t ChecksumCtrl;

  uint32_t MaxSegmentSize;

  uint32_t PayloadLen;

  uint32_t TCPHeaderLen;

  uint32_t VlanTag;

  uint32_t VlanCtrl;

  uint32_t InnerVlanTag;

  uint32_t InnerVlanCtrl;

  void *pData;

} ETH_TxPacketConfigTypeDef;

typedef struct

{

  uint32_t TimeStampLow;

  uint32_t TimeStampHigh;


} ETH_TimeStampTypeDef;

#ifdef HAL_ETH_USE_PTP

typedef struct

{

  uint32_t Seconds;

  uint32_t NanoSeconds;

} ETH_TimeTypeDef;

#endif  /* HAL_ETH_USE_PTP */


typedef struct

{

  uint32_t RxDesc[ETH_RX_DESC_CNT];     /*<! Rx DMA descriptors addresses. */


  uint32_t ItMode;                      /*<! If 1, DMA will generate the Rx complete interrupt.

                                             If 0, DMA will not generate the Rx complete interrupt. */


  uint32_t RxDescIdx;                 /*<! Current Rx descriptor. */


  uint32_t RxDescCnt;                 /*<! Number of descriptors . */


  uint32_t RxDataLength;              /*<! Received Data Length. */


  uint32_t RxBuildDescIdx;            /*<! Current Rx Descriptor for building descriptors. */


  uint32_t RxBuildDescCnt;            /*<! Number of Rx Descriptors awaiting building. */


  uint32_t pRxLastRxDesc;             /*<! Last received descriptor. */


  ETH_TimeStampTypeDef TimeStamp;     /*<! Time Stamp Low value for receive. */


  void *pRxStart;                     /*<! Pointer to the first buff. */


  void *pRxEnd;                       /*<! Pointer to the last buff. */


} ETH_RxDescListTypeDef;

typedef struct

{

  uint32_t

  SourceAddrControl;

  FunctionalState

  ChecksumOffload;

  uint32_t         InterPacketGapVal;

  FunctionalState  GiantPacketSizeLimitControl;

  FunctionalState  Support2KPacket;

  FunctionalState  CRCStripTypePacket;

  FunctionalState  AutomaticPadCRCStrip;

  FunctionalState  Watchdog;

  FunctionalState  Jabber;

  FunctionalState  JumboPacket;

  uint32_t         Speed;

  uint32_t         DuplexMode;

  FunctionalState  LoopbackMode;

  FunctionalState

  CarrierSenseBeforeTransmit;

  FunctionalState  ReceiveOwn;

  FunctionalState

  CarrierSenseDuringTransmit;

  FunctionalState

  RetryTransmission;

  uint32_t         BackOffLimit;

  FunctionalState

  DeferralCheck;

  uint32_t

  PreambleLength;

  FunctionalState

  UnicastSlowProtocolPacketDetect;

  FunctionalState  SlowProtocolDetect;

  FunctionalState  CRCCheckingRxPackets;

  uint32_t

  GiantPacketSizeLimit;

  FunctionalState  ExtendedInterPacketGap;

  uint32_t         ExtendedInterPacketGapVal;

  FunctionalState  ProgrammableWatchdog;

  uint32_t         WatchdogTimeout;

  uint32_t

  PauseTime;

  FunctionalState

  ZeroQuantaPause;

  uint32_t

  PauseLowThreshold;

  FunctionalState

  TransmitFlowControl;

  FunctionalState

  UnicastPausePacketDetect;

  FunctionalState  ReceiveFlowControl;

  uint32_t         TransmitQueueMode;

  uint32_t         ReceiveQueueMode;

  FunctionalState  DropTCPIPChecksumErrorPacket;

  FunctionalState  ForwardRxErrorPacket;

  FunctionalState  ForwardRxUndersizedGoodPacket;

} ETH_MACConfigTypeDef;

typedef struct

{

  uint32_t        DMAArbitration;

  FunctionalState AddressAlignedBeats;

  uint32_t        BurstMode;

  FunctionalState RebuildINCRxBurst;

  FunctionalState PBLx8Mode;

  uint32_t

  TxDMABurstLength;

  FunctionalState

  SecondPacketOperate;

  uint32_t

  RxDMABurstLength;

  FunctionalState FlushRxPacket;

  FunctionalState TCPSegmentation;

  uint32_t

  MaximumSegmentSize;

} ETH_DMAConfigTypeDef;

typedef enum

{

  HAL_ETH_MII_MODE             = 0x00U,

  HAL_ETH_RMII_MODE            = 0x01U

} ETH_MediaInterfaceTypeDef;

#ifdef HAL_ETH_USE_PTP

typedef enum

{

  HAL_ETH_PTP_POSITIVE_UPDATE   = 0x00000000U,

  HAL_ETH_PTP_NEGATIVE_UPDATE   = 0x00000001U

} ETH_PtpUpdateTypeDef;

#endif  /* HAL_ETH_USE_PTP */


typedef struct

{

  uint8_t

  *MACAddr;

  ETH_MediaInterfaceTypeDef   MediaInterface;

  ETH_DMADescTypeDef

  *TxDesc;

  ETH_DMADescTypeDef

  *RxDesc;

  uint32_t                    RxBuffLen;

} ETH_InitTypeDef;

#ifdef HAL_ETH_USE_PTP

typedef struct

{

  uint32_t                    Timestamp;

  uint32_t                    TimestampUpdateMode;

  uint32_t                    TimestampInitialize;

  uint32_t                    TimestampUpdate;

  uint32_t                    TimestampAddendUpdate;

  uint32_t                    TimestampAll;

  uint32_t                    TimestampRolloverMode;

  uint32_t                    TimestampV2;

  uint32_t                    TimestampEthernet;

  uint32_t                    TimestampIPv6;

  uint32_t                    TimestampIPv4;

  uint32_t                    TimestampEvent;

  uint32_t                    TimestampMaster;

  uint32_t                    TimestampSnapshots;

  uint32_t                    TimestampFilter;

  uint32_t

  TimestampChecksumCorrection;

  uint32_t                    TimestampStatusMode;

  uint32_t                    TimestampAddend;

  uint32_t                    TimestampSubsecondInc;

} ETH_PTP_ConfigTypeDef;

#endif  /* HAL_ETH_USE_PTP */


typedef uint32_t HAL_ETH_StateTypeDef;

typedef  void (*pETH_rxAllocateCallbackTypeDef)(uint8_t **buffer);

typedef  void (*pETH_rxLinkCallbackTypeDef)(void **pStart, void **pEnd, uint8_t *buff,

                                            uint16_t Length);

typedef  void (*pETH_txFreeCallbackTypeDef)(uint32_t *buffer);

typedef  void (*pETH_txPtpCallbackTypeDef)(uint32_t *buffer,

                                           ETH_TimeStampTypeDef *timestamp);

#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)

typedef struct __ETH_HandleTypeDef

#else

typedef struct

#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */

{

  ETH_TypeDef                *Instance;

  ETH_InitTypeDef            Init;

  ETH_TxDescListTypeDef      TxDescList;

  ETH_RxDescListTypeDef      RxDescList;

#ifdef HAL_ETH_USE_PTP

  ETH_TimeStampTypeDef       TxTimestamp;

#endif /* HAL_ETH_USE_PTP */


  __IO HAL_ETH_StateTypeDef  gState;

  __IO uint32_t              ErrorCode;

  __IO uint32_t

  DMAErrorCode;

  __IO uint32_t

  MACErrorCode;

  __IO uint32_t              MACWakeUpEvent;

  __IO uint32_t              MACLPIEvent;

  __IO uint32_t              IsPtpConfigured;

#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)


  void (* TxCpltCallback)(struct __ETH_HandleTypeDef *heth);

  void (* RxCpltCallback)(struct __ETH_HandleTypeDef *heth);

  void (* ErrorCallback)(struct __ETH_HandleTypeDef *heth);

  void (* PMTCallback)(struct __ETH_HandleTypeDef *heth);

  void (* EEECallback)(struct __ETH_HandleTypeDef *heth);

  void (* WakeUpCallback)(struct __ETH_HandleTypeDef *heth);

  void (* MspInitCallback)(struct __ETH_HandleTypeDef *heth);

  void (* MspDeInitCallback)(struct __ETH_HandleTypeDef *heth);

#endif  /* USE_HAL_ETH_REGISTER_CALLBACKS */


  pETH_rxAllocateCallbackTypeDef  rxAllocateCallback;

  pETH_rxLinkCallbackTypeDef      rxLinkCallback;

  pETH_txFreeCallbackTypeDef      txFreeCallback;

  pETH_txPtpCallbackTypeDef       txPtpCallback;

} ETH_HandleTypeDef;

#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)

typedef enum

{

  HAL_ETH_MSPINIT_CB_ID            = 0x00U,

  HAL_ETH_MSPDEINIT_CB_ID          = 0x01U,

  HAL_ETH_TX_COMPLETE_CB_ID        = 0x02U,

  HAL_ETH_RX_COMPLETE_CB_ID        = 0x03U,

  HAL_ETH_ERROR_CB_ID              = 0x04U,

  HAL_ETH_PMT_CB_ID                = 0x06U,

  HAL_ETH_EEE_CB_ID                = 0x07U,

  HAL_ETH_WAKEUP_CB_ID             = 0x08U

} HAL_ETH_CallbackIDTypeDef;


typedef  void (*pETH_CallbackTypeDef)(ETH_HandleTypeDef *heth);

#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */


typedef struct

{

  FunctionalState PromiscuousMode;

  FunctionalState ReceiveAllMode;

  FunctionalState HachOrPerfectFilter;

  FunctionalState HashUnicast;

  FunctionalState HashMulticast;

  FunctionalState PassAllMulticast;

  FunctionalState SrcAddrFiltering;

  FunctionalState SrcAddrInverseFiltering;

  FunctionalState DestAddrInverseFiltering;

  FunctionalState BroadcastFilter;

  uint32_t        ControlPacketsFilter;

} ETH_MACFilterConfigTypeDef;

typedef struct

{

  FunctionalState WakeUpPacket;

  FunctionalState MagicPacket;

  FunctionalState GlobalUnicast;

  FunctionalState WakeUpForward;

} ETH_PowerDownConfigTypeDef;

/* Exported constants --------------------------------------------------------*/

/*

   DMA Tx Normal Descriptor Read Format

  -----------------------------------------------------------------------------------------------

  TDES0 |                         Buffer1 or Header Address  [31:0]                              |

  -----------------------------------------------------------------------------------------------

  TDES1 |                   Buffer2 Address [31:0] / Next Descriptor Address [31:0]              |

  -----------------------------------------------------------------------------------------------

  TDES2 | IOC(31) | TTSE(30) | Buff2 Length[29:16] | VTIR[15:14] | Header or Buff1 Length[13:0]  |

  -----------------------------------------------------------------------------------------------

  TDES3 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] |

  -----------------------------------------------------------------------------------------------

*/


#define ETH_DMATXNDESCRF_B1AP         0xFFFFFFFFU

#define ETH_DMATXNDESCRF_B2AP         0xFFFFFFFFU

#define ETH_DMATXNDESCRF_IOC          0x80000000U

#define ETH_DMATXNDESCRF_TTSE         0x40000000U

#define ETH_DMATXNDESCRF_B2L          0x3FFF0000U

#define ETH_DMATXNDESCRF_VTIR         0x0000C000U

#define ETH_DMATXNDESCRF_VTIR_DISABLE 0x00000000U

#define ETH_DMATXNDESCRF_VTIR_REMOVE  0x00004000U

#define ETH_DMATXNDESCRF_VTIR_INSERT  0x00008000U

#define ETH_DMATXNDESCRF_VTIR_REPLACE 0x0000C000U

#define ETH_DMATXNDESCRF_B1L          0x00003FFFU

#define ETH_DMATXNDESCRF_HL           0x000003FFU

#define ETH_DMATXNDESCRF_OWN                                 0x80000000U

#define ETH_DMATXNDESCRF_CTXT                                0x40000000U

#define ETH_DMATXNDESCRF_FD                                  0x20000000U

#define ETH_DMATXNDESCRF_LD                                  0x10000000U

#define ETH_DMATXNDESCRF_CPC                                 0x0C000000U

#define ETH_DMATXNDESCRF_CPC_CRCPAD_INSERT                   0x00000000U

#define ETH_DMATXNDESCRF_CPC_CRC_INSERT                      0x04000000U

#define ETH_DMATXNDESCRF_CPC_DISABLE                         0x08000000U

#define ETH_DMATXNDESCRF_CPC_CRC_REPLACE                     0x0C000000U

#define ETH_DMATXNDESCRF_SAIC                                0x03800000U

#define ETH_DMATXNDESCRF_SAIC_DISABLE                        0x00000000U

#define ETH_DMATXNDESCRF_SAIC_INSERT                         0x00800000U

#define ETH_DMATXNDESCRF_SAIC_REPLACE                        0x01000000U

#define ETH_DMATXNDESCRF_THL                                 0x00780000U

#define ETH_DMATXNDESCRF_TSE                                 0x00040000U

#define ETH_DMATXNDESCRF_CIC                                 0x00030000U

#define ETH_DMATXNDESCRF_CIC_DISABLE                         0x00000000U

#define ETH_DMATXNDESCRF_CIC_IPHDR_INSERT                    0x00010000U

#define ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT            0x00020000U

#define ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT_PHDR_CALC  0x00030000U

#define ETH_DMATXNDESCRF_TPL                                 0x0003FFFFU

#define ETH_DMATXNDESCRF_FL                                  0x00007FFFU

/*

   DMA Tx Normal Descriptor Write Back Format

  -----------------------------------------------------------------------------------------------

  TDES0 |                         Timestamp Low                                                  |

  -----------------------------------------------------------------------------------------------

  TDES1 |                         Timestamp High                                                 |

  -----------------------------------------------------------------------------------------------

  TDES2 |                           Reserved[31:0]                                               |

  -----------------------------------------------------------------------------------------------

  TDES3 | OWN(31) |                          Status[30:0]                                        |

  -----------------------------------------------------------------------------------------------

*/


#define ETH_DMATXNDESCWBF_TTSL                    0xFFFFFFFFU

#define ETH_DMATXNDESCWBF_TTSH                    0xFFFFFFFFU

#define ETH_DMATXNDESCWBF_OWN                     0x80000000U

#define ETH_DMATXNDESCWBF_CTXT                    0x40000000U

#define ETH_DMATXNDESCWBF_FD                      0x20000000U

#define ETH_DMATXNDESCWBF_LD                      0x10000000U

#define ETH_DMATXNDESCWBF_TTSS                    0x00020000U

#define ETH_DMATXNDESCWBF_DP                      0x04000000U

#define ETH_DMATXNDESCWBF_TTSE                    0x02000000U

#define ETH_DMATXNDESCWBF_ES                      0x00008000U

#define ETH_DMATXNDESCWBF_JT                      0x00004000U

#define ETH_DMATXNDESCWBF_FF                      0x00002000U

#define ETH_DMATXNDESCWBF_PCE                     0x00001000U

#define ETH_DMATXNDESCWBF_LCA                     0x00000800U

#define ETH_DMATXNDESCWBF_NC                      0x00000400U

#define ETH_DMATXNDESCWBF_LCO                     0x00000200U

#define ETH_DMATXNDESCWBF_EC                      0x00000100U

#define ETH_DMATXNDESCWBF_CC                      0x000000F0U

#define ETH_DMATXNDESCWBF_ED                      0x00000008U

#define ETH_DMATXNDESCWBF_UF                      0x00000004U

#define ETH_DMATXNDESCWBF_DB                      0x00000002U

#define ETH_DMATXNDESCWBF_IHE                     0x00000004U

/*

   DMA Tx Context Descriptor

  -----------------------------------------------------------------------------------------------

  TDES0 |                               Timestamp Low                                            |

  -----------------------------------------------------------------------------------------------

  TDES1 |                               Timestamp High                                           |

  -----------------------------------------------------------------------------------------------

  TDES2 |      Inner VLAN Tag[31:16]    | Reserved(15) |     Maximum Segment Size [14:0]         |

  -----------------------------------------------------------------------------------------------

  TDES3 | OWN(31) |                          Status[30:0]                                        |

  -----------------------------------------------------------------------------------------------

*/


#define ETH_DMATXCDESC_TTSL                    0xFFFFFFFFU

#define ETH_DMATXCDESC_TTSH                    0xFFFFFFFFU

#define ETH_DMATXCDESC_IVT                     0xFFFF0000U

#define ETH_DMATXCDESC_MSS                     0x00003FFFU

#define ETH_DMATXCDESC_OWN                     0x80000000U

#define ETH_DMATXCDESC_CTXT                    0x40000000U

#define ETH_DMATXCDESC_OSTC                    0x08000000U

#define ETH_DMATXCDESC_TCMSSV                  0x04000000U

#define ETH_DMATXCDESC_CDE                     0x00800000U

#define ETH_DMATXCDESC_IVTIR                   0x000C0000U

#define ETH_DMATXCDESC_IVTIR_DISABLE           0x00000000U

#define ETH_DMATXCDESC_IVTIR_REMOVE            0x00040000U

#define ETH_DMATXCDESC_IVTIR_INSERT            0x00080000U

#define ETH_DMATXCDESC_IVTIR_REPLACE           0x000C0000U

#define ETH_DMATXCDESC_IVLTV                   0x00020000U

#define ETH_DMATXCDESC_VLTV                    0x00010000U

#define ETH_DMATXCDESC_VT                      0x0000FFFFU

/*

  DMA Rx Normal Descriptor read format

  -----------------------------------------------------------------------------------------------------------

  RDES0 |                                  Buffer1 or Header Address [31:0]                                 |

  -----------------------------------------------------------------------------------------------------------

  RDES1 |                                            Reserved                                               |

  -----------------------------------------------------------------------------------------------------------

  RDES2 |                                      Payload or Buffer2 Address[31:0]                             |

  -----------------------------------------------------------------------------------------------------------

  RDES3 | OWN(31) | IOC(30) | Reserved [29:26] | BUF2V(25) | BUF1V(24) |           Reserved [23:0]          |

  -----------------------------------------------------------------------------------------------------------

*/


#define ETH_DMARXNDESCRF_BUF1AP           0xFFFFFFFFU

#define ETH_DMARXNDESCRF_BUF2AP           0xFFFFFFFFU

#define ETH_DMARXNDESCRF_OWN              0x80000000U

#define ETH_DMARXNDESCRF_IOC              0x40000000U

#define ETH_DMARXNDESCRF_BUF2V            0x02000000U

#define ETH_DMARXNDESCRF_BUF1V            0x01000000U

/*

  DMA Rx Normal Descriptor write back format

  ---------------------------------------------------------------------------------------------------------------------

  RDES0 |                 Inner VLAN Tag[31:16]                 |                 Outer VLAN Tag[15:0]                |

  ---------------------------------------------------------------------------------------------------------------------

  RDES1 |       OAM code, or MAC Control Opcode [31:16]         |               Extended Status                       |

  ---------------------------------------------------------------------------------------------------------------------

  RDES2 |      MAC Filter Status[31:16]        | VF(15) | Reserved [14:12] | ARP Status [11:10] | Header Length [9:0] |

  ---------------------------------------------------------------------------------------------------------------------

  RDES3 | OWN(31) | CTXT(30) |  FD(29) | LD(28) |   Status[27:16]     | ES(15) |        Packet Length[14:0]           |

  ---------------------------------------------------------------------------------------------------------------------

*/


#define ETH_DMARXNDESCWBF_IVT             0xFFFF0000U

#define ETH_DMARXNDESCWBF_OVT             0x0000FFFFU

#define ETH_DMARXNDESCWBF_OPC             0xFFFF0000U

#define ETH_DMARXNDESCWBF_TD              0x00008000U

#define ETH_DMARXNDESCWBF_TSA             0x00004000U

#define ETH_DMARXNDESCWBF_PV              0x00002000U

#define ETH_DMARXNDESCWBF_PFT             0x00001000U

#define ETH_DMARXNDESCWBF_PMT_NO          0x00000000U

#define ETH_DMARXNDESCWBF_PMT_SYNC        0x00000100U

#define ETH_DMARXNDESCWBF_PMT_FUP         0x00000200U

#define ETH_DMARXNDESCWBF_PMT_DREQ        0x00000300U

#define ETH_DMARXNDESCWBF_PMT_DRESP       0x00000400U

#define ETH_DMARXNDESCWBF_PMT_PDREQ       0x00000500U

#define ETH_DMARXNDESCWBF_PMT_PDRESP      0x00000600U

#define ETH_DMARXNDESCWBF_PMT_PDRESPFUP   0x00000700U

#define ETH_DMARXNDESCWBF_PMT_ANNOUNCE    0x00000800U

#define ETH_DMARXNDESCWBF_PMT_MANAG       0x00000900U

#define ETH_DMARXNDESCWBF_PMT_SIGN        0x00000A00U

#define ETH_DMARXNDESCWBF_PMT_RESERVED    0x00000F00U

#define ETH_DMARXNDESCWBF_IPCE            0x00000080U

#define ETH_DMARXNDESCWBF_IPCB            0x00000040U

#define ETH_DMARXNDESCWBF_IPV6            0x00000020U

#define ETH_DMARXNDESCWBF_IPV4            0x00000010U

#define ETH_DMARXNDESCWBF_IPHE            0x00000008U

#define ETH_DMARXNDESCWBF_PT              0x00000003U

#define ETH_DMARXNDESCWBF_PT_UNKNOWN      0x00000000U

#define ETH_DMARXNDESCWBF_PT_UDP          0x00000001U

#define ETH_DMARXNDESCWBF_PT_TCP          0x00000002U

#define ETH_DMARXNDESCWBF_PT_ICMP         0x00000003U

#define ETH_DMARXNDESCWBF_L3L4FM          0x20000000U

#define ETH_DMARXNDESCWBF_L4FM            0x10000000U

#define ETH_DMARXNDESCWBF_L3FM            0x08000000U

#define ETH_DMARXNDESCWBF_MADRM           0x07F80000U

#define ETH_DMARXNDESCWBF_HF              0x00040000U

#define ETH_DMARXNDESCWBF_DAF             0x00020000U

#define ETH_DMARXNDESCWBF_SAF             0x00010000U

#define ETH_DMARXNDESCWBF_VF              0x00008000U

#define ETH_DMARXNDESCWBF_ARPNR           0x00000400U

#define ETH_DMARXNDESCWBF_OWN             0x80000000U

#define ETH_DMARXNDESCWBF_CTXT            0x40000000U

#define ETH_DMARXNDESCWBF_FD              0x20000000U

#define ETH_DMARXNDESCWBF_LD              0x10000000U

#define ETH_DMARXNDESCWBF_RS2V            0x08000000U

#define ETH_DMARXNDESCWBF_RS1V            0x04000000U

#define ETH_DMARXNDESCWBF_RS0V            0x02000000U

#define ETH_DMARXNDESCWBF_CE              0x01000000U

#define ETH_DMARXNDESCWBF_GP              0x00800000U

#define ETH_DMARXNDESCWBF_RWT             0x00400000U

#define ETH_DMARXNDESCWBF_OE              0x00200000U

#define ETH_DMARXNDESCWBF_RE              0x00100000U

#define ETH_DMARXNDESCWBF_DE              0x00080000U

#define ETH_DMARXNDESCWBF_LT              0x00070000U

#define ETH_DMARXNDESCWBF_LT_LP           0x00000000U

#define ETH_DMARXNDESCWBF_LT_TP           0x00010000U

#define ETH_DMARXNDESCWBF_LT_ARP          0x00030000U

#define ETH_DMARXNDESCWBF_LT_VLAN         0x00040000U

#define ETH_DMARXNDESCWBF_LT_DVLAN        0x00050000U

#define ETH_DMARXNDESCWBF_LT_MAC          0x00060000U

#define ETH_DMARXNDESCWBF_LT_OAM          0x00070000U

#define ETH_DMARXNDESCWBF_ES              0x00008000U

#define ETH_DMARXNDESCWBF_PL              0x00007FFFU

/*

  DMA Rx context Descriptor

  ---------------------------------------------------------------------------------------------------------------------

  RDES0 |                                     Timestamp Low[31:0]                                                     |

  ---------------------------------------------------------------------------------------------------------------------

  RDES1 |                                     Timestamp High[31:0]                                                    |

  ---------------------------------------------------------------------------------------------------------------------

  RDES2 |                                          Reserved                                                           |

  ---------------------------------------------------------------------------------------------------------------------

  RDES3 | OWN(31) | CTXT(30) |                                Reserved[29:0]                                          |

  ---------------------------------------------------------------------------------------------------------------------

*/


#define ETH_DMARXCDESC_RTSL                   0xFFFFFFFFU

#define ETH_DMARXCDESC_RTSH                   0xFFFFFFFFU

#define ETH_DMARXCDESC_OWN                    0x80000000U

#define ETH_DMARXCDESC_CTXT                   0x40000000U

#define ETH_MAX_PACKET_SIZE                   1528U

#define ETH_HEADER                            14U

#define ETH_CRC                               4U

#define ETH_VLAN_TAG                          4U

#define ETH_MIN_PAYLOAD                       46U

#define ETH_MAX_PAYLOAD                       1500U

#define ETH_JUMBO_FRAME_PAYLOAD               9000U

#define HAL_ETH_ERROR_NONE                    0x00000000U

#define HAL_ETH_ERROR_PARAM                   0x00000001U

#define HAL_ETH_ERROR_BUSY                    0x00000002U

#define HAL_ETH_ERROR_TIMEOUT                 0x00000004U

#define HAL_ETH_ERROR_DMA                     0x00000008U

#define HAL_ETH_ERROR_MAC                     0x00000010U

#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)

#define HAL_ETH_ERROR_INVALID_CALLBACK        0x00000020U

#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */

#define ETH_TX_PACKETS_FEATURES_CSUM          0x00000001U

#define ETH_TX_PACKETS_FEATURES_SAIC          0x00000002U

#define ETH_TX_PACKETS_FEATURES_VLANTAG       0x00000004U

#define ETH_TX_PACKETS_FEATURES_INNERVLANTAG  0x00000008U

#define ETH_TX_PACKETS_FEATURES_TSO           0x00000010U

#define ETH_TX_PACKETS_FEATURES_CRCPAD        0x00000020U

#define ETH_SRC_ADDR_CONTROL_DISABLE          ETH_DMATXNDESCRF_SAIC_DISABLE

#define ETH_SRC_ADDR_INSERT                   ETH_DMATXNDESCRF_SAIC_INSERT

#define ETH_SRC_ADDR_REPLACE                  ETH_DMATXNDESCRF_SAIC_REPLACE

#define ETH_CRC_PAD_DISABLE      ETH_DMATXNDESCRF_CPC_DISABLE

#define ETH_CRC_PAD_INSERT       ETH_DMATXNDESCRF_CPC_CRCPAD_INSERT

#define ETH_CRC_INSERT           ETH_DMATXNDESCRF_CPC_CRC_INSERT

#define ETH_CRC_REPLACE          ETH_DMATXNDESCRF_CPC_CRC_REPLACE

#define ETH_CHECKSUM_DISABLE                         ETH_DMATXNDESCRF_CIC_DISABLE

#define ETH_CHECKSUM_IPHDR_INSERT                    ETH_DMATXNDESCRF_CIC_IPHDR_INSERT

#define ETH_CHECKSUM_IPHDR_PAYLOAD_INSERT            ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT

#define ETH_CHECKSUM_IPHDR_PAYLOAD_INSERT_PHDR_CALC  ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT_PHDR_CALC

#define ETH_VLAN_DISABLE  ETH_DMATXNDESCRF_VTIR_DISABLE

#define ETH_VLAN_REMOVE   ETH_DMATXNDESCRF_VTIR_REMOVE

#define ETH_VLAN_INSERT   ETH_DMATXNDESCRF_VTIR_INSERT

#define ETH_VLAN_REPLACE  ETH_DMATXNDESCRF_VTIR_REPLACE

#define ETH_INNER_VLAN_DISABLE  ETH_DMATXCDESC_IVTIR_DISABLE

#define ETH_INNER_VLAN_REMOVE   ETH_DMATXCDESC_IVTIR_REMOVE

#define ETH_INNER_VLAN_INSERT   ETH_DMATXCDESC_IVTIR_INSERT

#define ETH_INNER_VLAN_REPLACE  ETH_DMATXCDESC_IVTIR_REPLACE

#define ETH_CHECKSUM_BYPASSED           ETH_DMARXNDESCWBF_IPCB

#define ETH_CHECKSUM_IP_HEADER_ERROR    ETH_DMARXNDESCWBF_IPHE

#define ETH_CHECKSUM_IP_PAYLOAD_ERROR   ETH_DMARXNDESCWBF_IPCE

#define ETH_IP_HEADER_IPV4   ETH_DMARXNDESCWBF_IPV4

#define ETH_IP_HEADER_IPV6   ETH_DMARXNDESCWBF_IPV6

#define ETH_IP_PAYLOAD_UNKNOWN   ETH_DMARXNDESCWBF_PT_UNKNOWN

#define ETH_IP_PAYLOAD_UDP       ETH_DMARXNDESCWBF_PT_UDP

#define ETH_IP_PAYLOAD_TCP       ETH_DMARXNDESCWBF_PT_TCP

#define ETH_IP_PAYLOAD_ICMPN     ETH_DMARXNDESCWBF_PT_ICMP

#define ETH_HASH_FILTER_PASS        ETH_DMARXNDESCWBF_HF

#define ETH_VLAN_FILTER_PASS        ETH_DMARXNDESCWBF_VF

#define ETH_DEST_ADDRESS_FAIL       ETH_DMARXNDESCWBF_DAF

#define ETH_SOURCE_ADDRESS_FAIL     ETH_DMARXNDESCWBF_SAF

#define ETH_L3_FILTER0_MATCH        ETH_DMARXNDESCWBF_L3FM

#define ETH_L3_FILTER1_MATCH        (ETH_DMARXNDESCWBF_L3FM | ETH_DMARXNDESCWBF_L3L4FM)

#define ETH_L4_FILTER0_MATCH        ETH_DMARXNDESCWBF_L4FM

#define ETH_L4_FILTER1_MATCH        (ETH_DMARXNDESCWBF_L4FM | ETH_DMARXNDESCWBF_L3L4FM)

#define ETH_DRIBBLE_BIT_ERROR   ETH_DMARXNDESCWBF_DE

#define ETH_RECEIVE_ERROR       ETH_DMARXNDESCWBF_RE

#define ETH_RECEIVE_OVERFLOW    ETH_DMARXNDESCWBF_OE

#define ETH_WATCHDOG_TIMEOUT    ETH_DMARXNDESCWBF_RWT

#define ETH_GIANT_PACKET        ETH_DMARXNDESCWBF_GP

#define ETH_CRC_ERROR           ETH_DMARXNDESCWBF_CE

#define ETH_DMAARBITRATION_RX        ETH_DMAMR_DA

#define ETH_DMAARBITRATION_RX1_TX1   0x00000000U

#define ETH_DMAARBITRATION_RX2_TX1   ETH_DMAMR_PR_2_1

#define ETH_DMAARBITRATION_RX3_TX1   ETH_DMAMR_PR_3_1

#define ETH_DMAARBITRATION_RX4_TX1   ETH_DMAMR_PR_4_1

#define ETH_DMAARBITRATION_RX5_TX1   ETH_DMAMR_PR_5_1

#define ETH_DMAARBITRATION_RX6_TX1   ETH_DMAMR_PR_6_1

#define ETH_DMAARBITRATION_RX7_TX1   ETH_DMAMR_PR_7_1

#define ETH_DMAARBITRATION_RX8_TX1   ETH_DMAMR_PR_8_1

#define ETH_DMAARBITRATION_TX        (ETH_DMAMR_TXPR | ETH_DMAMR_DA)

#define ETH_DMAARBITRATION_TX1_RX1   0x00000000U

#define ETH_DMAARBITRATION_TX2_RX1   (ETH_DMAMR_TXPR | ETH_DMAMR_PR_2_1)

#define ETH_DMAARBITRATION_TX3_RX1   (ETH_DMAMR_TXPR | ETH_DMAMR_PR_3_1)

#define ETH_DMAARBITRATION_TX4_RX1   (ETH_DMAMR_TXPR | ETH_DMAMR_PR_4_1)

#define ETH_DMAARBITRATION_TX5_RX1   (ETH_DMAMR_TXPR | ETH_DMAMR_PR_5_1)

#define ETH_DMAARBITRATION_TX6_RX1   (ETH_DMAMR_TXPR | ETH_DMAMR_PR_6_1)

#define ETH_DMAARBITRATION_TX7_RX1   (ETH_DMAMR_TXPR | ETH_DMAMR_PR_7_1)

#define ETH_DMAARBITRATION_TX8_RX1   (ETH_DMAMR_TXPR | ETH_DMAMR_PR_8_1)

#define ETH_BURSTLENGTH_FIXED           ETH_DMASBMR_FB

#define ETH_BURSTLENGTH_MIXED           ETH_DMASBMR_MB

#define ETH_BURSTLENGTH_UNSPECIFIED     0x00000000U

#define ETH_TXDMABURSTLENGTH_1BEAT          ETH_DMACTCR_TPBL_1PBL

#define ETH_TXDMABURSTLENGTH_2BEAT          ETH_DMACTCR_TPBL_2PBL

#define ETH_TXDMABURSTLENGTH_4BEAT          ETH_DMACTCR_TPBL_4PBL

#define ETH_TXDMABURSTLENGTH_8BEAT          ETH_DMACTCR_TPBL_8PBL

#define ETH_TXDMABURSTLENGTH_16BEAT         ETH_DMACTCR_TPBL_16PBL

#define ETH_TXDMABURSTLENGTH_32BEAT         ETH_DMACTCR_TPBL_32PBL

#define ETH_RXDMABURSTLENGTH_1BEAT          ETH_DMACRCR_RPBL_1PBL

#define ETH_RXDMABURSTLENGTH_2BEAT          ETH_DMACRCR_RPBL_2PBL

#define ETH_RXDMABURSTLENGTH_4BEAT          ETH_DMACRCR_RPBL_4PBL

#define ETH_RXDMABURSTLENGTH_8BEAT          ETH_DMACRCR_RPBL_8PBL

#define ETH_RXDMABURSTLENGTH_16BEAT         ETH_DMACRCR_RPBL_16PBL

#define ETH_RXDMABURSTLENGTH_32BEAT         ETH_DMACRCR_RPBL_32PBL

#define ETH_DMA_NORMAL_IT                 ETH_DMACIER_NIE

#define ETH_DMA_ABNORMAL_IT               ETH_DMACIER_AIE

#define ETH_DMA_CONTEXT_DESC_ERROR_IT     ETH_DMACIER_CDEE

#define ETH_DMA_FATAL_BUS_ERROR_IT        ETH_DMACIER_FBEE

#define ETH_DMA_EARLY_RX_IT               ETH_DMACIER_ERIE

#define ETH_DMA_EARLY_TX_IT               ETH_DMACIER_ETIE

#define ETH_DMA_RX_WATCHDOG_TIMEOUT_IT    ETH_DMACIER_RWTE

#define ETH_DMA_RX_PROCESS_STOPPED_IT     ETH_DMACIER_RSE

#define ETH_DMA_RX_BUFFER_UNAVAILABLE_IT  ETH_DMACIER_RBUE

#define ETH_DMA_RX_IT                     ETH_DMACIER_RIE

#define ETH_DMA_TX_BUFFER_UNAVAILABLE_IT  ETH_DMACIER_TBUE

#define ETH_DMA_TX_PROCESS_STOPPED_IT     ETH_DMACIER_TXSE

#define ETH_DMA_TX_IT                     ETH_DMACIER_TIE

#define ETH_DMA_RX_NO_ERROR_FLAG                 0x00000000U

#define ETH_DMA_RX_DESC_READ_ERROR_FLAG          (ETH_DMACSR_REB_BIT_2 | ETH_DMACSR_REB_BIT_1 | ETH_DMACSR_REB_BIT_0)

#define ETH_DMA_RX_DESC_WRITE_ERROR_FLAG         (ETH_DMACSR_REB_BIT_2 | ETH_DMACSR_REB_BIT_1)

#define ETH_DMA_RX_BUFFER_READ_ERROR_FLAG        (ETH_DMACSR_REB_BIT_2 | ETH_DMACSR_REB_BIT_0)

#define ETH_DMA_RX_BUFFER_WRITE_ERROR_FLAG        ETH_DMACSR_REB_BIT_2

#define ETH_DMA_TX_NO_ERROR_FLAG                 0x00000000U

#define ETH_DMA_TX_DESC_READ_ERROR_FLAG          (ETH_DMACSR_TEB_BIT_2 | ETH_DMACSR_TEB_BIT_1 | ETH_DMACSR_TEB_BIT_0)

#define ETH_DMA_TX_DESC_WRITE_ERROR_FLAG         (ETH_DMACSR_TEB_BIT_2 | ETH_DMACSR_TEB_BIT_1)

#define ETH_DMA_TX_BUFFER_READ_ERROR_FLAG        (ETH_DMACSR_TEB_BIT_2 | ETH_DMACSR_TEB_BIT_0)

#define ETH_DMA_TX_BUFFER_WRITE_ERROR_FLAG        ETH_DMACSR_TEB_BIT_2

#define ETH_DMA_CONTEXT_DESC_ERROR_FLAG           ETH_DMACSR_CDE

#define ETH_DMA_FATAL_BUS_ERROR_FLAG              ETH_DMACSR_FBE

#define ETH_DMA_EARLY_TX_IT_FLAG                  ETH_DMACSR_ERI

#define ETH_DMA_RX_WATCHDOG_TIMEOUT_FLAG          ETH_DMACSR_RWT

#define ETH_DMA_RX_PROCESS_STOPPED_FLAG           ETH_DMACSR_RPS

#define ETH_DMA_RX_BUFFER_UNAVAILABLE_FLAG        ETH_DMACSR_RBU

#define ETH_DMA_TX_PROCESS_STOPPED_FLAG           ETH_DMACSR_TPS

#define ETH_TRANSMITSTOREFORWARD       ETH_MTLTQOMR_TSF

#define ETH_TRANSMITTHRESHOLD_32       ETH_MTLTQOMR_TTC_32BITS

#define ETH_TRANSMITTHRESHOLD_64       ETH_MTLTQOMR_TTC_64BITS

#define ETH_TRANSMITTHRESHOLD_96       ETH_MTLTQOMR_TTC_96BITS

#define ETH_TRANSMITTHRESHOLD_128      ETH_MTLTQOMR_TTC_128BITS

#define ETH_TRANSMITTHRESHOLD_192      ETH_MTLTQOMR_TTC_192BITS

#define ETH_TRANSMITTHRESHOLD_256      ETH_MTLTQOMR_TTC_256BITS

#define ETH_TRANSMITTHRESHOLD_384      ETH_MTLTQOMR_TTC_384BITS

#define ETH_TRANSMITTHRESHOLD_512      ETH_MTLTQOMR_TTC_512BITS

#define ETH_RECEIVESTOREFORWARD        ETH_MTLRQOMR_RSF

#define ETH_RECEIVETHRESHOLD8_64       ETH_MTLRQOMR_RTC_64BITS

#define ETH_RECEIVETHRESHOLD8_32       ETH_MTLRQOMR_RTC_32BITS

#define ETH_RECEIVETHRESHOLD8_96       ETH_MTLRQOMR_RTC_96BITS

#define ETH_RECEIVETHRESHOLD8_128      ETH_MTLRQOMR_RTC_128BITS

#define ETH_PAUSELOWTHRESHOLD_MINUS_4        ETH_MACTFCR_PLT_MINUS4

#define ETH_PAUSELOWTHRESHOLD_MINUS_28       ETH_MACTFCR_PLT_MINUS28

#define ETH_PAUSELOWTHRESHOLD_MINUS_36       ETH_MACTFCR_PLT_MINUS36

#define ETH_PAUSELOWTHRESHOLD_MINUS_144      ETH_MACTFCR_PLT_MINUS144

#define ETH_PAUSELOWTHRESHOLD_MINUS_256      ETH_MACTFCR_PLT_MINUS256

#define ETH_PAUSELOWTHRESHOLD_MINUS_512      ETH_MACTFCR_PLT_MINUS512

#define ETH_WATCHDOGTIMEOUT_2KB      ETH_MACWTR_WTO_2KB

#define ETH_WATCHDOGTIMEOUT_3KB      ETH_MACWTR_WTO_3KB

#define ETH_WATCHDOGTIMEOUT_4KB      ETH_MACWTR_WTO_4KB

#define ETH_WATCHDOGTIMEOUT_5KB      ETH_MACWTR_WTO_5KB

#define ETH_WATCHDOGTIMEOUT_6KB      ETH_MACWTR_WTO_6KB

#define ETH_WATCHDOGTIMEOUT_7KB      ETH_MACWTR_WTO_7KB

#define ETH_WATCHDOGTIMEOUT_8KB      ETH_MACWTR_WTO_8KB

#define ETH_WATCHDOGTIMEOUT_9KB      ETH_MACWTR_WTO_9KB

#define ETH_WATCHDOGTIMEOUT_10KB     ETH_MACWTR_WTO_10KB

#define ETH_WATCHDOGTIMEOUT_11KB     ETH_MACWTR_WTO_12KB

#define ETH_WATCHDOGTIMEOUT_12KB     ETH_MACWTR_WTO_12KB

#define ETH_WATCHDOGTIMEOUT_13KB     ETH_MACWTR_WTO_13KB

#define ETH_WATCHDOGTIMEOUT_14KB     ETH_MACWTR_WTO_14KB

#define ETH_WATCHDOGTIMEOUT_15KB     ETH_MACWTR_WTO_15KB

#define ETH_WATCHDOGTIMEOUT_16KB     ETH_MACWTR_WTO_16KB

#define ETH_INTERPACKETGAP_96BIT   ETH_MACCR_IPG_96BIT

#define ETH_INTERPACKETGAP_88BIT   ETH_MACCR_IPG_88BIT

#define ETH_INTERPACKETGAP_80BIT   ETH_MACCR_IPG_80BIT

#define ETH_INTERPACKETGAP_72BIT   ETH_MACCR_IPG_72BIT

#define ETH_INTERPACKETGAP_64BIT   ETH_MACCR_IPG_64BIT

#define ETH_INTERPACKETGAP_56BIT   ETH_MACCR_IPG_56BIT

#define ETH_INTERPACKETGAP_48BIT   ETH_MACCR_IPG_48BIT

#define ETH_INTERPACKETGAP_40BIT   ETH_MACCR_IPG_40BIT

#define ETH_SPEED_10M        0x00000000U

#define ETH_SPEED_100M       ETH_MACCR_FES

#define ETH_FULLDUPLEX_MODE       ETH_MACCR_DM

#define ETH_HALFDUPLEX_MODE       0x00000000U

#define ETH_BACKOFFLIMIT_10  ETH_MACCR_BL_10

#define ETH_BACKOFFLIMIT_8   ETH_MACCR_BL_8

#define ETH_BACKOFFLIMIT_4   ETH_MACCR_BL_4

#define ETH_BACKOFFLIMIT_1   ETH_MACCR_BL_1

#define ETH_PREAMBLELENGTH_7      ETH_MACCR_PRELEN_7

#define ETH_PREAMBLELENGTH_5      ETH_MACCR_PRELEN_5

#define ETH_PREAMBLELENGTH_3      ETH_MACCR_PRELEN_3

#define ETH_SOURCEADDRESS_DISABLE           0x00000000U

#define ETH_SOURCEADDRESS_INSERT_ADDR0      ETH_MACCR_SARC_INSADDR0

#define ETH_SOURCEADDRESS_INSERT_ADDR1      ETH_MACCR_SARC_INSADDR1

#define ETH_SOURCEADDRESS_REPLACE_ADDR0     ETH_MACCR_SARC_REPADDR0

#define ETH_SOURCEADDRESS_REPLACE_ADDR1     ETH_MACCR_SARC_REPADDR1

#define ETH_CTRLPACKETS_BLOCK_ALL                      ETH_MACPFR_PCF_BLOCKALL

#define ETH_CTRLPACKETS_FORWARD_ALL_EXCEPT_PA          ETH_MACPFR_PCF_FORWARDALLEXCEPTPA

#define ETH_CTRLPACKETS_FORWARD_ALL                    ETH_MACPFR_PCF_FORWARDALL

#define ETH_CTRLPACKETS_FORWARD_PASSED_ADDR_FILTER     ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER

#define ETH_VLANTAGCOMPARISON_16BIT          0x00000000U

#define ETH_VLANTAGCOMPARISON_12BIT          ETH_MACVTR_ETV

#define ETH_MAC_ADDRESS0     0x00000000U

#define ETH_MAC_ADDRESS1     0x00000008U

#define ETH_MAC_ADDRESS2     0x00000010U

#define ETH_MAC_ADDRESS3     0x00000018U

#define ETH_MAC_RX_STATUS_IT     ETH_MACIER_RXSTSIE

#define ETH_MAC_TX_STATUS_IT     ETH_MACIER_TXSTSIE

#define ETH_MAC_TIMESTAMP_IT     ETH_MACIER_TSIE

#define ETH_MAC_LPI_IT           ETH_MACIER_LPIIE

#define ETH_MAC_PMT_IT           ETH_MACIER_PMTIE

#define ETH_MAC_PHY_IT           ETH_MACIER_PHYIE

#define ETH_WAKEUP_PACKET_RECIEVED    ETH_MACPCSR_RWKPRCVD

#define ETH_MAGIC_PACKET_RECIEVED     ETH_MACPCSR_MGKPRCVD

#define ETH_RECEIVE_WATCHDOG_TIMEOUT        ETH_MACRXTXSR_RWT

#define ETH_EXECESSIVE_COLLISIONS           ETH_MACRXTXSR_EXCOL

#define ETH_LATE_COLLISIONS                 ETH_MACRXTXSR_LCOL

#define ETH_EXECESSIVE_DEFERRAL             ETH_MACRXTXSR_EXDEF

#define ETH_LOSS_OF_CARRIER                 ETH_MACRXTXSR_LCARR

#define ETH_NO_CARRIER                      ETH_MACRXTXSR_NCARR

#define ETH_TRANSMIT_JABBR_TIMEOUT          ETH_MACRXTXSR_TJT

#define HAL_ETH_STATE_RESET                0x00000000U

#define HAL_ETH_STATE_READY                0x00000010U

#define HAL_ETH_STATE_BUSY                 0x00000023U

#define HAL_ETH_STATE_STARTED              0x00000023U

#define HAL_ETH_STATE_ERROR                0x000000E0U

#define HAL_ETH_PTP_NOT_CONFIGURED        0x00000000U

#define HAL_ETH_PTP_CONFIGURED            0x00000001U

/* Exported macro ------------------------------------------------------------*/

#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)

#define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \

                                                      (__HANDLE__)->gState = HAL_ETH_STATE_RESET;      \

                                                      (__HANDLE__)->MspInitCallback = NULL;             \

                                                      (__HANDLE__)->MspDeInitCallback = NULL;           \

                                                    } while(0)

#else

#define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \

                                                      (__HANDLE__)->gState = HAL_ETH_STATE_RESET;      \

                                                    } while(0)

#endif /*USE_HAL_ETH_REGISTER_CALLBACKS */


#define __HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMACIER |= (__INTERRUPT__))


#define __HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMACIER &= ~(__INTERRUPT__))


#define __HAL_ETH_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \

  (((__HANDLE__)->Instance->DMACIER &  (__INTERRUPT__)) == (__INTERRUPT__))


#define __HAL_ETH_DMA_GET_IT(__HANDLE__, __INTERRUPT__) \

  (((__HANDLE__)->Instance->DMACSR &  (__INTERRUPT__)) == (__INTERRUPT__))


#define __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMACSR = (__INTERRUPT__))


#define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->DMACSR &( __FLAG__)) == ( __FLAG__))


#define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->DMACSR = ( __FLAG__))


#define __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIER |= (__INTERRUPT__))


#define __HAL_ETH_MAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIER &= ~(__INTERRUPT__))


#define __HAL_ETH_MAC_GET_IT(__HANDLE__, __INTERRUPT__)                     (((__HANDLE__)->Instance->MACISR &\

                                                                              ( __INTERRUPT__)) == ( __INTERRUPT__))


#define ETH_WAKEUP_EXTI_LINE  0x00400000U  /* !<  86 - 64 = 22 */


#define __HAL_ETH_WAKEUP_EXTI_ENABLE_IT(__EXTI_LINE__)   (EXTI_D1->IMR3 |= (__EXTI_LINE__))


#define __HAL_ETH_WAKEUP_EXTI_GET_FLAG(__EXTI_LINE__)  (EXTI_D1->PR3 & (__EXTI_LINE__))


#define __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI_D1->PR3 = (__EXTI_LINE__))


#if defined(DUAL_CORE)

#define __HAL_ETH_WAKEUP_EXTID2_ENABLE_IT(__EXTI_LINE__)   (EXTI_D2->IMR3 |= (__EXTI_LINE__))


#define __HAL_ETH_WAKEUP_EXTID2_GET_FLAG(__EXTI_LINE__)  (EXTI_D2->PR3 & (__EXTI_LINE__))


#define __HAL_ETH_WAKEUP_EXTID2_CLEAR_FLAG(__EXTI_LINE__) (EXTI_D2->PR3 = (__EXTI_LINE__))

#endif /* DUAL_CORE */


#define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE(__EXTI_LINE__) (EXTI->FTSR3 &= ~(__EXTI_LINE__)); \

  (EXTI->RTSR3 |= (__EXTI_LINE__))


#define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE(__EXTI_LINE__) (EXTI->RTSR3 &= ~(__EXTI_LINE__));\

  (EXTI->FTSR3 |= (__EXTI_LINE__))


#define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE(__EXTI_LINE__) (EXTI->RTSR3 |= (__EXTI_LINE__));\

  (EXTI->FTSR3 |= (__EXTI_LINE__))


#define __HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER3 |= (__EXTI_LINE__))

#define __HAL_ETH_GET_PTP_CONTROL(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->MACTSCR) & \

                                                           (__FLAG__)) == (__FLAG__)) ? SET : RESET)

#define __HAL_ETH_SET_PTP_CONTROL(__HANDLE__, __FLAG__)   ((__HANDLE__)->Instance->MACTSCR |= (__FLAG__))


/* Include ETH HAL Extension module */

#include "stm32h7xx_hal_eth_ex.h"


/* Exported functions --------------------------------------------------------*/


/* Initialization and de initialization functions  **********************************/

HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth);

HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth);

void              HAL_ETH_MspInit(ETH_HandleTypeDef *heth);

void              HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth);


/* Callbacks Register/UnRegister functions  ***********************************/

#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)

HAL_StatusTypeDef HAL_ETH_RegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID,

                                           pETH_CallbackTypeDef pCallback);

HAL_StatusTypeDef HAL_ETH_UnRegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID);

#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */


/* IO operation functions *******************************************************/

HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth);

HAL_StatusTypeDef HAL_ETH_Start_IT(ETH_HandleTypeDef *heth);

HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth);

HAL_StatusTypeDef HAL_ETH_Stop_IT(ETH_HandleTypeDef *heth);


HAL_StatusTypeDef HAL_ETH_ReadData(ETH_HandleTypeDef *heth, void **pAppBuff);

HAL_StatusTypeDef HAL_ETH_RegisterRxAllocateCallback(ETH_HandleTypeDef *heth,

                                                     pETH_rxAllocateCallbackTypeDef rxAllocateCallback);

HAL_StatusTypeDef HAL_ETH_UnRegisterRxAllocateCallback(ETH_HandleTypeDef *heth);

HAL_StatusTypeDef HAL_ETH_RegisterRxLinkCallback(ETH_HandleTypeDef *heth, pETH_rxLinkCallbackTypeDef rxLinkCallback);

HAL_StatusTypeDef HAL_ETH_UnRegisterRxLinkCallback(ETH_HandleTypeDef *heth);

HAL_StatusTypeDef HAL_ETH_GetRxDataErrorCode(const ETH_HandleTypeDef *heth, uint32_t *pErrorCode);

HAL_StatusTypeDef HAL_ETH_RegisterTxFreeCallback(ETH_HandleTypeDef *heth, pETH_txFreeCallbackTypeDef txFreeCallback);

HAL_StatusTypeDef HAL_ETH_UnRegisterTxFreeCallback(ETH_HandleTypeDef *heth);

HAL_StatusTypeDef HAL_ETH_ReleaseTxPacket(ETH_HandleTypeDef *heth);


#ifdef HAL_ETH_USE_PTP

HAL_StatusTypeDef HAL_ETH_PTP_SetConfig(ETH_HandleTypeDef *heth, ETH_PTP_ConfigTypeDef *ptpconfig);

HAL_StatusTypeDef HAL_ETH_PTP_GetConfig(ETH_HandleTypeDef *heth, ETH_PTP_ConfigTypeDef *ptpconfig);

HAL_StatusTypeDef HAL_ETH_PTP_SetTime(ETH_HandleTypeDef *heth, ETH_TimeTypeDef *time);

HAL_StatusTypeDef HAL_ETH_PTP_GetTime(ETH_HandleTypeDef *heth, ETH_TimeTypeDef *time);

HAL_StatusTypeDef HAL_ETH_PTP_AddTimeOffset(ETH_HandleTypeDef *heth, ETH_PtpUpdateTypeDef ptpoffsettype,

                                            ETH_TimeTypeDef *timeoffset);

HAL_StatusTypeDef HAL_ETH_PTP_InsertTxTimestamp(ETH_HandleTypeDef *heth);

HAL_StatusTypeDef HAL_ETH_PTP_GetTxTimestamp(ETH_HandleTypeDef *heth, ETH_TimeStampTypeDef *timestamp);

HAL_StatusTypeDef HAL_ETH_PTP_GetRxTimestamp(ETH_HandleTypeDef *heth, ETH_TimeStampTypeDef *timestamp);

HAL_StatusTypeDef HAL_ETH_RegisterTxPtpCallback(ETH_HandleTypeDef *heth, pETH_txPtpCallbackTypeDef txPtpCallback);

HAL_StatusTypeDef HAL_ETH_UnRegisterTxPtpCallback(ETH_HandleTypeDef *heth);

#endif /* HAL_ETH_USE_PTP */


HAL_StatusTypeDef HAL_ETH_Transmit(ETH_HandleTypeDef *heth, ETH_TxPacketConfigTypeDef *pTxConfig, uint32_t Timeout);

HAL_StatusTypeDef HAL_ETH_Transmit_IT(ETH_HandleTypeDef *heth, ETH_TxPacketConfigTypeDef *pTxConfig);


HAL_StatusTypeDef HAL_ETH_WritePHYRegister(const ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg,

                                           uint32_t RegValue);

HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg,

                                          uint32_t *pRegValue);


void              HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth);

void              HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth);

void              HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth);

void              HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth);

void              HAL_ETH_PMTCallback(ETH_HandleTypeDef *heth);

void              HAL_ETH_EEECallback(ETH_HandleTypeDef *heth);

void              HAL_ETH_WakeUpCallback(ETH_HandleTypeDef *heth);

void              HAL_ETH_RxAllocateCallback(uint8_t **buff);

void              HAL_ETH_RxLinkCallback(void **pStart, void **pEnd, uint8_t *buff, uint16_t Length);

void              HAL_ETH_TxFreeCallback(uint32_t *buff);

void              HAL_ETH_TxPtpCallback(uint32_t *buff, ETH_TimeStampTypeDef *timestamp);

/* Peripheral Control functions  **********************************************/

/* MAC & DMA Configuration APIs  **********************************************/

HAL_StatusTypeDef HAL_ETH_GetMACConfig(const ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf);

HAL_StatusTypeDef HAL_ETH_GetDMAConfig(const ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf);

HAL_StatusTypeDef HAL_ETH_SetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf);

HAL_StatusTypeDef HAL_ETH_SetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf);

void              HAL_ETH_SetMDIOClockRange(ETH_HandleTypeDef *heth);


/* MAC VLAN Processing APIs    ************************************************/

void              HAL_ETH_SetRxVLANIdentifier(ETH_HandleTypeDef *heth, uint32_t ComparisonBits,

                                              uint32_t VLANIdentifier);


/* MAC L2 Packet Filtering APIs  **********************************************/

HAL_StatusTypeDef HAL_ETH_GetMACFilterConfig(const ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig);

HAL_StatusTypeDef HAL_ETH_SetMACFilterConfig(ETH_HandleTypeDef *heth, const ETH_MACFilterConfigTypeDef *pFilterConfig);

HAL_StatusTypeDef HAL_ETH_SetHashTable(ETH_HandleTypeDef *heth, uint32_t *pHashTable);

HAL_StatusTypeDef HAL_ETH_SetSourceMACAddrMatch(const ETH_HandleTypeDef *heth, uint32_t AddrNbr,

                                                const uint8_t *pMACAddr);


/* MAC Power Down APIs    *****************************************************/

void              HAL_ETH_EnterPowerDownMode(ETH_HandleTypeDef *heth,

                                             const ETH_PowerDownConfigTypeDef *pPowerDownConfig);

void              HAL_ETH_ExitPowerDownMode(ETH_HandleTypeDef *heth);

HAL_StatusTypeDef HAL_ETH_SetWakeUpFilter(ETH_HandleTypeDef *heth, uint32_t *pFilter, uint32_t Count);


/* Peripheral State functions  **************************************************/

HAL_ETH_StateTypeDef HAL_ETH_GetState(const ETH_HandleTypeDef *heth);

uint32_t             HAL_ETH_GetError(const ETH_HandleTypeDef *heth);

uint32_t             HAL_ETH_GetDMAError(const ETH_HandleTypeDef *heth);

uint32_t             HAL_ETH_GetMACError(const ETH_HandleTypeDef *heth);

uint32_t             HAL_ETH_GetMACWakeUpSource(const ETH_HandleTypeDef *heth);

#endif /* ETH */


#ifdef __cplusplus

}

#endif


#endif /* STM32H7xx_HAL_ETH_H */

__IO
#define __IO
Definition: core_cm4.h:239

stm32h7xx_hal_def.h
This file contains HAL common defines, enumeration, macros and structures definitions.

HAL_StatusTypeDef
HAL_StatusTypeDef
HAL Status structures definition.
Definition: stm32h7xx_hal_def.h:47

stm32h7xx_hal_eth_ex.h
Header file of ETH HAL Extended module.

ETH_TypeDef
Ethernet MAC.
Definition: stm32h723xx.h:717