RTEMS 6.1-rc5
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stm32h7xx_hal_dts.h
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1
19/* Define to prevent recursive inclusion -------------------------------------*/
20#ifndef __STM32H7xx_HAL_DTS_H
21#define __STM32H7xx_HAL_DTS_H
22
23#ifdef __cplusplus
24extern "C" {
25#endif
26
27
28/* Includes ------------------------------------------------------------------*/
29#include "stm32h7xx_hal_def.h"
30
31
35#if defined(DTS)
40/* Exported types ------------------------------------------------------------*/
49typedef struct
50{
51 uint32_t QuickMeasure;
54 uint32_t RefClock;
57 uint32_t TriggerInput;
60 uint32_t SamplingTime;
63 uint32_t Divider;
66 uint32_t HighThreshold;
68 uint32_t LowThreshold;
70} DTS_InitTypeDef;
71
75typedef enum
76{
77 HAL_DTS_STATE_RESET = 0x00UL,
78 HAL_DTS_STATE_READY = 0x01UL,
79 HAL_DTS_STATE_BUSY = 0x02UL,
80 HAL_DTS_STATE_TIMEOUT = 0x03UL,
81 HAL_DTS_STATE_ERROR = 0x04UL
82} HAL_DTS_StateTypeDef;
83
87#if (USE_HAL_DTS_REGISTER_CALLBACKS == 1)
88typedef struct __DTS_HandleTypeDef
89#else
90typedef struct
91#endif /* USE_HAL_DTS_REGISTER_CALLBACKS */
92{
93 DTS_TypeDef *Instance;
94 DTS_InitTypeDef Init;
95 HAL_LockTypeDef Lock;
96 __IO HAL_DTS_StateTypeDef State;
97#if (USE_HAL_DTS_REGISTER_CALLBACKS == 1)
98 void (* MspInitCallback)(struct __DTS_HandleTypeDef *hdts);
99 void (* MspDeInitCallback)(struct __DTS_HandleTypeDef *hdts);
100 void (* EndCallback)(struct __DTS_HandleTypeDef *hdts);
101 void (* LowCallback)(struct __DTS_HandleTypeDef *hdts);
102 void (* HighCallback)(struct __DTS_HandleTypeDef *hdts);
103 void (* AsyncEndCallback)(struct __DTS_HandleTypeDef *hdts);
104 void (* AsyncLowCallback)(struct __DTS_HandleTypeDef *hdts);
105 void (* AsyncHighCallback)(struct __DTS_HandleTypeDef *hdts);
106#endif /* USE_HAL_DTS_REGISTER_CALLBACKS */
107} DTS_HandleTypeDef;
108
109#if (USE_HAL_DTS_REGISTER_CALLBACKS == 1)
113typedef enum
114{
115 HAL_DTS_MEAS_COMPLETE_CB_ID = 0x00U,
116 HAL_DTS_ASYNC_MEAS_COMPLETE_CB_ID = 0x01U,
117 HAL_DTS_LOW_THRESHOLD_CB_ID = 0x02U,
118 HAL_DTS_ASYNC_LOW_THRESHOLD_CB_ID = 0x03U,
119 HAL_DTS_HIGH_THRESHOLD_CB_ID = 0x04U,
120 HAL_DTS_ASYNC_HIGH_THRESHOLD_CB_ID = 0x05U,
121 HAL_DTS_MSPINIT_CB_ID = 0x06U,
122 HAL_DTS_MSPDEINIT_CB_ID = 0x07U
123} HAL_DTS_CallbackIDTypeDef;
124
128typedef void (*pDTS_CallbackTypeDef)(DTS_HandleTypeDef *hdts);
129#endif /* USE_HAL_DTS_REGISTER_CALLBACKS */
130
135/* Exported constants --------------------------------------------------------*/
145/* @brief No Hardware trigger detection */
146#define DTS_TRIGGER_HW_NONE (0UL)
147
148/* @brief External Interrupt Mode with LPTIMER1 trigger detection */
149#define DTS_TRIGGER_LPTIMER1 DTS_CFGR1_TS1_INTRIG_SEL_0
150
151/* @brief External Interrupt Mode with LPTIMER2 trigger detection */
152#define DTS_TRIGGER_LPTIMER2 DTS_CFGR1_TS1_INTRIG_SEL_1
153
154/* @brief External Interrupt Mode with LPTIMER3 trigger detection */
155#define DTS_TRIGGER_LPTIMER3 (DTS_CFGR1_TS1_INTRIG_SEL_0 | DTS_CFGR1_TS1_INTRIG_SEL_1)
156
157/* @brief External Interrupt Mode with EXTI13 trigger detection */
158#define DTS_TRIGGER_EXTI13 DTS_CFGR1_TS1_INTRIG_SEL_2
167#define DTS_QUICKMEAS_ENABLE DTS_CFGR1_Q_MEAS_OPT
168#define DTS_QUICKMEAS_DISABLE (0x0UL)
177#define DTS_REFCLKSEL_LSE DTS_CFGR1_REFCLK_SEL
178#define DTS_REFCLKSEL_PCLK (0UL)
187#define DTS_SMP_TIME_1_CYCLE DTS_CFGR1_TS1_SMP_TIME_0
188#define DTS_SMP_TIME_2_CYCLE DTS_CFGR1_TS1_SMP_TIME_1
189#define DTS_SMP_TIME_3_CYCLE (DTS_CFGR1_TS1_SMP_TIME_0 | DTS_CFGR1_TS1_SMP_TIME_1)
190#define DTS_SMP_TIME_4_CYCLE (DTS_CFGR1_TS1_SMP_TIME_2)
191#define DTS_SMP_TIME_5_CYCLE (DTS_CFGR1_TS1_SMP_TIME_0 | DTS_CFGR1_TS1_SMP_TIME_2)
192#define DTS_SMP_TIME_6_CYCLE (DTS_CFGR1_TS1_SMP_TIME_1 | DTS_CFGR1_TS1_SMP_TIME_2)
193#define DTS_SMP_TIME_7_CYCLE (DTS_CFGR1_TS1_SMP_TIME_0 | DTS_CFGR1_TS1_SMP_TIME_1 | DTS_CFGR1_TS1_SMP_TIME_2)
194#define DTS_SMP_TIME_8_CYCLE (DTS_CFGR1_TS1_SMP_TIME_3)
195#define DTS_SMP_TIME_9_CYCLE (DTS_CFGR1_TS1_SMP_TIME_0 | DTS_CFGR1_TS1_SMP_TIME_3)
196#define DTS_SMP_TIME_10_CYCLE (DTS_CFGR1_TS1_SMP_TIME_1 | DTS_CFGR1_TS1_SMP_TIME_3)
197#define DTS_SMP_TIME_11_CYCLE (DTS_CFGR1_TS1_SMP_TIME_0 | DTS_CFGR1_TS1_SMP_TIME_1 | DTS_CFGR1_TS1_SMP_TIME_3)
198#define DTS_SMP_TIME_12_CYCLE (DTS_CFGR1_TS1_SMP_TIME_2 | DTS_CFGR1_TS1_SMP_TIME_3)
199#define DTS_SMP_TIME_13_CYCLE (DTS_CFGR1_TS1_SMP_TIME_0 | DTS_CFGR1_TS1_SMP_TIME_2 | DTS_CFGR1_TS1_SMP_TIME_3)
200#define DTS_SMP_TIME_14_CYCLE (DTS_CFGR1_TS1_SMP_TIME_1 | DTS_CFGR1_TS1_SMP_TIME_2 | DTS_CFGR1_TS1_SMP_TIME_3)
201#define DTS_SMP_TIME_15_CYCLE (DTS_CFGR1_TS1_SMP_TIME_0 | DTS_CFGR1_TS1_SMP_TIME_1 | DTS_CFGR1_TS1_SMP_TIME_2 | DTS_CFGR1_TS1_SMP_TIME_3)
209#define DTS_FLAG_TS1_ITE DTS_SR_TS1_ITEF
210#define DTS_FLAG_TS1_ITL DTS_SR_TS1_ITLF
211#define DTS_FLAG_TS1_ITH DTS_SR_TS1_ITHF
212#define DTS_FLAG_TS1_AITE DTS_SR_TS1_AITEF
213#define DTS_FLAG_TS1_AITL DTS_SR_TS1_AITLF
214#define DTS_FLAG_TS1_AITH DTS_SR_TS1_AITHF
215#define DTS_FLAG_TS1_RDY DTS_SR_TS1_RDY
224#define DTS_IT_TS1_ITE DTS_ITENR_TS1_ITEEN
225#define DTS_IT_TS1_ITL DTS_ITENR_TS1_ITLEN
226#define DTS_IT_TS1_ITH DTS_ITENR_TS1_ITHEN
227#define DTS_IT_TS1_AITE DTS_ITENR_TS1_AITEEN
228#define DTS_IT_TS1_AITL DTS_ITENR_TS1_AITLEN
229#define DTS_IT_TS1_AITH DTS_ITENR_TS1_AITHEN
237/* Exported macros -----------------------------------------------------------*/
247#if (USE_HAL_DTS_REGISTER_CALLBACKS == 1)
248#define __HAL_DTS_RESET_HANDLE_STATE(__HANDLE__) do{ \
249 (__HANDLE__)->State = HAL_DTS_STATE_RESET; \
250 (__HANDLE__)->MspInitCallback = NULL; \
251 (__HANDLE__)->MspDeInitCallback = NULL; \
252 } while(0)
253#else /* USE_HAL_DTS_REGISTER_CALLBACKS */
254#define __HAL_DTS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DTS_STATE_RESET)
255#endif /* USE_HAL_DTS_REGISTER_CALLBACKS */
256
262#define __HAL_DTS_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CFGR1, DTS_CFGR1_TS1_EN)
263
269#define __HAL_DTS_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CFGR1, DTS_CFGR1_TS1_EN)
270
275#define __HAL_DTS_EXTI_WAKEUP_ENABLE_IT() SET_BIT(EXTI->IMR3, DTS_EXTI_LINE_DTS1)
276
281#define __HAL_DTS_EXTI_WAKEUP_DISABLE_IT() CLEAR_BIT(EXTI->IMR3, DTS_EXTI_LINE_DTS1)
282
287#define __HAL_DTS_EXTI_WAKEUP_ENABLE_EVENT() SET_BIT(EXTI->EMR3, DTS_EXTI_LINE_DTS1)
288
293#define __HAL_DTS_EXTI_WAKEUP_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR3, DTS_EXTI_LINE_DTS1)
294
308#define __HAL_DTS_GET_FLAG(__HANDLE__, __FLAG__) \
309 (((((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__)))? SET : RESET)
310
311
324#define __HAL_DTS_CLEAR_FLAG(__HANDLE__, __FLAG__) \
325 ((__HANDLE__)->Instance->ICIFR = (__FLAG__))
326
327
340#define __HAL_DTS_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
341 SET_BIT((__HANDLE__)->Instance->ITENR, __INTERRUPT__)
342
343
356#define __HAL_DTS_DISABLE_IT(__HANDLE__,__INTERRUPT__) \
357 CLEAR_BIT((__HANDLE__)->Instance->ITENR, __INTERRUPT__)
358
359
372#define __HAL_DTS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
373 (( ((__HANDLE__)->Instance->ITENR & (__INTERRUPT__)) == (__INTERRUPT__) \
374 )? SET : RESET)
375
376
385#define __HAL_DTS_GET_REFCLK(__HANDLE__, __REFCLK__) ((((__HANDLE__)->Instance->CFGR1 & (__REFCLK__)) == (__REFCLK__))? SET : RESET)
386
396#define __HAL_DTS_GET_TRIGGER(__HANDLE__) ((__HANDLE__)->Instance->CFGR1 & (DTS_CFGR1_TS1_INTRIG_SEL))
401/* Exported functions --------------------------------------------------------*/
409/* Initialization and de-initialization functions **********************************/
410HAL_StatusTypeDef HAL_DTS_Init(DTS_HandleTypeDef *hdts);
411HAL_StatusTypeDef HAL_DTS_DeInit(DTS_HandleTypeDef *hdts);
412void HAL_DTS_MspInit(DTS_HandleTypeDef *hdts);
413void HAL_DTS_MspDeInit(DTS_HandleTypeDef *hdts);
414#if (USE_HAL_DTS_REGISTER_CALLBACKS == 1)
415HAL_StatusTypeDef HAL_DTS_RegisterCallback(DTS_HandleTypeDef *hdts,
416 HAL_DTS_CallbackIDTypeDef CallbackID,
417 pDTS_CallbackTypeDef pCallback);
418HAL_StatusTypeDef HAL_DTS_UnRegisterCallback(DTS_HandleTypeDef *hdts,
419 HAL_DTS_CallbackIDTypeDef CallbackID);
420#endif /* USE_HAL_DTS_REGISTER_CALLBACKS */
425/* IO operation functions *****************************************************/
429HAL_StatusTypeDef HAL_DTS_Start(DTS_HandleTypeDef *hdts);
430HAL_StatusTypeDef HAL_DTS_Stop(DTS_HandleTypeDef *hdts);
431HAL_StatusTypeDef HAL_DTS_GetTemperature(DTS_HandleTypeDef *hdts, int32_t *Temperature);
432HAL_StatusTypeDef HAL_DTS_Start_IT(DTS_HandleTypeDef *hdts);
433HAL_StatusTypeDef HAL_DTS_Stop_IT(DTS_HandleTypeDef *hdts);
434void HAL_DTS_IRQHandler(DTS_HandleTypeDef *hdts);
435HAL_DTS_StateTypeDef HAL_DTS_GetState(DTS_HandleTypeDef *hdts);
436/* Callback in Interrupt mode */
437void HAL_DTS_EndCallback(DTS_HandleTypeDef *hdts);
438void HAL_DTS_LowCallback(DTS_HandleTypeDef *hdts);
439void HAL_DTS_HighCallback(DTS_HandleTypeDef *hdts);
440void HAL_DTS_AsyncEndCallback(DTS_HandleTypeDef *hdts);
441void HAL_DTS_AsyncLowCallback(DTS_HandleTypeDef *hdts);
442void HAL_DTS_AsyncHighCallback(DTS_HandleTypeDef *hdts);
450/* Private types -------------------------------------------------------------*/
451/* Private constants ---------------------------------------------------------*/
460#define DTS_EXTI_LINE_DTS1 (EXTI_IMR3_IM88)
468/* Private macros ------------------------------------------------------------*/
478#define IS_DTS_QUICKMEAS(__SEL__) (((__SEL__) == DTS_QUICKMEAS_DISABLE) || \
479 ((__SEL__) == DTS_QUICKMEAS_ENABLE))
480
481#define IS_DTS_REFCLK(__SEL__) (((__SEL__) == DTS_REFCLKSEL_LSE) || \
482 ((__SEL__) == DTS_REFCLKSEL_PCLK))
483
484#define IS_DTS_TRIGGERINPUT(__INPUT__) (((__INPUT__) == DTS_TRIGGER_HW_NONE) || \
485 ((__INPUT__) == DTS_TRIGGER_LPTIMER1) || \
486 ((__INPUT__) == DTS_TRIGGER_LPTIMER2) || \
487 ((__INPUT__) == DTS_TRIGGER_LPTIMER3) || \
488 ((__INPUT__) == DTS_TRIGGER_EXTI13))
489
490#define IS_DTS_THRESHOLD(__THRESHOLD__) ((__THRESHOLD__) <= 0xFFFFUL)
491
492#define IS_DTS_DIVIDER_RATIO_NUMBER(__NUMBER__) ((__NUMBER__) <= 127UL)
493
494#define IS_DTS_SAMPLINGTIME(__CYCLE__) (((__CYCLE__) == DTS_SMP_TIME_1_CYCLE) || \
495 ((__CYCLE__) == DTS_SMP_TIME_2_CYCLE) || \
496 ((__CYCLE__) == DTS_SMP_TIME_3_CYCLE) || \
497 ((__CYCLE__) == DTS_SMP_TIME_4_CYCLE) || \
498 ((__CYCLE__) == DTS_SMP_TIME_5_CYCLE) || \
499 ((__CYCLE__) == DTS_SMP_TIME_6_CYCLE) || \
500 ((__CYCLE__) == DTS_SMP_TIME_7_CYCLE) || \
501 ((__CYCLE__) == DTS_SMP_TIME_8_CYCLE) || \
502 ((__CYCLE__) == DTS_SMP_TIME_9_CYCLE) || \
503 ((__CYCLE__) == DTS_SMP_TIME_10_CYCLE) || \
504 ((__CYCLE__) == DTS_SMP_TIME_11_CYCLE) || \
505 ((__CYCLE__) == DTS_SMP_TIME_12_CYCLE) || \
506 ((__CYCLE__) == DTS_SMP_TIME_13_CYCLE) || \
507 ((__CYCLE__) == DTS_SMP_TIME_14_CYCLE) || \
508 ((__CYCLE__) == DTS_SMP_TIME_15_CYCLE))
509
518/* Private functions ---------------------------------------------------------*/
519
528#endif /* DTS */
529
530#ifdef __cplusplus
531}
532#endif
533
534#endif /* __STM32H7xx_HAL_DTS_H */
535
__IO
#define __IO
Definition: core_cm4.h:239
stm32h7xx_hal_def.h
This file contains HAL common defines, enumeration, macros and structures definitions.
HAL_StatusTypeDef
HAL_StatusTypeDef
HAL Status structures definition.
Definition: stm32h7xx_hal_def.h:47
HAL_LockTypeDef
HAL_LockTypeDef
HAL Lock structures definition.
Definition: stm32h7xx_hal_def.h:58
DTS_TypeDef
DTS.
Definition: stm32h723xx.h:1504
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