RTEMS 6.1-rc5
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stm32h7xx_hal_dsi.h
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1
19/* Define to prevent recursive inclusion -------------------------------------*/
20#ifndef STM32H7xx_HAL_DSI_H
21#define STM32H7xx_HAL_DSI_H
22
23#ifdef __cplusplus
24extern "C" {
25#endif
26
27/* Includes ------------------------------------------------------------------*/
28#include "stm32h7xx_hal_def.h"
29
30#if defined(DSI)
31
42/* Exported types ------------------------------------------------------------*/
50typedef struct
51{
52 uint32_t AutomaticClockLaneControl;
55 uint32_t TXEscapeCkdiv;
58 uint32_t NumberOfLanes;
61} DSI_InitTypeDef;
62
66typedef struct
67{
68 uint32_t PLLNDIV;
71 uint32_t PLLIDF;
74 uint32_t PLLODF;
77} DSI_PLLInitTypeDef;
78
82typedef struct
83{
84 uint32_t VirtualChannelID;
86 uint32_t ColorCoding;
89 uint32_t LooselyPacked;
93 uint32_t Mode;
96 uint32_t PacketSize;
98 uint32_t NumberOfChunks;
100 uint32_t NullPacketSize;
102 uint32_t HSPolarity;
105 uint32_t VSPolarity;
108 uint32_t DEPolarity;
111 uint32_t HorizontalSyncActive;
113 uint32_t HorizontalBackPorch;
115 uint32_t HorizontalLine;
117 uint32_t VerticalSyncActive;
119 uint32_t VerticalBackPorch;
121 uint32_t VerticalFrontPorch;
123 uint32_t VerticalActive;
125 uint32_t LPCommandEnable;
128 uint32_t LPLargestPacketSize;
131 uint32_t LPVACTLargestPacketSize;
134 uint32_t LPHorizontalFrontPorchEnable;
137 uint32_t LPHorizontalBackPorchEnable;
140 uint32_t LPVerticalActiveEnable;
143 uint32_t LPVerticalFrontPorchEnable;
146 uint32_t LPVerticalBackPorchEnable;
149 uint32_t LPVerticalSyncActiveEnable;
152 uint32_t FrameBTAAcknowledgeEnable;
155} DSI_VidCfgTypeDef;
156
160typedef struct
161{
162 uint32_t VirtualChannelID;
164 uint32_t ColorCoding;
167 uint32_t CommandSize;
170 uint32_t TearingEffectSource;
173 uint32_t TearingEffectPolarity;
176 uint32_t HSPolarity;
179 uint32_t VSPolarity;
182 uint32_t DEPolarity;
185 uint32_t VSyncPol;
188 uint32_t AutomaticRefresh;
191 uint32_t TEAcknowledgeRequest;
194} DSI_CmdCfgTypeDef;
195
199typedef struct
200{
201 uint32_t LPGenShortWriteNoP;
204 uint32_t LPGenShortWriteOneP;
207 uint32_t LPGenShortWriteTwoP;
210 uint32_t LPGenShortReadNoP;
213 uint32_t LPGenShortReadOneP;
216 uint32_t LPGenShortReadTwoP;
219 uint32_t LPGenLongWrite;
222 uint32_t LPDcsShortWriteNoP;
225 uint32_t LPDcsShortWriteOneP;
228 uint32_t LPDcsShortReadNoP;
231 uint32_t LPDcsLongWrite;
234 uint32_t LPMaxReadPacket;
237 uint32_t AcknowledgeRequest;
240} DSI_LPCmdTypeDef;
241
245typedef struct
246{
247 uint32_t ClockLaneHS2LPTime;
250 uint32_t ClockLaneLP2HSTime;
253 uint32_t DataLaneHS2LPTime;
256 uint32_t DataLaneLP2HSTime;
259 uint32_t DataLaneMaxReadTime;
261 uint32_t StopWaitTime;
264} DSI_PHY_TimerTypeDef;
265
269typedef struct
270{
271 uint32_t TimeoutCkdiv;
273 uint32_t HighSpeedTransmissionTimeout;
275 uint32_t LowPowerReceptionTimeout;
277 uint32_t HighSpeedReadTimeout;
279 uint32_t LowPowerReadTimeout;
281 uint32_t HighSpeedWriteTimeout;
283 uint32_t HighSpeedWritePrespMode;
286 uint32_t LowPowerWriteTimeout;
288 uint32_t BTATimeout;
290} DSI_HOST_TimeoutTypeDef;
291
295typedef enum
296{
297 HAL_DSI_STATE_RESET = 0x00U,
298 HAL_DSI_STATE_READY = 0x01U,
299 HAL_DSI_STATE_ERROR = 0x02U,
300 HAL_DSI_STATE_BUSY = 0x03U,
301 HAL_DSI_STATE_TIMEOUT = 0x04U
302} HAL_DSI_StateTypeDef;
303
307#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
308typedef struct __DSI_HandleTypeDef
309#else
310typedef struct
311#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
312{
313 DSI_TypeDef *Instance;
314 DSI_InitTypeDef Init;
315 HAL_LockTypeDef Lock;
316 __IO HAL_DSI_StateTypeDef State;
317 __IO uint32_t ErrorCode;
318 uint32_t ErrorMsk;
320#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
321 void (* TearingEffectCallback)(struct __DSI_HandleTypeDef *hdsi);
322 void (* EndOfRefreshCallback)(struct __DSI_HandleTypeDef *hdsi);
323 void (* ErrorCallback)(struct __DSI_HandleTypeDef *hdsi);
325 void (* MspInitCallback)(struct __DSI_HandleTypeDef *hdsi);
326 void (* MspDeInitCallback)(struct __DSI_HandleTypeDef *hdsi);
328#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
329
330} DSI_HandleTypeDef;
331
332#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
336typedef enum
337{
338 HAL_DSI_MSPINIT_CB_ID = 0x00U,
339 HAL_DSI_MSPDEINIT_CB_ID = 0x01U,
341 HAL_DSI_TEARING_EFFECT_CB_ID = 0x02U,
342 HAL_DSI_ENDOF_REFRESH_CB_ID = 0x03U,
343 HAL_DSI_ERROR_CB_ID = 0x04U
345} HAL_DSI_CallbackIDTypeDef;
346
350typedef void (*pDSI_CallbackTypeDef)(DSI_HandleTypeDef *hdsi);
352#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
357/* Exported constants --------------------------------------------------------*/
366#define DSI_ENTER_IDLE_MODE 0x39U
367#define DSI_ENTER_INVERT_MODE 0x21U
368#define DSI_ENTER_NORMAL_MODE 0x13U
369#define DSI_ENTER_PARTIAL_MODE 0x12U
370#define DSI_ENTER_SLEEP_MODE 0x10U
371#define DSI_EXIT_IDLE_MODE 0x38U
372#define DSI_EXIT_INVERT_MODE 0x20U
373#define DSI_EXIT_SLEEP_MODE 0x11U
374#define DSI_GET_3D_CONTROL 0x3FU
375#define DSI_GET_ADDRESS_MODE 0x0BU
376#define DSI_GET_BLUE_CHANNEL 0x08U
377#define DSI_GET_DIAGNOSTIC_RESULT 0x0FU
378#define DSI_GET_DISPLAY_MODE 0x0DU
379#define DSI_GET_GREEN_CHANNEL 0x07U
380#define DSI_GET_PIXEL_FORMAT 0x0CU
381#define DSI_GET_POWER_MODE 0x0AU
382#define DSI_GET_RED_CHANNEL 0x06U
383#define DSI_GET_SCANLINE 0x45U
384#define DSI_GET_SIGNAL_MODE 0x0EU
385#define DSI_NOP 0x00U
386#define DSI_READ_DDB_CONTINUE 0xA8U
387#define DSI_READ_DDB_START 0xA1U
388#define DSI_READ_MEMORY_CONTINUE 0x3EU
389#define DSI_READ_MEMORY_START 0x2EU
390#define DSI_SET_3D_CONTROL 0x3DU
391#define DSI_SET_ADDRESS_MODE 0x36U
392#define DSI_SET_COLUMN_ADDRESS 0x2AU
393#define DSI_SET_DISPLAY_OFF 0x28U
394#define DSI_SET_DISPLAY_ON 0x29U
395#define DSI_SET_GAMMA_CURVE 0x26U
396#define DSI_SET_PAGE_ADDRESS 0x2BU
397#define DSI_SET_PARTIAL_COLUMNS 0x31U
398#define DSI_SET_PARTIAL_ROWS 0x30U
399#define DSI_SET_PIXEL_FORMAT 0x3AU
400#define DSI_SET_SCROLL_AREA 0x33U
401#define DSI_SET_SCROLL_START 0x37U
402#define DSI_SET_TEAR_OFF 0x34U
403#define DSI_SET_TEAR_ON 0x35U
404#define DSI_SET_TEAR_SCANLINE 0x44U
405#define DSI_SET_VSYNC_TIMING 0x40U
406#define DSI_SOFT_RESET 0x01U
407#define DSI_WRITE_LUT 0x2DU
408#define DSI_WRITE_MEMORY_CONTINUE 0x3CU
409#define DSI_WRITE_MEMORY_START 0x2CU
418#define DSI_VID_MODE_NB_PULSES 0U
419#define DSI_VID_MODE_NB_EVENTS 1U
420#define DSI_VID_MODE_BURST 2U
429#define DSI_COLOR_MODE_FULL 0x00000000U
430#define DSI_COLOR_MODE_EIGHT DSI_WCR_COLM
439#define DSI_DISPLAY_ON 0x00000000U
440#define DSI_DISPLAY_OFF DSI_WCR_SHTDN
449#define DSI_LP_COMMAND_DISABLE 0x00000000U
450#define DSI_LP_COMMAND_ENABLE DSI_VMCR_LPCE
459#define DSI_LP_HFP_DISABLE 0x00000000U
460#define DSI_LP_HFP_ENABLE DSI_VMCR_LPHFPE
469#define DSI_LP_HBP_DISABLE 0x00000000U
470#define DSI_LP_HBP_ENABLE DSI_VMCR_LPHBPE
479#define DSI_LP_VACT_DISABLE 0x00000000U
480#define DSI_LP_VACT_ENABLE DSI_VMCR_LPVAE
489#define DSI_LP_VFP_DISABLE 0x00000000U
490#define DSI_LP_VFP_ENABLE DSI_VMCR_LPVFPE
499#define DSI_LP_VBP_DISABLE 0x00000000U
500#define DSI_LP_VBP_ENABLE DSI_VMCR_LPVBPE
509#define DSI_LP_VSYNC_DISABLE 0x00000000U
510#define DSI_LP_VSYNC_ENABLE DSI_VMCR_LPVSAE
519#define DSI_FBTAA_DISABLE 0x00000000U
520#define DSI_FBTAA_ENABLE DSI_VMCR_FBTAAE
529#define DSI_TE_DSILINK 0x00000000U
530#define DSI_TE_EXTERNAL DSI_WCFGR_TESRC
539#define DSI_TE_RISING_EDGE 0x00000000U
540#define DSI_TE_FALLING_EDGE DSI_WCFGR_TEPOL
549#define DSI_VSYNC_FALLING 0x00000000U
550#define DSI_VSYNC_RISING DSI_WCFGR_VSPOL
559#define DSI_AR_DISABLE 0x00000000U
560#define DSI_AR_ENABLE DSI_WCFGR_AR
569#define DSI_TE_ACKNOWLEDGE_DISABLE 0x00000000U
570#define DSI_TE_ACKNOWLEDGE_ENABLE DSI_CMCR_TEARE
579#define DSI_ACKNOWLEDGE_DISABLE 0x00000000U
580#define DSI_ACKNOWLEDGE_ENABLE DSI_CMCR_ARE
589#define DSI_LP_GSW0P_DISABLE 0x00000000U
590#define DSI_LP_GSW0P_ENABLE DSI_CMCR_GSW0TX
599#define DSI_LP_GSW1P_DISABLE 0x00000000U
600#define DSI_LP_GSW1P_ENABLE DSI_CMCR_GSW1TX
609#define DSI_LP_GSW2P_DISABLE 0x00000000U
610#define DSI_LP_GSW2P_ENABLE DSI_CMCR_GSW2TX
619#define DSI_LP_GSR0P_DISABLE 0x00000000U
620#define DSI_LP_GSR0P_ENABLE DSI_CMCR_GSR0TX
629#define DSI_LP_GSR1P_DISABLE 0x00000000U
630#define DSI_LP_GSR1P_ENABLE DSI_CMCR_GSR1TX
639#define DSI_LP_GSR2P_DISABLE 0x00000000U
640#define DSI_LP_GSR2P_ENABLE DSI_CMCR_GSR2TX
649#define DSI_LP_GLW_DISABLE 0x00000000U
650#define DSI_LP_GLW_ENABLE DSI_CMCR_GLWTX
659#define DSI_LP_DSW0P_DISABLE 0x00000000U
660#define DSI_LP_DSW0P_ENABLE DSI_CMCR_DSW0TX
669#define DSI_LP_DSW1P_DISABLE 0x00000000U
670#define DSI_LP_DSW1P_ENABLE DSI_CMCR_DSW1TX
679#define DSI_LP_DSR0P_DISABLE 0x00000000U
680#define DSI_LP_DSR0P_ENABLE DSI_CMCR_DSR0TX
689#define DSI_LP_DLW_DISABLE 0x00000000U
690#define DSI_LP_DLW_ENABLE DSI_CMCR_DLWTX
699#define DSI_LP_MRDP_DISABLE 0x00000000U
700#define DSI_LP_MRDP_ENABLE DSI_CMCR_MRDPS
709#define DSI_HS_PM_DISABLE 0x00000000U
710#define DSI_HS_PM_ENABLE DSI_TCCR3_PM
720#define DSI_AUTO_CLK_LANE_CTRL_DISABLE 0x00000000U
721#define DSI_AUTO_CLK_LANE_CTRL_ENABLE DSI_CLCR_ACR
730#define DSI_ONE_DATA_LANE 0U
731#define DSI_TWO_DATA_LANES 1U
740#define DSI_FLOW_CONTROL_CRC_RX DSI_PCR_CRCRXE
741#define DSI_FLOW_CONTROL_ECC_RX DSI_PCR_ECCRXE
742#define DSI_FLOW_CONTROL_BTA DSI_PCR_BTAE
743#define DSI_FLOW_CONTROL_EOTP_RX DSI_PCR_ETRXE
744#define DSI_FLOW_CONTROL_EOTP_TX DSI_PCR_ETTXE
745#define DSI_FLOW_CONTROL_ALL (DSI_FLOW_CONTROL_CRC_RX | DSI_FLOW_CONTROL_ECC_RX | \
746 DSI_FLOW_CONTROL_BTA | DSI_FLOW_CONTROL_EOTP_RX | \
747 DSI_FLOW_CONTROL_EOTP_TX)
756#define DSI_RGB565 0x00000000U
757#define DSI_RGB666 0x00000003U
758#define DSI_RGB888 0x00000005U
767#define DSI_LOOSELY_PACKED_ENABLE DSI_LCOLCR_LPE
768#define DSI_LOOSELY_PACKED_DISABLE 0x00000000U
777#define DSI_HSYNC_ACTIVE_HIGH 0x00000000U
778#define DSI_HSYNC_ACTIVE_LOW DSI_LPCR_HSP
787#define DSI_VSYNC_ACTIVE_HIGH 0x00000000U
788#define DSI_VSYNC_ACTIVE_LOW DSI_LPCR_VSP
797#define DSI_DATA_ENABLE_ACTIVE_HIGH 0x00000000U
798#define DSI_DATA_ENABLE_ACTIVE_LOW DSI_LPCR_DEP
807#define DSI_PLL_IN_DIV1 0x00000001U
808#define DSI_PLL_IN_DIV2 0x00000002U
809#define DSI_PLL_IN_DIV3 0x00000003U
810#define DSI_PLL_IN_DIV4 0x00000004U
811#define DSI_PLL_IN_DIV5 0x00000005U
812#define DSI_PLL_IN_DIV6 0x00000006U
813#define DSI_PLL_IN_DIV7 0x00000007U
822#define DSI_PLL_OUT_DIV1 0x00000000U
823#define DSI_PLL_OUT_DIV2 0x00000001U
824#define DSI_PLL_OUT_DIV4 0x00000002U
825#define DSI_PLL_OUT_DIV8 0x00000003U
834#define DSI_FLAG_TE DSI_WISR_TEIF
835#define DSI_FLAG_ER DSI_WISR_ERIF
836#define DSI_FLAG_BUSY DSI_WISR_BUSY
837#define DSI_FLAG_PLLLS DSI_WISR_PLLLS
838#define DSI_FLAG_PLLL DSI_WISR_PLLLIF
839#define DSI_FLAG_PLLU DSI_WISR_PLLUIF
840#define DSI_FLAG_RRS DSI_WISR_RRS
841#define DSI_FLAG_RR DSI_WISR_RRIF
850#define DSI_IT_TE DSI_WIER_TEIE
851#define DSI_IT_ER DSI_WIER_ERIE
852#define DSI_IT_PLLL DSI_WIER_PLLLIE
853#define DSI_IT_PLLU DSI_WIER_PLLUIE
854#define DSI_IT_RR DSI_WIER_RRIE
863#define DSI_DCS_SHORT_PKT_WRITE_P0 0x00000005U
864#define DSI_DCS_SHORT_PKT_WRITE_P1 0x00000015U
865#define DSI_GEN_SHORT_PKT_WRITE_P0 0x00000003U
866#define DSI_GEN_SHORT_PKT_WRITE_P1 0x00000013U
867#define DSI_GEN_SHORT_PKT_WRITE_P2 0x00000023U
876#define DSI_DCS_LONG_PKT_WRITE 0x00000039U
877#define DSI_GEN_LONG_PKT_WRITE 0x00000029U
886#define DSI_DCS_SHORT_PKT_READ 0x00000006U
887#define DSI_GEN_SHORT_PKT_READ_P0 0x00000004U
888#define DSI_GEN_SHORT_PKT_READ_P1 0x00000014U
889#define DSI_GEN_SHORT_PKT_READ_P2 0x00000024U
898#define HAL_DSI_ERROR_NONE 0U
899#define HAL_DSI_ERROR_ACK 0x00000001U
900#define HAL_DSI_ERROR_PHY 0x00000002U
901#define HAL_DSI_ERROR_TX 0x00000004U
902#define HAL_DSI_ERROR_RX 0x00000008U
903#define HAL_DSI_ERROR_ECC 0x00000010U
904#define HAL_DSI_ERROR_CRC 0x00000020U
905#define HAL_DSI_ERROR_PSE 0x00000040U
906#define HAL_DSI_ERROR_EOT 0x00000080U
907#define HAL_DSI_ERROR_OVF 0x00000100U
908#define HAL_DSI_ERROR_GEN 0x00000200U
909#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
910#define HAL_DSI_ERROR_INVALID_CALLBACK 0x00000400U
911#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
920#define DSI_CLOCK_LANE 0x00000000U
921#define DSI_DATA_LANES 0x00000001U
930#define DSI_SLEW_RATE_HSTX 0x00000000U
931#define DSI_SLEW_RATE_LPTX 0x00000001U
932#define DSI_HS_DELAY 0x00000002U
941#define DSI_SWAP_LANE_PINS 0x00000000U
942#define DSI_INVERT_HS_SIGNAL 0x00000001U
951#define DSI_CLK_LANE 0x00000000U
952#define DSI_DATA_LANE0 0x00000001U
953#define DSI_DATA_LANE1 0x00000002U
962#define DSI_TCLK_POST 0x00000000U
963#define DSI_TLPX_CLK 0x00000001U
964#define DSI_THS_EXIT 0x00000002U
965#define DSI_TLPX_DATA 0x00000003U
966#define DSI_THS_ZERO 0x00000004U
967#define DSI_THS_TRAIL 0x00000005U
968#define DSI_THS_PREPARE 0x00000006U
969#define DSI_TCLK_ZERO 0x00000007U
970#define DSI_TCLK_PREPARE 0x00000008U
980/* Exported macros -----------------------------------------------------------*/
991#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
992#define __HAL_DSI_RESET_HANDLE_STATE(__HANDLE__) do{ \
993 (__HANDLE__)->State = HAL_DSI_STATE_RESET; \
994 (__HANDLE__)->MspInitCallback = NULL; \
995 (__HANDLE__)->MspDeInitCallback = NULL; \
996 } while(0)
997#else
998#define __HAL_DSI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DSI_STATE_RESET)
999#endif /*USE_HAL_DSI_REGISTER_CALLBACKS */
1000
1006#define __HAL_DSI_ENABLE(__HANDLE__) do { \
1007 __IO uint32_t tmpreg = 0x00U; \
1008 SET_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\
1009 /* Delay after an DSI Host enabling */ \
1010 tmpreg = READ_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\
1011 UNUSED(tmpreg); \
1012 } while(0U)
1013
1019#define __HAL_DSI_DISABLE(__HANDLE__) do { \
1020 __IO uint32_t tmpreg = 0x00U; \
1021 CLEAR_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\
1022 /* Delay after an DSI Host disabling */ \
1023 tmpreg = READ_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\
1024 UNUSED(tmpreg); \
1025 } while(0U)
1026
1032#define __HAL_DSI_WRAPPER_ENABLE(__HANDLE__) do { \
1033 __IO uint32_t tmpreg = 0x00U; \
1034 SET_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\
1035 /* Delay after an DSI wrapper enabling */ \
1036 tmpreg = READ_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\
1037 UNUSED(tmpreg); \
1038 } while(0U)
1039
1045#define __HAL_DSI_WRAPPER_DISABLE(__HANDLE__) do { \
1046 __IO uint32_t tmpreg = 0x00U; \
1047 CLEAR_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\
1048 /* Delay after an DSI wrapper disabling*/ \
1049 tmpreg = READ_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\
1050 UNUSED(tmpreg); \
1051 } while(0U)
1052
1058#define __HAL_DSI_PLL_ENABLE(__HANDLE__) do { \
1059 __IO uint32_t tmpreg = 0x00U; \
1060 SET_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\
1061 /* Delay after an DSI PLL enabling */ \
1062 tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\
1063 UNUSED(tmpreg); \
1064 } while(0U)
1065
1071#define __HAL_DSI_PLL_DISABLE(__HANDLE__) do { \
1072 __IO uint32_t tmpreg = 0x00U; \
1073 CLEAR_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\
1074 /* Delay after an DSI PLL disabling */ \
1075 tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\
1076 UNUSED(tmpreg); \
1077 } while(0U)
1078
1084#define __HAL_DSI_REG_ENABLE(__HANDLE__) do { \
1085 __IO uint32_t tmpreg = 0x00U; \
1086 SET_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\
1087 /* Delay after an DSI regulator enabling */ \
1088 tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\
1089 UNUSED(tmpreg); \
1090 } while(0U)
1091
1097#define __HAL_DSI_REG_DISABLE(__HANDLE__) do { \
1098 __IO uint32_t tmpreg = 0x00U; \
1099 CLEAR_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\
1100 /* Delay after an DSI regulator disabling */ \
1101 tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\
1102 UNUSED(tmpreg); \
1103 } while(0U)
1104
1120#define __HAL_DSI_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->WISR & (__FLAG__))
1121
1134#define __HAL_DSI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->WIFCR = (__FLAG__))
1135
1148#define __HAL_DSI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->WIER |= (__INTERRUPT__))
1149
1162#define __HAL_DSI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->WIER &= ~(__INTERRUPT__))
1163
1176#define __HAL_DSI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->WIER & (__INTERRUPT__))
1177
1182/* Exported functions --------------------------------------------------------*/
1192HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLInit);
1193HAL_StatusTypeDef HAL_DSI_DeInit(DSI_HandleTypeDef *hdsi);
1194void HAL_DSI_MspInit(DSI_HandleTypeDef *hdsi);
1195void HAL_DSI_MspDeInit(DSI_HandleTypeDef *hdsi);
1196HAL_StatusTypeDef HAL_DSI_ConfigErrorMonitor(DSI_HandleTypeDef *hdsi, uint32_t ActiveErrors);
1197/* Callbacks Register/UnRegister functions ***********************************/
1198#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
1199HAL_StatusTypeDef HAL_DSI_RegisterCallback(DSI_HandleTypeDef *hdsi, HAL_DSI_CallbackIDTypeDef CallbackID,
1200 pDSI_CallbackTypeDef pCallback);
1201HAL_StatusTypeDef HAL_DSI_UnRegisterCallback(DSI_HandleTypeDef *hdsi, HAL_DSI_CallbackIDTypeDef CallbackID);
1202#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
1212void HAL_DSI_IRQHandler(DSI_HandleTypeDef *hdsi);
1213void HAL_DSI_TearingEffectCallback(DSI_HandleTypeDef *hdsi);
1214void HAL_DSI_EndOfRefreshCallback(DSI_HandleTypeDef *hdsi);
1215void HAL_DSI_ErrorCallback(DSI_HandleTypeDef *hdsi);
1225HAL_StatusTypeDef HAL_DSI_SetGenericVCID(DSI_HandleTypeDef *hdsi, uint32_t VirtualChannelID);
1226HAL_StatusTypeDef HAL_DSI_ConfigVideoMode(DSI_HandleTypeDef *hdsi, DSI_VidCfgTypeDef *VidCfg);
1227HAL_StatusTypeDef HAL_DSI_ConfigAdaptedCommandMode(DSI_HandleTypeDef *hdsi, DSI_CmdCfgTypeDef *CmdCfg);
1228HAL_StatusTypeDef HAL_DSI_ConfigCommand(DSI_HandleTypeDef *hdsi, DSI_LPCmdTypeDef *LPCmd);
1229HAL_StatusTypeDef HAL_DSI_ConfigFlowControl(DSI_HandleTypeDef *hdsi, uint32_t FlowControl);
1230HAL_StatusTypeDef HAL_DSI_ConfigPhyTimer(DSI_HandleTypeDef *hdsi, DSI_PHY_TimerTypeDef *PhyTimers);
1231HAL_StatusTypeDef HAL_DSI_ConfigHostTimeouts(DSI_HandleTypeDef *hdsi, DSI_HOST_TimeoutTypeDef *HostTimeouts);
1232HAL_StatusTypeDef HAL_DSI_Start(DSI_HandleTypeDef *hdsi);
1233HAL_StatusTypeDef HAL_DSI_Stop(DSI_HandleTypeDef *hdsi);
1234HAL_StatusTypeDef HAL_DSI_Refresh(DSI_HandleTypeDef *hdsi);
1235HAL_StatusTypeDef HAL_DSI_ColorMode(DSI_HandleTypeDef *hdsi, uint32_t ColorMode);
1236HAL_StatusTypeDef HAL_DSI_Shutdown(DSI_HandleTypeDef *hdsi, uint32_t Shutdown);
1237HAL_StatusTypeDef HAL_DSI_ShortWrite(DSI_HandleTypeDef *hdsi,
1238 uint32_t ChannelID,
1239 uint32_t Mode,
1240 uint32_t Param1,
1241 uint32_t Param2);
1242HAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi,
1243 uint32_t ChannelID,
1244 uint32_t Mode,
1245 uint32_t NbParams,
1246 uint32_t Param1,
1247 const uint8_t *ParametersTable);
1248HAL_StatusTypeDef HAL_DSI_Read(DSI_HandleTypeDef *hdsi,
1249 uint32_t ChannelNbr,
1250 uint8_t *Array,
1251 uint32_t Size,
1252 uint32_t Mode,
1253 uint32_t DCSCmd,
1254 uint8_t *ParametersTable);
1255HAL_StatusTypeDef HAL_DSI_EnterULPMData(DSI_HandleTypeDef *hdsi);
1256HAL_StatusTypeDef HAL_DSI_ExitULPMData(DSI_HandleTypeDef *hdsi);
1257HAL_StatusTypeDef HAL_DSI_EnterULPM(DSI_HandleTypeDef *hdsi);
1258HAL_StatusTypeDef HAL_DSI_ExitULPM(DSI_HandleTypeDef *hdsi);
1259
1260HAL_StatusTypeDef HAL_DSI_PatternGeneratorStart(DSI_HandleTypeDef *hdsi, uint32_t Mode, uint32_t Orientation);
1261HAL_StatusTypeDef HAL_DSI_PatternGeneratorStop(DSI_HandleTypeDef *hdsi);
1262
1263HAL_StatusTypeDef HAL_DSI_SetSlewRateAndDelayTuning(DSI_HandleTypeDef *hdsi, uint32_t CommDelay, uint32_t Lane,
1264 uint32_t Value);
1265HAL_StatusTypeDef HAL_DSI_SetLowPowerRXFilter(DSI_HandleTypeDef *hdsi, uint32_t Frequency);
1266HAL_StatusTypeDef HAL_DSI_SetSDD(DSI_HandleTypeDef *hdsi, FunctionalState State);
1267HAL_StatusTypeDef HAL_DSI_SetLanePinsConfiguration(DSI_HandleTypeDef *hdsi, uint32_t CustomLane, uint32_t Lane,
1268 FunctionalState State);
1269HAL_StatusTypeDef HAL_DSI_SetPHYTimings(DSI_HandleTypeDef *hdsi, uint32_t Timing, FunctionalState State,
1270 uint32_t Value);
1271HAL_StatusTypeDef HAL_DSI_ForceTXStopMode(DSI_HandleTypeDef *hdsi, uint32_t Lane, FunctionalState State);
1272HAL_StatusTypeDef HAL_DSI_ForceRXLowPower(DSI_HandleTypeDef *hdsi, FunctionalState State);
1273HAL_StatusTypeDef HAL_DSI_ForceDataLanesInRX(DSI_HandleTypeDef *hdsi, FunctionalState State);
1274HAL_StatusTypeDef HAL_DSI_SetPullDown(DSI_HandleTypeDef *hdsi, FunctionalState State);
1275HAL_StatusTypeDef HAL_DSI_SetContentionDetectionOff(DSI_HandleTypeDef *hdsi, FunctionalState State);
1276
1286uint32_t HAL_DSI_GetError(const DSI_HandleTypeDef *hdsi);
1287HAL_DSI_StateTypeDef HAL_DSI_GetState(const DSI_HandleTypeDef *hdsi);
1288
1297/* Private types -------------------------------------------------------------*/
1298/* Private defines -----------------------------------------------------------*/
1299/* Private variables ---------------------------------------------------------*/
1300/* Private constants ---------------------------------------------------------*/
1305#define DSI_MAX_RETURN_PKT_SIZE (0x00000037U)
1310/* Private macros ------------------------------------------------------------*/
1315#define IS_DSI_PLL_NDIV(NDIV) ((10U <= (NDIV)) && ((NDIV) <= 125U))
1316#define IS_DSI_PLL_IDF(IDF) (((IDF) == DSI_PLL_IN_DIV1) || \
1317 ((IDF) == DSI_PLL_IN_DIV2) || \
1318 ((IDF) == DSI_PLL_IN_DIV3) || \
1319 ((IDF) == DSI_PLL_IN_DIV4) || \
1320 ((IDF) == DSI_PLL_IN_DIV5) || \
1321 ((IDF) == DSI_PLL_IN_DIV6) || \
1322 ((IDF) == DSI_PLL_IN_DIV7))
1323#define IS_DSI_PLL_ODF(ODF) (((ODF) == DSI_PLL_OUT_DIV1) || \
1324 ((ODF) == DSI_PLL_OUT_DIV2) || \
1325 ((ODF) == DSI_PLL_OUT_DIV4) || \
1326 ((ODF) == DSI_PLL_OUT_DIV8))
1327#define IS_DSI_AUTO_CLKLANE_CONTROL(AutoClkLane) (((AutoClkLane) == DSI_AUTO_CLK_LANE_CTRL_DISABLE)\
1328 || ((AutoClkLane) == DSI_AUTO_CLK_LANE_CTRL_ENABLE))
1329#define IS_DSI_NUMBER_OF_LANES(NumberOfLanes) (((NumberOfLanes) == DSI_ONE_DATA_LANE)\
1330 || ((NumberOfLanes) == DSI_TWO_DATA_LANES))
1331#define IS_DSI_FLOW_CONTROL(FlowControl) (((FlowControl) | DSI_FLOW_CONTROL_ALL) == DSI_FLOW_CONTROL_ALL)
1332#define IS_DSI_COLOR_CODING(ColorCoding) ((ColorCoding) <= 5U)
1333#define IS_DSI_LOOSELY_PACKED(LooselyPacked) (((LooselyPacked) == DSI_LOOSELY_PACKED_ENABLE)\
1334 || ((LooselyPacked) == DSI_LOOSELY_PACKED_DISABLE))
1335#define IS_DSI_DE_POLARITY(DataEnable) (((DataEnable) == DSI_DATA_ENABLE_ACTIVE_HIGH)\
1336 || ((DataEnable) == DSI_DATA_ENABLE_ACTIVE_LOW))
1337#define IS_DSI_VSYNC_POLARITY(Vsync) (((Vsync) == DSI_VSYNC_ACTIVE_HIGH)\
1338 || ((Vsync) == DSI_VSYNC_ACTIVE_LOW))
1339#define IS_DSI_HSYNC_POLARITY(Hsync) (((Hsync) == DSI_HSYNC_ACTIVE_HIGH)\
1340 || ((Hsync) == DSI_HSYNC_ACTIVE_LOW))
1341#define IS_DSI_VIDEO_MODE_TYPE(VideoModeType) (((VideoModeType) == DSI_VID_MODE_NB_PULSES) || \
1342 ((VideoModeType) == DSI_VID_MODE_NB_EVENTS) || \
1343 ((VideoModeType) == DSI_VID_MODE_BURST))
1344#define IS_DSI_COLOR_MODE(ColorMode) (((ColorMode) == DSI_COLOR_MODE_FULL)\
1345 || ((ColorMode) == DSI_COLOR_MODE_EIGHT))
1346#define IS_DSI_SHUT_DOWN(ShutDown) (((ShutDown) == DSI_DISPLAY_ON) || ((ShutDown) == DSI_DISPLAY_OFF))
1347#define IS_DSI_LP_COMMAND(LPCommand) (((LPCommand) == DSI_LP_COMMAND_DISABLE)\
1348 || ((LPCommand) == DSI_LP_COMMAND_ENABLE))
1349#define IS_DSI_LP_HFP(LPHFP) (((LPHFP) == DSI_LP_HFP_DISABLE) || ((LPHFP) == DSI_LP_HFP_ENABLE))
1350#define IS_DSI_LP_HBP(LPHBP) (((LPHBP) == DSI_LP_HBP_DISABLE) || ((LPHBP) == DSI_LP_HBP_ENABLE))
1351#define IS_DSI_LP_VACTIVE(LPVActive) (((LPVActive) == DSI_LP_VACT_DISABLE)\
1352 || ((LPVActive) == DSI_LP_VACT_ENABLE))
1353#define IS_DSI_LP_VFP(LPVFP) (((LPVFP) == DSI_LP_VFP_DISABLE) || ((LPVFP) == DSI_LP_VFP_ENABLE))
1354#define IS_DSI_LP_VBP(LPVBP) (((LPVBP) == DSI_LP_VBP_DISABLE) || ((LPVBP) == DSI_LP_VBP_ENABLE))
1355#define IS_DSI_LP_VSYNC(LPVSYNC) (((LPVSYNC) == DSI_LP_VSYNC_DISABLE)\
1356 || ((LPVSYNC) == DSI_LP_VSYNC_ENABLE))
1357#define IS_DSI_FBTAA(FrameBTAAcknowledge) (((FrameBTAAcknowledge) == DSI_FBTAA_DISABLE)\
1358 || ((FrameBTAAcknowledge) == DSI_FBTAA_ENABLE))
1359#define IS_DSI_TE_SOURCE(TESource) (((TESource) == DSI_TE_DSILINK) || ((TESource) == DSI_TE_EXTERNAL))
1360#define IS_DSI_TE_POLARITY(TEPolarity) (((TEPolarity) == DSI_TE_RISING_EDGE)\
1361 || ((TEPolarity) == DSI_TE_FALLING_EDGE))
1362#define IS_DSI_AUTOMATIC_REFRESH(AutomaticRefresh) (((AutomaticRefresh) == DSI_AR_DISABLE)\
1363 || ((AutomaticRefresh) == DSI_AR_ENABLE))
1364#define IS_DSI_VS_POLARITY(VSPolarity) (((VSPolarity) == DSI_VSYNC_FALLING)\
1365 || ((VSPolarity) == DSI_VSYNC_RISING))
1366#define IS_DSI_TE_ACK_REQUEST(TEAcknowledgeRequest) (((TEAcknowledgeRequest) == DSI_TE_ACKNOWLEDGE_DISABLE)\
1367 || ((TEAcknowledgeRequest) == DSI_TE_ACKNOWLEDGE_ENABLE))
1368#define IS_DSI_ACK_REQUEST(AcknowledgeRequest) (((AcknowledgeRequest) == DSI_ACKNOWLEDGE_DISABLE)\
1369 || ((AcknowledgeRequest) == DSI_ACKNOWLEDGE_ENABLE))
1370#define IS_DSI_LP_GSW0P(LP_GSW0P) (((LP_GSW0P) == DSI_LP_GSW0P_DISABLE)\
1371 || ((LP_GSW0P) == DSI_LP_GSW0P_ENABLE))
1372#define IS_DSI_LP_GSW1P(LP_GSW1P) (((LP_GSW1P) == DSI_LP_GSW1P_DISABLE)\
1373 || ((LP_GSW1P) == DSI_LP_GSW1P_ENABLE))
1374#define IS_DSI_LP_GSW2P(LP_GSW2P) (((LP_GSW2P) == DSI_LP_GSW2P_DISABLE)\
1375 || ((LP_GSW2P) == DSI_LP_GSW2P_ENABLE))
1376#define IS_DSI_LP_GSR0P(LP_GSR0P) (((LP_GSR0P) == DSI_LP_GSR0P_DISABLE)\
1377 || ((LP_GSR0P) == DSI_LP_GSR0P_ENABLE))
1378#define IS_DSI_LP_GSR1P(LP_GSR1P) (((LP_GSR1P) == DSI_LP_GSR1P_DISABLE)\
1379 || ((LP_GSR1P) == DSI_LP_GSR1P_ENABLE))
1380#define IS_DSI_LP_GSR2P(LP_GSR2P) (((LP_GSR2P) == DSI_LP_GSR2P_DISABLE)\
1381 || ((LP_GSR2P) == DSI_LP_GSR2P_ENABLE))
1382#define IS_DSI_LP_GLW(LP_GLW) (((LP_GLW) == DSI_LP_GLW_DISABLE)\
1383 || ((LP_GLW) == DSI_LP_GLW_ENABLE))
1384#define IS_DSI_LP_DSW0P(LP_DSW0P) (((LP_DSW0P) == DSI_LP_DSW0P_DISABLE)\
1385 || ((LP_DSW0P) == DSI_LP_DSW0P_ENABLE))
1386#define IS_DSI_LP_DSW1P(LP_DSW1P) (((LP_DSW1P) == DSI_LP_DSW1P_DISABLE)\
1387 || ((LP_DSW1P) == DSI_LP_DSW1P_ENABLE))
1388#define IS_DSI_LP_DSR0P(LP_DSR0P) (((LP_DSR0P) == DSI_LP_DSR0P_DISABLE)\
1389 || ((LP_DSR0P) == DSI_LP_DSR0P_ENABLE))
1390#define IS_DSI_LP_DLW(LP_DLW) (((LP_DLW) == DSI_LP_DLW_DISABLE)\
1391 || ((LP_DLW) == DSI_LP_DLW_ENABLE))
1392#define IS_DSI_LP_MRDP(LP_MRDP) (((LP_MRDP) == DSI_LP_MRDP_DISABLE)\
1393 || ((LP_MRDP) == DSI_LP_MRDP_ENABLE))
1394#define IS_DSI_SHORT_WRITE_PACKET_TYPE(MODE) (((MODE) == DSI_DCS_SHORT_PKT_WRITE_P0) || \
1395 ((MODE) == DSI_DCS_SHORT_PKT_WRITE_P1) || \
1396 ((MODE) == DSI_GEN_SHORT_PKT_WRITE_P0) || \
1397 ((MODE) == DSI_GEN_SHORT_PKT_WRITE_P1) || \
1398 ((MODE) == DSI_GEN_SHORT_PKT_WRITE_P2))
1399#define IS_DSI_LONG_WRITE_PACKET_TYPE(MODE) (((MODE) == DSI_DCS_LONG_PKT_WRITE) || \
1400 ((MODE) == DSI_GEN_LONG_PKT_WRITE))
1401#define IS_DSI_READ_PACKET_TYPE(MODE) (((MODE) == DSI_DCS_SHORT_PKT_READ) || \
1402 ((MODE) == DSI_GEN_SHORT_PKT_READ_P0) || \
1403 ((MODE) == DSI_GEN_SHORT_PKT_READ_P1) || \
1404 ((MODE) == DSI_GEN_SHORT_PKT_READ_P2))
1405#define IS_DSI_COMMUNICATION_DELAY(CommDelay) (((CommDelay) == DSI_SLEW_RATE_HSTX) || \
1406 ((CommDelay) == DSI_SLEW_RATE_LPTX) || \
1407 ((CommDelay) == DSI_HS_DELAY))
1408#define IS_DSI_LANE_GROUP(Lane) (((Lane) == DSI_CLOCK_LANE) || ((Lane) == DSI_DATA_LANES))
1409#define IS_DSI_CUSTOM_LANE(CustomLane) (((CustomLane) == DSI_SWAP_LANE_PINS)\
1410 || ((CustomLane) == DSI_INVERT_HS_SIGNAL))
1411#define IS_DSI_LANE(Lane) (((Lane) == DSI_CLOCK_LANE) || \
1412 ((Lane) == DSI_DATA_LANE0) || ((Lane) == DSI_DATA_LANE1))
1413#define IS_DSI_PHY_TIMING(Timing) (((Timing) == DSI_TCLK_POST ) || \
1414 ((Timing) == DSI_TLPX_CLK ) || \
1415 ((Timing) == DSI_THS_EXIT ) || \
1416 ((Timing) == DSI_TLPX_DATA ) || \
1417 ((Timing) == DSI_THS_ZERO ) || \
1418 ((Timing) == DSI_THS_TRAIL ) || \
1419 ((Timing) == DSI_THS_PREPARE ) || \
1420 ((Timing) == DSI_TCLK_ZERO ) || \
1421 ((Timing) == DSI_TCLK_PREPARE))
1422
1434#endif /* DSI */
1435
1436#ifdef __cplusplus
1437}
1438#endif
1439
1440#endif /* STM32H7xx_HAL_DSI_H */
__IO
#define __IO
Definition: core_cm4.h:239
stm32h7xx_hal_def.h
This file contains HAL common defines, enumeration, macros and structures definitions.
HAL_StatusTypeDef
HAL_StatusTypeDef
HAL Status structures definition.
Definition: stm32h7xx_hal_def.h:47
HAL_LockTypeDef
HAL_LockTypeDef
HAL Lock structures definition.
Definition: stm32h7xx_hal_def.h:58
DSI_TypeDef
DSI Controller.
Definition: stm32h747xg.h:709
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