RTEMS 6.1-rc5
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stm32h7xx_hal_dma2d.h
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1
19/* Define to prevent recursive inclusion -------------------------------------*/
20#ifndef STM32H7xx_HAL_DMA2D_H
21#define STM32H7xx_HAL_DMA2D_H
22
23#ifdef __cplusplus
24extern "C" {
25#endif
26
27/* Includes ------------------------------------------------------------------*/
28#include "stm32h7xx_hal_def.h"
29
34#if defined (DMA2D)
35
41/* Exported types ------------------------------------------------------------*/
46#define MAX_DMA2D_LAYER 2U
51typedef struct
52{
53 uint32_t *pCLUT;
55 uint32_t CLUTColorMode;
58 uint32_t Size;
60} DMA2D_CLUTCfgTypeDef;
61
65typedef struct
66{
67 uint32_t Mode;
70 uint32_t ColorMode;
73 uint32_t OutputOffset;
76 uint32_t AlphaInverted;
79 uint32_t RedBlueSwap;
84 uint32_t BytesSwap;
87 uint32_t LineOffsetMode;
90} DMA2D_InitTypeDef;
91
92
96typedef struct
97{
98 uint32_t InputOffset;
102 uint32_t InputColorMode;
105 uint32_t AlphaMode;
108 uint32_t InputAlpha;
119 uint32_t AlphaInverted;
122 uint32_t RedBlueSwap;
125 uint32_t ChromaSubSampling;
128} DMA2D_LayerCfgTypeDef;
129
133typedef enum
134{
135 HAL_DMA2D_STATE_RESET = 0x00U,
136 HAL_DMA2D_STATE_READY = 0x01U,
137 HAL_DMA2D_STATE_BUSY = 0x02U,
138 HAL_DMA2D_STATE_TIMEOUT = 0x03U,
139 HAL_DMA2D_STATE_ERROR = 0x04U,
140 HAL_DMA2D_STATE_SUSPEND = 0x05U
141} HAL_DMA2D_StateTypeDef;
142
146typedef struct __DMA2D_HandleTypeDef
147{
148 DMA2D_TypeDef *Instance;
150 DMA2D_InitTypeDef Init;
152 void (* XferCpltCallback)(struct __DMA2D_HandleTypeDef *hdma2d);
154 void (* XferErrorCallback)(struct __DMA2D_HandleTypeDef *hdma2d);
156#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
157 void (* LineEventCallback)(struct __DMA2D_HandleTypeDef *hdma2d);
159 void (* CLUTLoadingCpltCallback)(struct __DMA2D_HandleTypeDef *hdma2d);
161 void (* MspInitCallback)(struct __DMA2D_HandleTypeDef *hdma2d);
163 void (* MspDeInitCallback)(struct __DMA2D_HandleTypeDef *hdma2d);
165#endif /* (USE_HAL_DMA2D_REGISTER_CALLBACKS) */
166
167 DMA2D_LayerCfgTypeDef LayerCfg[MAX_DMA2D_LAYER];
169 HAL_LockTypeDef Lock;
171 __IO HAL_DMA2D_StateTypeDef State;
173 __IO uint32_t ErrorCode;
174} DMA2D_HandleTypeDef;
175
176#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
180typedef void (*pDMA2D_CallbackTypeDef)(DMA2D_HandleTypeDef *hdma2d);
181#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
186/* Exported constants --------------------------------------------------------*/
196#define HAL_DMA2D_ERROR_NONE 0x00000000U
197#define HAL_DMA2D_ERROR_TE 0x00000001U
198#define HAL_DMA2D_ERROR_CE 0x00000002U
199#define HAL_DMA2D_ERROR_CAE 0x00000004U
200#define HAL_DMA2D_ERROR_TIMEOUT 0x00000020U
201#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
202#define HAL_DMA2D_ERROR_INVALID_CALLBACK 0x00000040U
203#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
204
213#define DMA2D_M2M 0x00000000U
214#define DMA2D_M2M_PFC DMA2D_CR_MODE_0
215#define DMA2D_M2M_BLEND DMA2D_CR_MODE_1
216#define DMA2D_R2M (DMA2D_CR_MODE_1 | DMA2D_CR_MODE_0)
217#define DMA2D_M2M_BLEND_FG DMA2D_CR_MODE_2
218#define DMA2D_M2M_BLEND_BG (DMA2D_CR_MODE_2 | DMA2D_CR_MODE_0)
227#define DMA2D_OUTPUT_ARGB8888 0x00000000U
228#define DMA2D_OUTPUT_RGB888 DMA2D_OPFCCR_CM_0
229#define DMA2D_OUTPUT_RGB565 DMA2D_OPFCCR_CM_1
230#define DMA2D_OUTPUT_ARGB1555 (DMA2D_OPFCCR_CM_0|DMA2D_OPFCCR_CM_1)
231#define DMA2D_OUTPUT_ARGB4444 DMA2D_OPFCCR_CM_2
240#define DMA2D_INPUT_ARGB8888 0x00000000U
241#define DMA2D_INPUT_RGB888 0x00000001U
242#define DMA2D_INPUT_RGB565 0x00000002U
243#define DMA2D_INPUT_ARGB1555 0x00000003U
244#define DMA2D_INPUT_ARGB4444 0x00000004U
245#define DMA2D_INPUT_L8 0x00000005U
246#define DMA2D_INPUT_AL44 0x00000006U
247#define DMA2D_INPUT_AL88 0x00000007U
248#define DMA2D_INPUT_L4 0x00000008U
249#define DMA2D_INPUT_A8 0x00000009U
250#define DMA2D_INPUT_A4 0x0000000AU
251#define DMA2D_INPUT_YCBCR 0x0000000BU
260#define DMA2D_NO_MODIF_ALPHA 0x00000000U
261#define DMA2D_REPLACE_ALPHA 0x00000001U
262#define DMA2D_COMBINE_ALPHA 0x00000002U
272#define DMA2D_REGULAR_ALPHA 0x00000000U
273#define DMA2D_INVERTED_ALPHA 0x00000001U
282#define DMA2D_RB_REGULAR 0x00000000U
283#define DMA2D_RB_SWAP 0x00000001U
294#define DMA2D_LOM_PIXELS 0x00000000U
295#define DMA2D_LOM_BYTES DMA2D_CR_LOM
304#define DMA2D_BYTES_REGULAR 0x00000000U
305#define DMA2D_BYTES_SWAP DMA2D_OPFCCR_SB
314#define DMA2D_NO_CSS 0x00000000U
315#define DMA2D_CSS_422 0x00000001U
316#define DMA2D_CSS_420 0x00000002U
325#define DMA2D_CCM_ARGB8888 0x00000000U
326#define DMA2D_CCM_RGB888 0x00000001U
335#define DMA2D_IT_CE DMA2D_CR_CEIE
336#define DMA2D_IT_CTC DMA2D_CR_CTCIE
337#define DMA2D_IT_CAE DMA2D_CR_CAEIE
338#define DMA2D_IT_TW DMA2D_CR_TWIE
339#define DMA2D_IT_TC DMA2D_CR_TCIE
340#define DMA2D_IT_TE DMA2D_CR_TEIE
349#define DMA2D_FLAG_CE DMA2D_ISR_CEIF
350#define DMA2D_FLAG_CTC DMA2D_ISR_CTCIF
351#define DMA2D_FLAG_CAE DMA2D_ISR_CAEIF
352#define DMA2D_FLAG_TW DMA2D_ISR_TWIF
353#define DMA2D_FLAG_TC DMA2D_ISR_TCIF
354#define DMA2D_FLAG_TE DMA2D_ISR_TEIF
359#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
363typedef enum
364{
365 HAL_DMA2D_MSPINIT_CB_ID = 0x00U,
366 HAL_DMA2D_MSPDEINIT_CB_ID = 0x01U,
367 HAL_DMA2D_TRANSFERCOMPLETE_CB_ID = 0x02U,
368 HAL_DMA2D_TRANSFERERROR_CB_ID = 0x03U,
369 HAL_DMA2D_LINEEVENT_CB_ID = 0x04U,
370 HAL_DMA2D_CLUTLOADINGCPLT_CB_ID = 0x05U,
371} HAL_DMA2D_CallbackIDTypeDef;
372#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
373
374
378/* Exported macros ------------------------------------------------------------*/
388#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
389#define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) do{ \
390 (__HANDLE__)->State = HAL_DMA2D_STATE_RESET;\
391 (__HANDLE__)->MspInitCallback = NULL; \
392 (__HANDLE__)->MspDeInitCallback = NULL; \
393 }while(0)
394#else
395#define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA2D_STATE_RESET)
396#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
397
398
404#define __HAL_DMA2D_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA2D_CR_START)
405
406
407/* Interrupt & Flag management */
421#define __HAL_DMA2D_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__))
422
436#define __HAL_DMA2D_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->IFCR = (__FLAG__))
437
451#define __HAL_DMA2D_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
452
466#define __HAL_DMA2D_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
467
481#define __HAL_DMA2D_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR & (__INTERRUPT__))
482
487/* Exported functions --------------------------------------------------------*/
496/* Initialization and de-initialization functions *******************************/
497HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d);
498HAL_StatusTypeDef HAL_DMA2D_DeInit(DMA2D_HandleTypeDef *hdma2d);
499void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef *hdma2d);
500void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef *hdma2d);
501/* Callbacks Register/UnRegister functions ***********************************/
502#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
503HAL_StatusTypeDef HAL_DMA2D_RegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID,
504 pDMA2D_CallbackTypeDef pCallback);
505HAL_StatusTypeDef HAL_DMA2D_UnRegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID);
506#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
507
517/* IO operation functions *******************************************************/
518HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width,
519 uint32_t Height);
520HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2,
521 uint32_t DstAddress, uint32_t Width, uint32_t Height);
522HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width,
523 uint32_t Height);
524HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2,
525 uint32_t DstAddress, uint32_t Width, uint32_t Height);
526HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d);
527HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d);
528HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d);
529HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
530HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg,
531 uint32_t LayerIdx);
532HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg,
533 uint32_t LayerIdx);
534HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
535HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
536HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
537HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
538HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Resume(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
539HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout);
540void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d);
541void HAL_DMA2D_LineEventCallback(DMA2D_HandleTypeDef *hdma2d);
542void HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d);
543
552/* Peripheral Control functions *************************************************/
553HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
554HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
555HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line);
556HAL_StatusTypeDef HAL_DMA2D_EnableDeadTime(DMA2D_HandleTypeDef *hdma2d);
557HAL_StatusTypeDef HAL_DMA2D_DisableDeadTime(DMA2D_HandleTypeDef *hdma2d);
558HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t DeadTime);
559
568/* Peripheral State functions ***************************************************/
569HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d);
570uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d);
571
580/* Private constants ---------------------------------------------------------*/
581
590#define DMA2D_LINE_WATERMARK_MAX DMA2D_LWR_LW
599#define DMA2D_COLOR_VALUE 0x000000FFU
608#define DMA2D_MAX_LAYER 2U
617#define DMA2D_BACKGROUND_LAYER 0x00000000U
618#define DMA2D_FOREGROUND_LAYER 0x00000001U
627#define DMA2D_OFFSET DMA2D_FGOR_LO
636#define DMA2D_PIXEL (DMA2D_NLR_PL >> 16U)
637#define DMA2D_LINE DMA2D_NLR_NL
646#define DMA2D_CLUT_SIZE (DMA2D_FGPFCCR_CS >> 8U)
656/* Private macros ------------------------------------------------------------*/
661#define IS_DMA2D_LAYER(LAYER) (((LAYER) == DMA2D_BACKGROUND_LAYER)\
662 || ((LAYER) == DMA2D_FOREGROUND_LAYER))
663
664#define IS_DMA2D_MODE(MODE) (((MODE) == DMA2D_M2M) || ((MODE) == DMA2D_M2M_PFC) || \
665 ((MODE) == DMA2D_M2M_BLEND) || ((MODE) == DMA2D_R2M) || \
666 ((MODE) == DMA2D_M2M_BLEND_FG) || ((MODE) == DMA2D_M2M_BLEND_BG))
667
668#define IS_DMA2D_CMODE(MODE_ARGB) (((MODE_ARGB) == DMA2D_OUTPUT_ARGB8888) || \
669 ((MODE_ARGB) == DMA2D_OUTPUT_RGB888) || \
670 ((MODE_ARGB) == DMA2D_OUTPUT_RGB565) || \
671 ((MODE_ARGB) == DMA2D_OUTPUT_ARGB1555) || \
672 ((MODE_ARGB) == DMA2D_OUTPUT_ARGB4444))
673
674#define IS_DMA2D_COLOR(COLOR) ((COLOR) <= DMA2D_COLOR_VALUE)
675#define IS_DMA2D_LINE(LINE) ((LINE) <= DMA2D_LINE)
676#define IS_DMA2D_PIXEL(PIXEL) ((PIXEL) <= DMA2D_PIXEL)
677#define IS_DMA2D_OFFSET(OOFFSET) ((OOFFSET) <= DMA2D_OFFSET)
678
679#define IS_DMA2D_INPUT_COLOR_MODE(INPUT_CM) (((INPUT_CM) == DMA2D_INPUT_ARGB8888) || \
680 ((INPUT_CM) == DMA2D_INPUT_RGB888) || \
681 ((INPUT_CM) == DMA2D_INPUT_RGB565) || \
682 ((INPUT_CM) == DMA2D_INPUT_ARGB1555) || \
683 ((INPUT_CM) == DMA2D_INPUT_ARGB4444) || \
684 ((INPUT_CM) == DMA2D_INPUT_L8) || \
685 ((INPUT_CM) == DMA2D_INPUT_AL44) || \
686 ((INPUT_CM) == DMA2D_INPUT_AL88) || \
687 ((INPUT_CM) == DMA2D_INPUT_L4) || \
688 ((INPUT_CM) == DMA2D_INPUT_A8) || \
689 ((INPUT_CM) == DMA2D_INPUT_A4) || \
690 ((INPUT_CM) == DMA2D_INPUT_YCBCR))
691
692#define IS_DMA2D_ALPHA_MODE(AlphaMode) (((AlphaMode) == DMA2D_NO_MODIF_ALPHA) || \
693 ((AlphaMode) == DMA2D_REPLACE_ALPHA) || \
694 ((AlphaMode) == DMA2D_COMBINE_ALPHA))
695
696#define IS_DMA2D_ALPHA_INVERTED(Alpha_Inverted) (((Alpha_Inverted) == DMA2D_REGULAR_ALPHA) || \
697 ((Alpha_Inverted) == DMA2D_INVERTED_ALPHA))
698
699#define IS_DMA2D_RB_SWAP(RB_Swap) (((RB_Swap) == DMA2D_RB_REGULAR) || \
700 ((RB_Swap) == DMA2D_RB_SWAP))
701
702#define IS_DMA2D_LOM_MODE(LOM) (((LOM) == DMA2D_LOM_PIXELS) || \
703 ((LOM) == DMA2D_LOM_BYTES))
704
705#define IS_DMA2D_BYTES_SWAP(BYTES_SWAP) (((BYTES_SWAP) == DMA2D_BYTES_REGULAR) || \
706 ((BYTES_SWAP) == DMA2D_BYTES_SWAP))
707
708#define IS_DMA2D_CHROMA_SUB_SAMPLING(CSS) (((CSS) == DMA2D_NO_CSS) || \
709 ((CSS) == DMA2D_CSS_422) || \
710 ((CSS) == DMA2D_CSS_420))
711
712#define IS_DMA2D_CLUT_CM(CLUT_CM) (((CLUT_CM) == DMA2D_CCM_ARGB8888) || ((CLUT_CM) == DMA2D_CCM_RGB888))
713#define IS_DMA2D_CLUT_SIZE(CLUT_SIZE) ((CLUT_SIZE) <= DMA2D_CLUT_SIZE)
714#define IS_DMA2D_LINEWATERMARK(LineWatermark) ((LineWatermark) <= DMA2D_LINE_WATERMARK_MAX)
715#define IS_DMA2D_IT(IT) (((IT) == DMA2D_IT_CTC) || ((IT) == DMA2D_IT_CAE) || \
716 ((IT) == DMA2D_IT_TW) || ((IT) == DMA2D_IT_TC) || \
717 ((IT) == DMA2D_IT_TE) || ((IT) == DMA2D_IT_CE))
718#define IS_DMA2D_GET_FLAG(FLAG) (((FLAG) == DMA2D_FLAG_CTC) || ((FLAG) == DMA2D_FLAG_CAE) || \
719 ((FLAG) == DMA2D_FLAG_TW) || ((FLAG) == DMA2D_FLAG_TC) || \
720 ((FLAG) == DMA2D_FLAG_TE) || ((FLAG) == DMA2D_FLAG_CE))
729#endif /* defined (DMA2D) */
730
735#ifdef __cplusplus
736}
737#endif
738
739#endif /* STM32H7xx_HAL_DMA2D_H */
__IO
#define __IO
Definition: core_cm4.h:239
stm32h7xx_hal_def.h
This file contains HAL common defines, enumeration, macros and structures definitions.
HAL_StatusTypeDef
HAL_StatusTypeDef
HAL Status structures definition.
Definition: stm32h7xx_hal_def.h:47
HAL_LockTypeDef
HAL_LockTypeDef
HAL Lock structures definition.
Definition: stm32h7xx_hal_def.h:58
DMA2D_TypeDef
DMA2D Controller.
Definition: stm32h723xx.h:686
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