RTEMS 6.1-rc5
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spwtdp.h
1/* SPDX-License-Identifier: BSD-2-Clause */
2
3/* SPWTDP - SpaceWire Time Distribution Protocol. The driver provides
4 * device discovery and interrupt management.
5 *
6 * COPYRIGHT (c) 2017.
7 * Cobham Gaisler AB
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 *
30 */
31
32#ifndef __SPWTDP_H__
33#define __SPWTDP_H__
34
35#ifdef __cplusplus
36extern "C" {
37#endif
38
39#define SPWTDP_ERR_OK 0
40#define SPWTDP_ERR_EINVAL -1
41#define SPWTDP_ERR_ERROR -2
42#define SPWTDP_ERR_NOINIT -3
43
44/* Maximum number of SPWTDP devices supported by driver */
45#define SPWTDP_MAX 2
46
47/* SPWTDP Register layout */
48struct spwtdp_regs {
49 volatile unsigned int conf[4]; /* 0x000-0x00C */
50 volatile unsigned int stat[4]; /* 0x010-0x01C */
51 volatile unsigned int cmd_ctrl; /* 0x020 */
52 volatile unsigned int cmd_et[5]; /* 0x024-0x034 */
53 volatile unsigned int resv1[2]; /* 0x038-0x03C */
54 volatile unsigned int dat_ctrl; /* 0x040 */
55 volatile unsigned int dat_et[5]; /* 0x044-0x054 */
56 volatile unsigned int resv2[2]; /* 0x058-0x05C */
57 volatile unsigned int ts_rx_ctrl; /* 0x060 */
58 volatile unsigned int ts_rx_et[5]; /* 0x064-0x074 */
59 volatile unsigned int resv3[2]; /* 0x078-0x07C */
60 volatile unsigned int ts_tx_ctrl; /* 0x080 */
61 volatile unsigned int ts_tx_et[5]; /* 0x084-0x094 */
62 volatile unsigned int resv4[2]; /* 0x098 */
63 volatile unsigned int lat_ctrl; /* 0x0A0 */
64 volatile unsigned int lat_et[5]; /* 0x0A4-0x0B4 */
65 volatile unsigned int resv5[2]; /* 0x0B8-0x0BC */
66 volatile unsigned int ien; /* 0x0C0 */
67 volatile unsigned int ists; /* 0x0C4 */
68 volatile unsigned int dlycnt; /* 0x0C8 */
69 volatile unsigned int dissync; /* 0x0CC */
70 volatile unsigned int resv6[12]; /* 0x0D0-0x0FC */
71 volatile unsigned int edmask[4]; /* 0x100-0x10C */
72 struct {
73 volatile unsigned int ctrl; /* 0x110, 0x130, 0x150, 0x170 */
74 volatile unsigned int et[5]; /* 0x114-0x124, 0x134-0x144, 0x154-0x164, 0x174-0x184, */
75 volatile unsigned int resv0[2]; /* 0x128-0x12C, 0x148-0x14C, 0x168-0x16C, 0x188-0x18C, */
76 } edat[4]; /* 0x110-0x18C */
77 volatile unsigned int resv7[4]; /* 0x190-0x19C */
78 volatile unsigned int pulse[8]; /* 0x1A0-0x1BC */
79 volatile unsigned int resv8[16]; /* 0x1C0-0x1FC */
80};
81
82/*
83 * Configuration register definitions
84 */
85#define CONF0_JE (0x1 << CONF0_JE_BIT)
86#define CONF0_ST (0x1 << CONF0_ST_BIT)
87#define CONF0_EP (0x1 << CONF0_EP_BIT)
88#define CONF0_ET (0x1 << CONF0_ET_BIT)
89#define CONF0_SP (0x1 << CONF0_SP_BIT)
90#define CONF0_SE (0x1 << CONF0_SE_BIT)
91#define CONF0_LE (0x1 << CONF0_LE_BIT)
92#define CONF0_AE (0x1 << CONF0_AE_BIT)
93#define CONF0_MAP (0x1f << CONF0_MAP_BIT)
94#define CONF0_TD (0x1 << CONF0_TD_BIT)
95#define CONF0_MU (0x1 << CONF0_MU_BIT)
96#define CONF0_SEL (0x3 << CONF0_SEL_BIT)
97#define CONF0_ME (0x1 << CONF0_ME_BIT)
98#define CONF0_RE (0x1 << CONF0_RE_BIT)
99#define CONF0_TE (0x1 << CONF0_TE_BIT)
100#define CONF0_RS (0x1 << CONF0_RS_BIT)
101
102#define CONF0_JE_BIT 24
103#define CONF0_ST_BIT 21
104#define CONF0_EP_BIT 20
105#define CONF0_ET_BIT 19
106#define CONF0_SP_BIT 18
107#define CONF0_SE_BIT 17
108#define CONF0_LE_BIT 16
109#define CONF0_AE_BIT 15
110#define CONF0_MAP_BIT 8
111#define CONF0_TD_BIT 7
112#define CONF0_MU_BIT 6
113#define CONF0_SEL_BIT 4
114#define CONF0_ME_BIT 3
115#define CONF0_RE_BIT 2
116#define CONF0_TE_BIT 1
117#define CONF0_RS_BIT 0
118
119#define CONF1_FSINC (0x3fffffff << CONF1_FSINC_BIT)
120
121#define CONF1_FSINC_BIT 0
122
123#define CONF2_CV (0xffffff << CONF2_CV_BIT)
124#define CONF2_ETINC (0xff << CONF2_ETINC_BIT)
125
126#define CONF2_CV_BIT 8
127#define CONF2_ETINC_BIT 0
128
129#define CONF3_OUTPORT (0xf << CONF3_OUTPORT_BIT)
130#define CONF3_INPORT (0xf << CONF3_INPORT_BIT)
131#define CONF3_STM (0x3f << CONF3_STM_BIT)
132#define CONF3_DI64R (0x1 << CONF3_DI64R_BIT)
133#define CONF3_DI64T (0x1 << CONF3_DI64T_BIT)
134#define CONF3_DI64 (0x1 << CONF3_DI64_BIT)
135#define CONF3_DI (0x1 << CONF3_DI_BIT)
136#define CONF3_INRX (0x1f << CONF3_INRX_BIT)
137#define CONF3_INTX (0x1f << CONF3_INTX_BIT)
138
139#define CONF3_OUTPORT_BIT 28
140#define CONF3_INPORT_BIT 24
141#define CONF3_STM_BIT 16
142#define CONF3_DI64R_BIT 13
143#define CONF3_DI64T_BIT 12
144#define CONF3_DI64_BIT 11
145#define CONF3_DI_BIT 10
146#define CONF3_INRX_BIT 5
147#define CONF3_INTX_BIT 0
148
149/*
150 * Control register definitions
151 */
152#define CTRL_NC (0x1 << CTRL_NC_BIT)
153#define CTRL_IS (0x1 << CTRL_IS_BIT)
154#define CTRL_SPWTC (0xff << CTRL_SPWTC_BIT)
155#define CTRL_CPF (0xffff << CTRL_CPF_BIT)
156
157#define CTRL_NC_BIT 31
158#define CTRL_IS_BIT 30
159#define CTRL_SPWTC_BIT 16
160#define CTRL_CPF_BIT 0
161
162/*
163 * Interrupt register definition
164 */
165#define SPWTDP_IRQ_S (0x1 << SPWTDP_IRQ_S_BIT)
166#define SPWTDP_IRQ_TR (0x1 << SPWTDP_IRQ_TR_BIT)
167#define SPWTDP_IRQ_TM (0x1 << SPWTDP_IRQ_TM_BIT)
168#define SPWTDP_IRQ_TT (0x1 << SPWTDP_IRQ_TT_BIT)
169#define SPWTDP_IRQ_DIR (0x1 << SPWTDP_IRQ_DIR_BIT)
170#define SPWTDP_IRQ_DIT (0x1 << SPWTDP_IRQ_DIT_BIT)
171#define SPWTDP_IRQ_EDI0 (0x1 << SPWTDP_IRQ_EDI0_BIT)
172#define SPWTDP_IRQ_EDI1 (0x1 << SPWTDP_IRQ_EDI1_BIT)
173#define SPWTDP_IRQ_EDI2 (0x1 << SPWTDP_IRQ_EDI2_BIT)
174#define SPWTDP_IRQ_EDI3 (0x1 << SPWTDP_IRQ_EDI3_BIT)
175#define SPWTDP_IRQ_SET (0x1 << SPWTDP_IRQ_SET_BIT)
176#define SPWTDP_IRQ_P0 (0x1 << SPWTDP_IRQ_P0_BIT)
177#define SPWTDP_IRQ_P1 (0x1 << SPWTDP_IRQ_P1_BIT)
178#define SPWTDP_IRQ_P2 (0x1 << SPWTDP_IRQ_P2_BIT)
179#define SPWTDP_IRQ_P3 (0x1 << SPWTDP_IRQ_P3_BIT)
180#define SPWTDP_IRQ_P4 (0x1 << SPWTDP_IRQ_P4_BIT)
181#define SPWTDP_IRQ_P5 (0x1 << SPWTDP_IRQ_P5_BIT)
182#define SPWTDP_IRQ_P6 (0x1 << SPWTDP_IRQ_P6_BIT)
183#define SPWTDP_IRQ_P7 (0x1 << SPWTDP_IRQ_P7_BIT)
184#define SPWTDP_IRQ_NCTC (0x1 << SPWTDP_IRQ_NCTC_BIT)
185#define SPWTDP_IRQ_WCLEAR \
186 (SPWTDP_IRQ_S | SPWTDP_IRQ_TR | SPWTDP_IRQ_TM | \
187 SPWTDP_IRQ_TT | SPWTDP_IRQ_DIR | SPWTDP_IRQ_DIT | SPWTDP_IRQ_EDI0 | \
188 SPWTDP_IRQ_EDI1 | SPWTDP_IRQ_EDI2 | SPWTDP_IRQ_EDI3 | SPWTDP_IRQ_SET |\
189 SPWTDP_IRQ_P0 | SPWTDP_IRQ_P1 | SPWTDP_IRQ_P2 | SPWTDP_IRQ_P3 | \
190 SPWTDP_IRQ_P4 | SPWTDP_IRQ_P5 | SPWTDP_IRQ_P6 | SPWTDP_IRQ_P7 | \
191 SPWTDP_IRQ_NCTC)
192#define SPWTDP_IRQ_ALL (SPWTDP_IRQ_WCLEAR)
193
194#define SPWTDP_IRQ_S_BIT 0
195#define SPWTDP_IRQ_TR_BIT 1
196#define SPWTDP_IRQ_TM_BIT 2
197#define SPWTDP_IRQ_TT_BIT 3
198#define SPWTDP_IRQ_DIR_BIT 4
199#define SPWTDP_IRQ_DIT_BIT 5
200#define SPWTDP_IRQ_EDI0_BIT 6
201#define SPWTDP_IRQ_EDI1_BIT 7
202#define SPWTDP_IRQ_EDI2_BIT 8
203#define SPWTDP_IRQ_EDI3_BIT 9
204#define SPWTDP_IRQ_SET_BIT 10
205#define SPWTDP_IRQ_P0_BIT 11
206#define SPWTDP_IRQ_P1_BIT 12
207#define SPWTDP_IRQ_P2_BIT 13
208#define SPWTDP_IRQ_P3_BIT 14
209#define SPWTDP_IRQ_P4_BIT 15
210#define SPWTDP_IRQ_P5_BIT 16
211#define SPWTDP_IRQ_P6_BIT 17
212#define SPWTDP_IRQ_P7_BIT 18
213#define SPWTDP_IRQ_NCTC_BIT 19
214
215/* Register the SPWTDP Driver to the Driver Manager */
216void spwtdp_register_drv(void);
217
218/* Open a SPWTDP device by registration order index. A SPWTDP device can only by
219 * opened once. The handle returned must be used as the input parameter 'spwtdp'
220 * in the rest of the calls in the function interface.
221 */
222extern void *spwtdp_open(int dev_no);
223
224/* Close a previously opened SPWTDP device */
225extern int spwtdp_close(void *spwtdp);
226
227/* Reset SPWTDP Core */
228extern int spwtdp_reset(void *spwtdp);
229
230/* Setup the frequency configuration registers */
231extern int spwtdp_freq_setup(void *spwtdp, uint32_t fsinc, uint32_t cv,
232 uint8_t etinc);
233
234/* Unmask Interrupts at Interrupt controller */
235extern int spwtdp_interrupt_unmask(void *spwtdp, uint32_t irqmask);
236
237/* Mask Interrupts at Interrupt controller */
238extern int spwtdp_interrupt_mask(void *spwtdp, uint32_t irqmask);
239
240/* Function ISR callback prototype
241 *
242 * ists - Interrupt STatus register of the SPWTDP core read by ISR
243 * data - Custom data provided by user
244 */
245typedef void (*spwtdp_isr_t)(unsigned int ists, void *data);
246
247/* Register an Interrupt handler and custom data, the function call is
248 * removed by calling unregister function.
249 */
250extern int spwtdp_isr_register(void *spwtdp, spwtdp_isr_t isr, void *data);
251
252/* Unregister an Interrupt handler */
253extern int spwtdp_isr_unregister(void *spwtdp);
254
255/* Get and clear interrupt status */
256extern int spwtdp_interrupt_status(void *spwtdp, uint32_t *sts,
257 uint32_t clrmask);
258
259/* Setup Initiator and target */
260#define SPWTDP_TDP_ENABLE CONF0_TD
261#define SPWTDP_TDP_DISABLE 0
262#define SPWTDP_LATENCY_ENABLE CONF0_LE
263#define SPWTDP_LATENCY_DISABLE 0
264#define SPWTDP_EXTET_INC_POLARITY_RISING CONF0_EP
265#define SPWTDP_EXTET_INC_POLARITY_FALLING 0
266#define SPWTDP_EXTET_INC_ENABLE CONF0_ET
267#define SPWTDP_EXTET_INC_DISABLE 0
268#define SPWTDP_EXTET_POLARITY_RISING CONF0_SP
269#define SPWTDP_EXTET_POLARITY_FALLING 0
270#define SPWTDP_EXTET_ENABLE CONF0_SE
271#define SPWTDP_EXTET_DISABLE 0
272#define SPWTDP_TARGET_SPWSYNC_ENABLE CONF0_ST
273#define SPWTDP_TARGET_SPWSYNC_DISABLE 0
274#define SPWTDP_TARGET_JITTERC_ENABLE CONF0_JE
275#define SPWTDP_TARGET_JITTERC_DISABLE 0
276#define SPWTDP_TARGET_MITIGATION_ENABLE CONF0_ME
277#define SPWTDP_TARGET_MITIGATION_DISABLE 0
278extern int spwtdp_initiator_conf(void *spwtdp, uint8_t mapping,
279 uint32_t options);
280extern int spwtdp_target_conf(void *spwtdp, uint8_t mapping, uint32_t options);
281
282/* Setup Initiator and target dist interrupts */
283extern int spwtdp_initiator_int_conf(void *spwtdp, uint8_t stm, uint8_t inrx,
284 uint8_t intx);
285#define SPWTDP_TARGET_DISTINT_INTACK CONF3_DI
286#define SPWTDP_TARGET_DISTINT_INT 0
287extern int spwtdp_target_int_conf(void *spwtdp, uint8_t inrx, uint8_t intx,
288 uint32_t options);
289
290/* Enable Initiator and target */
291extern int spwtdp_initiator_enable(void *spwtdp);
292extern int spwtdp_target_enable(void *spwtdp);
293
294/* Disable Initiator and target */
295extern int spwtdp_initiator_disable(void *spwtdp);
296extern int spwtdp_target_disable(void *spwtdp);
297
298/* Get and clear status */
299extern int spwtdp_status(void *spwtdp, uint32_t *sts, uint32_t clrmask);
300
301/* Define time struct */
302/* Length of the max data sample (136 bits), aligned to the next 32-bit word
303 * (160 bits=20 byte=5 words)
304 */
305#define SPWTDP_TIME_DATA_LENGTH 20
306struct spwtdp_time_t {
307 uint8_t data[SPWTDP_TIME_DATA_LENGTH];
308 uint32_t preamble;
309};
310typedef struct spwtdp_time_t spwtdp_time_t;
311
312/* Get datation elapsed time */
313extern int spwtdp_dat_et_get(void *spwtdp, spwtdp_time_t * val);
314extern int spwtdp_tsrx_et_get(void *spwtdp, spwtdp_time_t * val);
315extern int spwtdp_tstx_et_get(void *spwtdp, spwtdp_time_t * val);
316extern int spwtdp_lat_et_get(void *spwtdp, spwtdp_time_t * val);
317extern int spwtdp_cmd_et_get(void *spwtdp, spwtdp_time_t * val);
318
319/* Configure TSTX */
320extern int spwtdp_initiator_tstx_conf(void *spwtdp, uint8_t tstc);
321
322/* Manage control register */
323extern int spwtdp_initiator_cmd_et_set(void *spwtdp, spwtdp_time_t val);
324extern int spwtdp_initiator_cmd_spwtc_set(void *spwtdp, uint8_t spwtc);
325#define SPWTDP_TARGET_CTRL_NEWCOMMAND_ENABLE CTRL_NC
326#define SPWTDP_TARGET_CTRL_NEWCOMMAND_DISABLE 0
327#define SPWTDP_TARGET_CTRL_INIT CTRL_IS
328#define SPWTDP_TARGET_CTRL_SYNC 0
329extern int spwtdp_target_cmd_conf(void *spwtdp, uint8_t spwtc, uint16_t cpf,
330 uint32_t options);
331
332/* Get precision */
333extern int spwtdp_precision_get(void *spwtdp, uint8_t *fine, uint8_t *coarse);
334
335#ifdef __cplusplus
336}
337#endif
338
339#endif
spwtdp_regs
Definition: spwtdp.h:48
spwtdp_time_t
Definition: spwtdp.h:306
spwtdp
This structure defines the SPWTDP register block memory map.
Definition: spwtdp-regs.h:1055
cv
unsigned cv
Definition: tte.h:15
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