RTEMS 6.1-rc5
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spr.h
1/*
2 * spr.h -- Access to special purpose registers.
3 *
4 * Copyright (C) 1998 Gabriel Paubert, paubert@iram.es
5 *
6 * Modified to compile in RTEMS development environment
7 * by Eric Valette
8 *
9 * Copyright (C) 1999 Eric Valette. valette@crf.canon.fr
10 *
11 * The license and distribution terms for this file may be
12 * found in the file LICENSE in this distribution or at
13 * http://www.rtems.org/license/LICENSE.
14 *
15 */
16
17
18#ifndef _LIBCPU_SPR_H
19#define _LIBCPU_SPR_H
20
22
23#define __MFSPR(reg, val) \
24 __asm__ __volatile__("mfspr %0,"#reg : "=r" (val))
25
26#define __MTSPR(val, reg) \
27 __asm__ __volatile__("mtspr "#reg",%0" : : "r" (val))
28
29
30#define SPR_RW(reg) \
31static inline unsigned long _read_##reg(void) \
32{\
33 unsigned long val;\
34 __MFSPR(reg, val);\
35 return val;\
36}\
37static inline void _write_##reg(unsigned long val)\
38{\
39 __MTSPR(val,reg);\
40 return;\
41}
42
43#define SPR_RO(reg) \
44static inline unsigned long _read_##reg(void) \
45{\
46 unsigned long val;\
47 __MFSPR(reg,val);\
48 return val;\
49}
50
51static inline unsigned long _read_MSR(void)
52{
53 unsigned long val;
54 __asm__ volatile("mfmsr %0" : "=r" (val));
55 return val;
56}
57
58static inline void _write_MSR(unsigned long val)
59{
60 __asm__ volatile("mtmsr %0" : : "r" (val));
61 return;
62}
63
64static inline unsigned long _read_SR(void * va)
65{
66 unsigned long val;
67 __asm__ volatile (
68 ".machine \"push\"\n"
69 ".machine \"any\"\n"
70 "mfsrin %0,%1\n"
71 ".machine \"pop\"" :
72 "=r" (val) :
73 "r" (va)
74 );
75 return val;
76}
77
78static inline void _write_SR(unsigned long val, void * va)
79{
80 __asm__ volatile (
81 ".machine \"push\"\n"
82 ".machine \"any\"\n"
83 "mtsrin %0,%1\n"
84 ".machine \"pop\"" : :
85 "r" (val) , "r" (va) :
86 "memory"
87 );
88 return;
89}
90
91
92#endif