44#ifndef _RTEMS_SCORE_SPARC_H
45#define _RTEMS_SCORE_SPARC_H
76#define SPARC_HAS_BITSCAN 0
84#define SPARC_NUMBER_OF_REGISTER_WINDOWS 8
90#if defined(__FIX_LEON3FT_B2BST)
91 #define SPARC_LEON3FT_B2BST_NOP nop
93 #define SPARC_LEON3FT_B2BST_NOP
101#if defined(_SOFT_FLOAT)
102 #define SPARC_HAS_FPU 0
104 #define SPARC_HAS_FPU 1
112 #define CPU_MODEL_NAME "w/FPU"
114 #define CPU_MODEL_NAME "w/soft-float"
120#define CPU_NAME "SPARC"
131#if (SPARC_NUMBER_OF_REGISTER_WINDOWS == 8)
132 #define SPARC_PSR_CWP_MASK 0x07
133#elif (SPARC_NUMBER_OF_REGISTER_WINDOWS == 16)
134 #define SPARC_PSR_CWP_MASK 0x0F
135#elif (SPARC_NUMBER_OF_REGISTER_WINDOWS == 32)
136 #define SPARC_PSR_CWP_MASK 0x1F
138 #error "Unsupported number of register windows for this cpu"
142#define SPARC_PSR_ET_MASK 0x00000020
144#define SPARC_PSR_PS_MASK 0x00000040
146#define SPARC_PSR_S_MASK 0x00000080
148#define SPARC_PSR_PIL_MASK 0x00000F00
150#define SPARC_PSR_EF_MASK 0x00001000
152#define SPARC_PSR_EC_MASK 0x00002000
154#define SPARC_PSR_ICC_MASK 0x00F00000
156#define SPARC_PSR_VER_MASK 0x0F000000
158#define SPARC_PSR_IMPL_MASK 0xF0000000
161#define SPARC_PSR_CWP_BIT_POSITION 0
163#define SPARC_PSR_ET_BIT_POSITION 5
165#define SPARC_PSR_PS_BIT_POSITION 6
167#define SPARC_PSR_S_BIT_POSITION 7
169#define SPARC_PSR_PIL_BIT_POSITION 8
171#define SPARC_PSR_EF_BIT_POSITION 12
173#define SPARC_PSR_EC_BIT_POSITION 13
175#define SPARC_PSR_ICC_BIT_POSITION 20
177#define SPARC_PSR_VER_BIT_POSITION 24
179#define SPARC_PSR_IMPL_BIT_POSITION 28
181#define LEON3_ASR17_PROCESSOR_INDEX_SHIFT 28
184#define SPARC_SWTRAP_SYSCALL 0
185#define SPARC_SWTRAP_IRQDIS 9
186#define SPARC_SWTRAP_IRQEN 10
187#if SPARC_HAS_FPU == 1
188#define SPARC_SWTRAP_IRQDIS_FP 11
195#define SPARC_SYNCHRONOUS_TRAP_BIT_MASK 0x100
206#define SPARC_ASYNCHRONOUS_TRAP( _vector ) ( _vector )
217#define SPARC_SYNCHRONOUS_TRAP( _vector ) ( ( _vector ) + 256 )
228#define SPARC_REAL_TRAP_NUMBER( _trap ) ( ( _trap ) % 256 )
243#define SPARC_IS_INTERRUPT_TRAP( _trap ) \
244 ( SPARC_REAL_TRAP_NUMBER( _trap ) >= 0x11 && \
245 SPARC_REAL_TRAP_NUMBER( _trap ) <= 0x1f )
261#define SPARC_INTERRUPT_TRAP_TO_SOURCE( _trap ) \
262 ( SPARC_REAL_TRAP_NUMBER( _trap ) - 0x10 )
273#define SPARC_INTERRUPT_SOURCE_TO_TRAP( _source ) \
274 ( SPARC_ASYNCHRONOUS_TRAP( _source ) + 0x10 )
283 __asm__ volatile ( "nop" ); \
291#if defined(RTEMS_PARAVIRT)
293uint32_t _SPARC_Get_PSR(
void );
295#define sparc_get_psr( _psr ) \
296 (_psr) = _SPARC_Get_PSR()
300#define sparc_get_psr( _psr ) \
303 __asm__ volatile( "rd %%psr, %0" : "=r" (_psr) : "0" (_psr) ); \
313#if defined(RTEMS_PARAVIRT)
315void _SPARC_Set_PSR( uint32_t new_psr );
317#define sparc_set_psr( _psr ) \
318 _SPARC_Set_PSR( _psr )
322#define sparc_set_psr( _psr ) \
324 __asm__ volatile ( "mov %0, %%psr " : "=r" ((_psr)) : "0" ((_psr)) ); \
337#if defined(RTEMS_PARAVIRT)
339uint32_t _SPARC_Get_TBR(
void );
341#define sparc_get_tbr( _tbr ) \
342 (_tbr) = _SPARC_Get_TBR()
346#define sparc_get_tbr( _tbr ) \
349 __asm__ volatile( "rd %%tbr, %0" : "=r" (_tbr) : "0" (_tbr) ); \
359#if defined(RTEMS_PARAVIRT)
361void _SPARC_Set_TBR( uint32_t new_tbr );
363#define sparc_set_tbr( _tbr ) \
364 _SPARC_Set_TBR((_tbr))
368#define sparc_set_tbr( _tbr ) \
370 __asm__ volatile( "wr %0, 0, %%tbr" : "=r" (_tbr) : "0" (_tbr) ); \
380#define sparc_get_wim( _wim ) \
382 __asm__ volatile( "rd %%wim, %0" : "=r" (_wim) : "0" (_wim) ); \
390#define sparc_set_wim( _wim ) \
392 __asm__ volatile( "wr %0, %%wim" : "=r" (_wim) : "0" (_wim) ); \
403#define sparc_get_y( _y ) \
405 __asm__ volatile( "rd %%y, %0" : "=r" (_y) : "0" (_y) ); \
413#define sparc_set_y( _y ) \
415 __asm__ volatile( "wr %0, %%y" : "=r" (_y) : "0" (_y) ); \
425static inline uint32_t sparc_disable_interrupts(
void)
427 register uint32_t psr __asm__(
"g1");
428#ifdef __FIX_LEON3FT_TN0018
429 __asm__
volatile (
"ta %1\n\tnop\n\t" :
"=r" (psr) :
"i" (SPARC_SWTRAP_IRQDIS));
431 __asm__
volatile (
"ta %1\n\t" :
"=r" (psr) :
"i" (SPARC_SWTRAP_IRQDIS));
443static inline void sparc_enable_interrupts(uint32_t psr)
445 register uint32_t _psr __asm__(
"g1") = psr;
453 __asm__
volatile (
"ta %0\nnop\n" ::
"i" (SPARC_SWTRAP_IRQEN),
"r" (_psr));
490#define sparc_flash_interrupts( _psr ) \
492 sparc_enable_interrupts( (_psr) ); \
493 _psr = sparc_disable_interrupts(); \
503#define sparc_get_interrupt_level( _level ) \
505 uint32_t _psr_level = 0; \
507 sparc_get_psr( _psr_level ); \
509 (_psr_level & SPARC_PSR_PIL_MASK) >> SPARC_PSR_PIL_BIT_POSITION; \
512static inline uint32_t _LEON3_Get_current_processor(
void )
521 return asr17 >> LEON3_ASR17_PROCESSOR_INDEX_SHIFT;
This header file provides basic definitions used by the API and the implementation.
#define RTEMS_NO_RETURN
Tells the compiler in a function declaration that this function does not return.
Definition: basedefs.h:386
RTEMS_NO_RETURN void sparc_syscall_exit(uint32_t exitcode1, uint32_t exitcode2)
SPARC exit through system call 1.