RTEMS
6.1-rc5
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bsps
powerpc
include
libcpu
pte121.h
1
#ifndef _LIBCPU_PTE121_H
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#define _LIBCPU_PTE121_H
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/*
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* Authorship
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* ----------
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* This software was created by
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* Till Straumann <strauman@slac.stanford.edu>, 4/2002, 2003, 2004,
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* Stanford Linear Accelerator Center, Stanford University.
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*
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* Acknowledgement of sponsorship
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* ------------------------------
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* This software was produced by
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* the Stanford Linear Accelerator Center, Stanford University,
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* under Contract DE-AC03-76SFO0515 with the Department of Energy.
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*
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* Government disclaimer of liability
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* ----------------------------------
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* Neither the United States nor the United States Department of Energy,
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* nor any of their employees, makes any warranty, express or implied, or
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* assumes any legal liability or responsibility for the accuracy,
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* completeness, or usefulness of any data, apparatus, product, or process
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* disclosed, or represents that its use would not infringe privately owned
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* rights.
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*
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* Stanford disclaimer of liability
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* --------------------------------
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* Stanford University makes no representations or warranties, express or
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* implied, nor assumes any liability for the use of this software.
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*
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* Stanford disclaimer of copyright
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* --------------------------------
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* Stanford University, owner of the copyright, hereby disclaims its
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* copyright and all other rights in this software. Hence, anyone may
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* freely use it for any purpose without restriction.
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*
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* Maintenance of notices
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* ----------------------
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* In the interest of clarity regarding the origin and status of this
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* SLAC software, this and all the preceding Stanford University notices
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* are to remain affixed to any copy or derivative of this software made
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* or distributed by the recipient and are to be affixed to any copy of
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* software made or distributed by the recipient that contains a copy or
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* derivative of this software.
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*
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* ------------------ SLAC Software Notices, Set 4 OTT.002a, 2004 FEB 03
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*/
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/* Rudimentary page/hash table support for Powerpc
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*
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* A simple, static (i.e. no 'per-process' virtual
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* address space etc.) page table providing
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* one-to-one effective <-> virtual <-> physical
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* address mapping.
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*
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* PURPOSE:
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* 1) allow write-protection of text/read-only data areas
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* 2) provide more effective-address space in case
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* the BATs are not enough
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* 3) allow 'alias' mappings. Such aliases can only use
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* the upper bits of the VSID since VSID & 0xf and the
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* PI are always mapped 1:1 to the RPN.
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* LIMITATIONS:
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* - no PTE replacement (makes no sense in a real-time
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* environment, anyway) -> the page table just MUST
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* be big enough!.
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* - only one page table supported.
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* - no locking implemented. If multiple threads modify
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* the page table, it is the user's responsibility to
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* implement exclusive access.
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*/
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/* I don't include mmu.h here because it says it's derived from linux
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* and I want to avoid licensing problems
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*/
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/* Abstract handle for a page table */
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typedef
struct
Triv121PgTblRec_
*
Triv121PgTbl
;
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/* A PTE entry */
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typedef
struct
PTERec_
{
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volatile
unsigned
long
v:1, vsid:24, h:1, api: 6;
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volatile
unsigned
long
rpn:20, pad: 3, r:1, c:1, wimg:4, marked:1, pp:2;
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}
PTERec
, *
APte
;
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/* Initialize a trivial page table
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* using 2^ldSize bytes of memory starting at
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* 'base'.
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*
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* RETURNS: a handle to the internal data structure
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* used to manage the page table. NULL on
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* error.
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*
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* NOTES: - 'base' must be aligned to the size
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* - minimal ldSize is 16 (== 64k)
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* - this routine maps the page table itself
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* with read-only access. While this prevents
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* the CPU from overwriting the page table,
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* it can still be corrupted by PCI bus masters
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* (like DMA engines, [VME] bridges etc.) and
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* even by this CPU if either the MMU is off
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* or if there is a DBAT mapping granting write
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* access...
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*/
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Triv121PgTbl
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triv121PgTblInit(
unsigned
long
base,
unsigned
ldSize);
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/* get the log2 of the minimal page table size needed
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* for mapping 'size' bytes.
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*
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* EXAMPLE: create a page table which maps the entire
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* physical memory. The page table itself shall
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* be allocated at the top of the available
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* memory (assuming 'memsize' is a power of two):
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*
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* ldSize = triv121PgTblLdMinSize(memsize);
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* memsize -= (1<<ldSize); / * reduce memory available to RTEMS * /
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* pgTbl = triv121PgTblInit(memsize,ldSize);
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*
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*/
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unsigned
long
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triv121PgTblLdMinSize(
unsigned
long
size);
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/* Map an address range 1:1 in pgTbl with the given protection;
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*
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* RETURNS: -1 (TRIV121_MAP_SUCCESS) on success; the page index
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* for which no PTE could be allocated, on failure.
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*
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* NOTES: - This routine returns MINUS ONE ON SUCCESS
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* - (parts) of a mapping which overlap with
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* already existing PTEs are silently ignored.
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*
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* Therefore, you can e.g. first create
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* a couple of write protected maps and
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* finally map the entire memory r/w. This
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* will leave the write protected maps
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* intact.
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*/
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long
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triv121PgTblMap(
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Triv121PgTbl
pgTbl,
/* handle, returned by Init or Get */
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long
vsid,
/* vsid for this mapping (contains topmost 4 bits of EA);
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*
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* NOTE: it is allowed to pass a VSID < 0 to tell this
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* routine it should use a VSID corresponding to a
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* 1:1:1 effective - virtual - physical mapping
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*/
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unsigned
long
start,
/* segment offset (lowermost 28 bits of EA) of address range
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*
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* NOTE: if VSID < 0 (TRIV121_121_VSID), 'start' is inter-
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* preted as an effective address (EA), i.e. all 32
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* bits are used - the most significant four going into
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* to the VSID...
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*/
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unsigned
long
numPages,
/* number of pages to map */
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unsigned
wimgAttr,
/* 'wimg' attributes
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* (Write thru, cache Inhibit, coherent Memory,
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* Guarded memory)
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*/
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unsigned
protection
/* 'pp' access protection: Super User
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*
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* 0 r/w none
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* 1 r/w ro
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* 2 r/w r/w
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* 3 ro ro
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*/
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);
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#define TRIV121_ATTR_W 8
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#define TRIV121_ATTR_I 4
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#define TRIV121_ATTR_M 2
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#define TRIV121_ATTR_G 1
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/* for I/O pages (e.g. PCI, VME addresses) use cache inhibited
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* and guarded pages. RTM about the 'eieio' instruction!
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*/
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#define TRIV121_ATTR_IO_PAGE (TRIV121_ATTR_I|TRIV121_ATTR_G)
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#define TRIV121_PP_RO_PAGE (1)
/* read-only for key = 1, unlocked by key=0 */
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#define TRIV121_PP_RW_PAGE (2)
/* read-write for key = 1/0 */
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#define TRIV121_121_VSID (-1)
/* use 1:1 effective<->virtual address mapping */
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#define TRIV121_SEG_VSID (-2)
/* lookup VSID in the segment register */
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#define TRIV121_MAP_SUCCESS (-1)
/* triv121PgTblMap() returns this on SUCCESS */
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/* get a handle to the one and only page table
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* (must have been initialized/allocated)
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*
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* RETURNS: NULL if the page table has not been initialized/allocated.
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*/
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Triv121PgTbl
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triv121PgTblGet(
void
);
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/*
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* compute the SDR1 register value for the page table
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*/
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unsigned
long
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triv121PgTblSDR1(
Triv121PgTbl
pgTbl);
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/*
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* Activate the page table:
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* - set up the segment registers for a 1:1 effective <-> virtual address mapping,
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* give user and supervisor keys.
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* - set up the SDR1 register
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* - flush all tlbs
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* - 'lock' pgTbl, i.e. prevent all further modifications.
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*
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* NOTE: This routine does not change any BATs. Since these
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* have priority over the page table, the user
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* may have to switch overlapping BATs OFF in order
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* for the page table mappings to take effect.
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*/
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void
triv121PgTblActivate(
Triv121PgTbl
pgTbl);
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/* Find the PTE for a EA and print its contents to stdout
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* RETURNS: pte for EA or NULL if no entry was found.
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*/
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APte
triv121DumpEa(
unsigned
long
ea);
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/* Find and return a PTE for a vsid/pi combination
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* RETURNS: pte or NULL if no entry was found
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*/
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APte
triv121FindPte(
unsigned
long
vsid,
unsigned
long
pi);
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/*
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* Unmap an effective address
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*
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* RETURNS: pte that mapped the ea or NULL if no
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* mapping existed.
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*/
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APte
triv121UnmapEa(
unsigned
long
ea);
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/*
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* Change the WIMG and PP attributes of the page containing 'ea'
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*
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* NOTES: The 'wimg' and 'pp' may be <0 to indicate that no
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* change is desired.
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*
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* RETURNS: Pointer to modified PTE or NULL if 'ea' is not mapped.
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*/
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APte
triv121ChangeEaAttributes(
unsigned
long
ea,
int
wimg,
int
pp);
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/* Make the whole page table writable
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* NOTES: If the page table has not been initialized yet,
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* this routine has no effect (i.e., after
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* initialization the page table will still be read-only).
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*/
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void
triv121MakePgTblRW(
void
);
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/* Make the whole page table read-only
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*/
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void
triv121MakePgTblRO(
void
);
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/* Dump a pte to stdout */
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long
triv121DumpPte(
APte
pte
);
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#endif
PTERec_
Definition:
pte121.h:82
Triv121PgTblRec_
Definition:
pte121.c:219
_pte
Definition:
mmu.h:130
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