1#ifndef _MPC83XX_MPC83XX_H
2#define _MPC83XX_MPC83XX_H
6#if MPC83XX_CHIP_TYPE == 8343
7#define M83xx_HAS_PCI TRUE
8#define M83xx_HAS_USB1 TRUE
9#elif MPC83XX_CHIP_TYPE == 8347
10#define M83xx_HAS_PCI TRUE
11#define M83xx_HAS_USB1 TRUE
12#define M83xx_HAS_USB2 TRUE
13#elif MPC83XX_CHIP_TYPE == 8349
14#define M83xx_HAS_PCI TRUE
15#define M83xx_HAS_WIDE_PCI TRUE
16#define M83xx_HAS_USB1 TRUE
17#define M83xx_HAS_USB2 TRUE
18#elif MPC83XX_CHIP_TYPE == 8360
19#define M83xx_HAS_PCI TRUE
20#define M83xx_HAS_QE TRUE
31 volatile uint32_t immrbar;
32 uint8_t reserved0_0004[0x00008-0x00004];
33 volatile uint32_t altcbar;
34 uint8_t reserved0_000C[0x00020-0x0000C];
35 volatile uint32_t lblawbar0;
36 volatile uint32_t lblawar0;
37 volatile uint32_t lblawbar1;
38 volatile uint32_t lblawar1;
39 volatile uint32_t lblawbar2;
40 volatile uint32_t lblawar2;
41 volatile uint32_t lblawbar3;
42 volatile uint32_t lblawar3;
43 uint8_t reserved0_0040[0x00060-0x00040];
44 volatile uint32_t pcilawbar0;
45 volatile uint32_t pcilawar0;
46 volatile uint32_t pcilawbar1;
47 volatile uint32_t pcilawar1;
48 uint8_t reserved0_0070[0x000A0-0x00070];
49 volatile uint32_t ddrlawbar0;
50 volatile uint32_t ddrlawar0;
51 volatile uint32_t ddrlawbar1;
52 volatile uint32_t ddrlawar1;
53 uint8_t reserved0_00B0[0x00100-0x000B0];
54 volatile uint32_t sgprl;
55 volatile uint32_t sgprh;
56 volatile uint32_t spridr;
57 uint8_t reserved0_010C[0x00110-0x0010C];
58 volatile uint32_t spcr;
59 volatile uint32_t sicrl;
60 volatile uint32_t sicrh;
61 uint8_t reserved0_011C[0x00128-0x0011C];
62 volatile uint32_t ddrcdr;
63 volatile uint32_t ddrdsr;
64 uint8_t reserved0_0130[0x00150-0x00130];
65 volatile uint32_t gpr_1;
66 uint8_t reserved0_0154[0x00200-0x00154];
68#define M83xx_SYSCON_SPCR_TBEN (1 << (31-9))
72 uint8_t reserved0_0200[0x00204-0x00200];
73 volatile uint32_t swcrr;
74 volatile uint32_t swcnr;
75 uint8_t reserved0_020C[(0x0020E)-0x0020C];
76 volatile uint16_t swsrr;
81 volatile uint32_t rtcnr;
82 volatile uint32_t rtldr;
83 volatile uint32_t rtpsr;
84 volatile uint32_t rtctr;
85 volatile uint32_t rtevr;
86 volatile uint32_t rtalr;
87 uint8_t reserved0_0314[0x00320-0x00318];
92 volatile uint32_t ptcnr;
93 volatile uint32_t ptldr;
94 volatile uint32_t ptpsr;
95 volatile uint32_t ptctr;
96 volatile uint32_t ptevr;
97 uint8_t reserved0_0414[0x00500-0x00414];
101#define M83xxGTIdx(n) (n&3)
102#define M83xxGTLowIdx(n) (n&1)
103#define M83xxGTHighIdx(n) (((n)>>1)&1)
104#define M83xxGTModIdx(n) (((n)>>2)&1)
106#define M83xxGTIdxCnt (4)
107#define M83xxGTLowCnt (2)
108#define M83xxGTHighCnt (2)
109#define M83xxGTModCnt (2)
113 volatile uint8_t reg;
114 uint8_t reserved0_0501[0x00504-0x00501];
115 } gtcfr[M83xxGTHighCnt];
116 uint8_t reserved0_0508[0x00510-0x00508];
118 volatile uint16_t gtmdr[M83xxGTLowCnt];
119 volatile uint16_t gtrfr[M83xxGTLowCnt];
120 volatile uint16_t gtcpr[M83xxGTLowCnt];
121 volatile uint16_t gtcnr[M83xxGTLowCnt];
122 } gt_tim_regs[M83xxGTHighCnt];
123 volatile uint16_t gtevr[M83xxGTIdxCnt];
124 volatile uint16_t gtpsr[M83xxGTIdxCnt];
125 uint8_t reserved0_0540[0x00600-0x00540];
130 volatile uint32_t sicfr;
131 volatile uint32_t sivcr;
132 volatile uint32_t sipnr[2];
133 volatile uint32_t siprr[4];
134 volatile uint32_t simsr[2];
135 uint8_t reserved0_0728[0x0072C-0x00728];
136 volatile uint32_t sepnr;
137 volatile uint32_t smprr[2];
138 volatile uint32_t semsr;
139 volatile uint32_t secnr;
140 volatile uint32_t sersr;
141 volatile uint32_t sermr;
142 volatile uint32_t sercr;
143 uint8_t reserved0_074C[0x00750-0x0074C];
144 volatile uint32_t sifcr[2];
145 volatile uint32_t sefcr;
146 volatile uint32_t serfr;
147 volatile uint32_t scvcr;
148 volatile uint32_t smvcr;
149 uint8_t reserved0_0760[0x00800-0x00768];
153#define MPC83xx_VCR_TO_VEC(regval) ((regval) & 0x7f)
158 volatile uint32_t acr;
159 volatile uint32_t atr;
160 uint8_t reserved0_0808[0x0080C-0x00808];
161 volatile uint32_t aer;
162 volatile uint32_t aidr;
163 volatile uint32_t amr;
164 volatile uint32_t aeatr;
165 volatile uint32_t aeadr;
166 volatile uint32_t aerr;
167 uint8_t reserved0_0824[0x00900-0x00824];
172 volatile uint32_t rcwlr;
173 volatile uint32_t rcwhr;
174 uint8_t reserved0_0908[0x00910-0x00908];
175 volatile uint32_t rsr;
176 volatile uint32_t rmr;
177 volatile uint32_t rpr;
178 volatile uint32_t rcr;
179 volatile uint32_t rcer;
180 uint8_t reserved0_0924[0x00A00-0x00924];
185 volatile uint32_t spmr;
186 volatile uint32_t occr;
187 volatile uint32_t sccr;
188 uint8_t reserved0_0A08[0x00B00-0x00A0C];
192 volatile uint32_t pmccr;
193 volatile uint32_t pmcer;
194 volatile uint32_t pmcmr;
195 uint8_t reserved0_0B10[0x00C00-0x00B0C];
199 volatile uint32_t gpdir;
200 volatile uint32_t gpdr;
201 volatile uint32_t gpdat;
202 volatile uint32_t gpier;
203 volatile uint32_t gpimr;
204 volatile uint32_t gpicr;
205 uint8_t reserved0_0C1C[0x00D00-0x00C18];
210 uint8_t reserved0_1000[0x01010-0x01000];
211 volatile uint32_t mckenr;
212 uint8_t reserved0_1014[0x01100-0x01014];
213 volatile uint32_t reserved0_1100;
214 volatile uint32_t reserved0_1104;
215 volatile uint32_t dllovr;
216 volatile uint32_t dllsr;
217 volatile uint32_t dllck;
218 uint8_t reserved0_1110[0x01200-0x01114];
223 volatile uint32_t cs0_bnds;
224 uint8_t reserved0_2004[0x02008-0x02004];
225 volatile uint32_t cs1_bnds;
226 uint8_t reserved0_200C[0x02010-0x0200C];
227 volatile uint32_t cs2_bnds;
228 uint8_t reserved0_2014[0x02018-0x02014];
229 volatile uint32_t cs3_bnds;
230 uint8_t reserved0_201C[0x02080-0x0201C];
231 volatile uint32_t cs0_config;
232 volatile uint32_t cs1_config;
233 volatile uint32_t cs2_config;
234 volatile uint32_t cs3_config;
235 uint8_t reserved0_2090[0x02100-0x02090];
236 volatile uint32_t timing_cfg_3;
237 volatile uint32_t timing_cfg_0;
238 volatile uint32_t timing_cfg_1;
239 volatile uint32_t timing_cfg_2;
240 volatile uint32_t ddr_sdram_cfg;
241 volatile uint32_t ddr_sdram_cfg_2;
242 volatile uint32_t ddr_sdram_mode;
243 volatile uint32_t ddr_sdram_mode_2;
244 volatile uint32_t ddr_sdram_md_cntl;
245 volatile uint32_t ddr_sdram_interval;
246 volatile uint32_t ddr_data_init;
247 uint8_t reserved0_212C[0x02130-0x0212C];
248 volatile uint32_t ddr_sdram_clk_cntl;
249 uint8_t reserved0_2134[0x02148-0x02134];
250 volatile uint32_t ddr_init_address;
251 uint8_t reserved0_214C[0x02BF8-0x0214C];
252 volatile uint32_t ddr_ip_rev1;
253 volatile uint32_t ddr_ip_rev2;
254 uint8_t reserved0_2C00[0x02E00-0x02C00];
255 volatile uint32_t data_err_inject_hi;
256 volatile uint32_t data_err_inject_lo;
257 volatile uint32_t ecc_err_inject;
258 uint8_t reserved0_2E0C[0x02E20-0x02E0C];
259 volatile uint32_t capture_data_hi;
260 volatile uint32_t capture_data_lo;
261 volatile uint32_t capture_ecc;
262 uint8_t reserved0_2E2C[0x02E40-0x02E2C];
263 volatile uint32_t err_detect;
264 volatile uint32_t err_disable;
265 volatile uint32_t err_int_en;
266 volatile uint32_t capture_attributes;
267 volatile uint32_t capture_address;
268 uint8_t reserved0_2E54[0x02E58-0x02E54];
269 volatile uint32_t err_sbe;
270 uint8_t reserved0_2E5C[0x2F00-0x2E5C];
275 volatile uint8_t i2cadr;
276 uint8_t reserved0_3001[0x03004-0x03001];
277 volatile uint8_t i2cfdr;
278 uint8_t reserved0_3005[0x03008-0x03005];
279 volatile uint8_t i2ccr;
280 uint8_t reserved0_3009[0x0300C-0x03009];
281 volatile uint8_t i2csr;
282 uint8_t reserved0_300D[0x03010-0x0300D];
283 volatile uint8_t i2cdr;
284 uint8_t reserved0_3011[0x03014-0x03011];
285 volatile uint8_t i2cdfsrr;
286 uint8_t reserved0_3015[0x03018-0x03015];
287 uint8_t reserved0_3018[0x03100-0x03018];
293 volatile uint8_t urbr;
294 volatile uint8_t uthr;
295 volatile uint8_t udlb;
298 volatile uint8_t uier;
299 volatile uint8_t udmb;
302 volatile uint8_t uiir;
303 volatile uint8_t ufcr;
304 volatile uint8_t uafr;
306 volatile uint8_t ulcr;
307 volatile uint8_t umcr;
308 volatile uint8_t ulsr;
309 volatile uint8_t umsr;
310 volatile uint8_t uscr;
311 uint8_t reserved0_4508[0x04510-0x04508];
312 volatile uint8_t udsr;
313 uint8_t reserved0_4511[0x04600-0x04511];
319 volatile uint32_t br;
320 volatile uint32_t optionsr;
322 uint8_t reserved0_5040[0x05068-0x05040];
323 volatile uint32_t mar;
324 uint8_t reserved0_506C[0x05070-0x0506C];
325 volatile uint32_t mamr;
326 volatile uint32_t mbmr;
327 volatile uint32_t mcmr;
328 uint8_t reserved0_507C[0x05084-0x0507C];
329 volatile uint32_t mrtpr;
330 volatile uint32_t mdr;
331 uint8_t reserved0_508C[0x05094-0x0508C];
332 volatile uint32_t lsdmr;
333 uint8_t reserved0_5098[0x050A0-0x05098];
334 volatile uint32_t lurt;
335 volatile uint32_t lsrt;
336 uint8_t reserved0_50A8[0x050B0-0x050A8];
337 volatile uint32_t ltesr;
338 volatile uint32_t ltedr;
339 volatile uint32_t lteir;
340 volatile uint32_t lteatr;
341 volatile uint32_t ltear;
342 uint8_t reserved0_50C4[0x050D0-0x050C4];
343 volatile uint32_t lbcr;
344 volatile uint32_t lcrr;
345 uint8_t reserved0_50D8[0x05100-0x050D8];
350 uint8_t reserved0_7000[0x07020-0x07000];
351 volatile uint32_t spmode;
352 volatile uint32_t spie;
353 volatile uint32_t spim;
354 volatile uint32_t spcom;
355 volatile uint32_t spitd;
356 volatile uint32_t spird;
357 uint8_t reserved0_7038[0x07100-0x07038];
360#define MPC83XX_SPIMODE_LOOP (1 << (31- 1))
361#define MPC83XX_SPIMODE_CI (1 << (31- 2))
362#define MPC83XX_SPIMODE_CP (1 << (31- 3))
363#define MPC83XX_SPIMODE_DIV16 (1 << (31- 4))
364#define MPC83XX_SPIMODE_REV (1 << (31- 5))
365#define MPC83XX_SPIMODE_M_S (1 << (31- 6))
366#define MPC83XX_SPIMODE_EN (1 << (31- 7))
367#define MPC83XX_SPIMODE_LEN(n) ((n) << (31-11))
368#define MPC83XX_SPIMODE_PM(n) ((n) << (31-15))
369#define MPC83XX_SPIMODE_OD (1 << (31-19))
372#define MPC83XX_SPCOM_LST (1 << (31- 9))
375#define MPC83XX_SPIE_LT (1 << (31-17))
376#define MPC83XX_SPIE_DNR (1 << (31-18))
377#define MPC83XX_SPIE_OV (1 << (31-19))
378#define MPC83XX_SPIE_UN (1 << (31-20))
379#define MPC83XX_SPIE_MME (1 << (31-21))
380#define MPC83XX_SPIE_NE (1 << (31-22))
381#define MPC83XX_SPIE_NF (1 << (31-23))
385 uint8_t reserved0_8000[0x08030-0x08000];
386 volatile uint32_t omisr;
387 volatile uint32_t omimr;
388 uint8_t reserved0_8038[0x08050-0x08038];
389 volatile uint32_t imr0;
390 volatile uint32_t imr1;
391 volatile uint32_t omr0;
392 volatile uint32_t omr1;
393 volatile uint32_t odr;
394 uint8_t reserved0_8064[0x08068-0x08064];
395 volatile uint32_t idr;
396 uint8_t reserved0_806C[0x08080-0x0806C];
397 volatile uint32_t imisr;
398 volatile uint32_t imimr;
399 uint8_t reserved0_8088[0x080A8-0x08088];
401 uint8_t reserved0_80A8[0x08100-0x080A8];
402 volatile uint32_t dmamr0;
403 volatile uint32_t dmasr0;
404 volatile uint32_t dmacdar0;
405 uint8_t reserved0_810C[0x08110-0x0810C];
406 volatile uint32_t dmasar0;
407 uint8_t reserved0_8114[0x08118-0x08114];
408 volatile uint32_t dmadar0;
409 uint8_t reserved0_811C[0x08120-0x0811C];
410 volatile uint32_t dmabcr0;
411 volatile uint32_t dmandar0;
413 volatile uint32_t dmagsr;
414 uint8_t reserved0_82AC[0x082FF-0x082AC];
420#define MPC83XX_DMAMR_DRCNT_1 (5 << 24)
421#define MPC83XX_DMAMR_DRCNT_2 (6 << 24)
422#define MPC83XX_DMAMR_DRCNT_4 (7 << 24)
423#define MPC83XX_DMAMR_DRCNT_8 (8 << 24)
424#define MPC83XX_DMAMR_DRCNT_16 (9 << 24)
425#define MPC83XX_DMAMR_DRCNT_32 (0xA << 24)
427#define MPC83XX_DMAMR_BWC_1 (0 << 21)
428#define MPC83XX_DMAMR_BWC_2 (1 << 21)
429#define MPC83XX_DMAMR_BWC_4 (2 << 21)
430#define MPC83XX_DMAMR_BWC_8 (3 << 21)
431#define MPC83XX_DMAMR_BWC_16 (4 << 21)
433#define MPC83XX_DMAMR_DMSEN (1 << 20)
434#define MPC83XX_DMAMR_IRQS (1 << 19)
435#define MPC83XX_DMAMR_EMSEN (1 << 18)
437#define MPC83XX_DMAMR_DAHTS_1 (0 << 16)
438#define MPC83XX_DMAMR_DAHTS_2 (1 << 16)
439#define MPC83XX_DMAMR_DAHTS_4 (2 << 16)
440#define MPC83XX_DMAMR_DAHTS_8 (3 << 16)
442#define MPC83XX_DMAMR_SAHTS_1 (0 << 14)
443#define MPC83XX_DMAMR_SAHTS_2 (1 << 14)
444#define MPC83XX_DMAMR_SAHTS_4 (2 << 14)
445#define MPC83XX_DMAMR_SAHTS_8 (3 << 14)
447#define MPC83XX_DMAMR_DAHE (1 << 13)
448#define MPC83XX_DMAMR_SAHE (1 << 12)
450#define MPC83XX_DMAMR_PRC_PCI_READ (0 << 10)
451#define MPC83XX_DMAMR_PRC_PCI_READ_LINE (1 << 10)
452#define MPC83XX_DMAMR_PRC_PCI_READ_MULTIPLE (2 << 10)
454#define MPC83XX_DMAMR_EOIIE (1 << 7)
455#define MPC83XX_DMAMR_TEM (1 << 3)
456#define MPC83XX_DMAMR_CTM (1 << 2)
457#define MPC83XX_DMAMR_CC (1 << 1)
458#define MPC83XX_DMAMR_CS (1 << 0)
461#define MPC83XX_DMASR_TE (1 << 7)
462#define MPC83XX_DMASR_CB (1 << 2)
463#define MPC83XX_DMASR_EOSI (1 << 1)
464#define MPC83XX_DMASR_EOCDI (1 << 0)
467#define MPC83XX_DMACDAR_SNEN (1 << 4)
468#define MPC83XX_DMACDAR_EOSIE (1 << 3)
471#define MPC83XX_DMANDAR_NSNEN (1 << 4)
472#define MPC83XX_DMANDAR_NEOSIE (1 << 3)
473#define MPC83XX_DMANDAR_EOTD (1 << 0)
478 volatile uint32_t config_address;
479 volatile uint32_t config_data;
480 volatile uint32_t int_ack;
481 uint8_t reserved0_830C[0x08380-0x0830C];
486 volatile uint32_t potar0;
487 uint8_t reserved0_8404[0x08408-0x08404];
488 volatile uint32_t pobar0;
489 uint8_t reserved0_840C[0x08410-0x0840C];
490 volatile uint32_t pocmr0;
491 uint8_t reserved0_8414[0x08418-0x08414];
492 volatile uint32_t potar1;
493 uint8_t reserved0_841C[0x08420-0x0841C];
494 volatile uint32_t pobar1;
495 uint8_t reserved0_8424[0x08428-0x08424];
496 volatile uint32_t pocmr1;
497 uint8_t reserved0_842C[0x08430-0x0842C];
498 volatile uint32_t potar2;
499 uint8_t reserved0_8434[0x08438-0x08434];
500 volatile uint32_t pobar2;
501 uint8_t reserved0_843C[0x08440-0x0843C];
502 volatile uint32_t pocmr2;
503 uint8_t reserved0_8444[0x08448-0x08444];
504 volatile uint32_t potar3;
505 uint8_t reserved0_844C[0x08450-0x0844C];
506 volatile uint32_t pobar3;
507 uint8_t reserved0_8454[0x08458-0x08454];
508 volatile uint32_t pocmr3;
509 uint8_t reserved0_845C[0x08460-0x0845C];
510 volatile uint32_t potar4;
511 uint8_t reserved0_8464[0x08468-0x08464];
512 volatile uint32_t pobar4;
513 uint8_t reserved0_846C[0x08470-0x0846C];
514 volatile uint32_t pocmr4;
515 uint8_t reserved0_8474[0x08478-0x08474];
516 volatile uint32_t potar5;
517 uint8_t reserved0_847C[0x08480-0x0847C];
518 volatile uint32_t pobar5;
519 uint8_t reserved0_8484[0x08488-0x08484];
520 volatile uint32_t pocmr5;
521 uint8_t reserved0_848C[0x084F0-0x0848C];
522 volatile uint32_t pmcr;
523 uint8_t reserved0_84F4[0x084F8-0x084F4];
524 volatile uint32_t dtcr;
525 uint8_t reserved0_84FC[0x08500-0x084FC];
530 volatile uint32_t pci_esr;
531 volatile uint32_t pci_ecdr;
532 volatile uint32_t pci_eer;
533 volatile uint32_t pci_eatcr;
534 volatile uint32_t pci_eacr;
535 volatile uint32_t pci_eeacr;
536 volatile uint32_t pci_edlcr;
537 volatile uint32_t pci_edhcr;
539 volatile uint32_t pci_gcr;
540 volatile uint32_t pci_ecr;
541 volatile uint32_t pci_gsr;
542 uint8_t reserved0_852C[0x08538-0x0852C];
544 volatile uint32_t pitar2;
545 uint8_t reserved0_853C[0x08540-0x0853C];
546 volatile uint32_t pibar2;
547 volatile uint32_t piebar2;
548 volatile uint32_t piwar2;
549 uint8_t reserved0_854C[0x08550-0x0854C];
550 volatile uint32_t pitar1;
551 uint8_t reserved0_8550[0x08558-0x08554];
552 volatile uint32_t pibar1;
553 volatile uint32_t piebar1;
554 volatile uint32_t piwar1;
555 uint8_t reserved0_8564[0x08568-0x08564];
556 volatile uint32_t pitar0;
557 uint8_t reserved0_856c[0x08570-0x0856c];
558 volatile uint32_t pibar0;
559 uint8_t reserved0_8574[0x08578-0x08574];
560 volatile uint32_t piwar0;
561 uint8_t reserved0_857c[0x08580-0x0857c];
562 uint8_t reserved0_8580[0x08600-0x08580];
567 uint8_t reserved0x2_2000[0x22100-0x22000];
568 volatile uint16_t caplength;
569 volatile uint16_t hciversion;
570 volatile uint32_t hcsparams;
571 volatile uint32_t hccparams;
572 uint8_t reserved0x2_210C[0x22140-0x2210C];
573 volatile uint32_t usbcmd;
574 volatile uint32_t usbsts;
575 volatile uint32_t usbintr;
576 volatile uint32_t frindex;
577 uint8_t reserved0x2_2150[0x22154-0x22150];
578 volatile uint32_t periodiclistbase;
579 volatile uint32_t asynclistaddr;
580 volatile uint32_t asyncttsts;
581 volatile uint32_t burstsize;
582 volatile uint32_t txfilltuning;
583 volatile uint32_t txttfilltuning;
584 uint8_t reserved0x2_216c[0x22170-0x2216c];
585 volatile uint32_t viewport;
586 uint8_t reserved0x2_2174[0x22180-0x22174];
587 volatile uint32_t configflag;
588 volatile uint32_t portsc1;
589 volatile uint32_t portsc2;
590 uint8_t reserved0x2_218c[0x221A8-0x2218c];
591 volatile uint32_t usbmode;
592 uint8_t reserved0x2_21AC[0x22400-0x221AC];
593 volatile uint32_t snoop1;
594 volatile uint32_t snoop2;
595 volatile uint32_t age_cnt_thresh;
596 volatile uint32_t si_ctrl;
597 volatile uint32_t pri_ctrl;
598 uint8_t reserved0x2_2414[0x22500-0x22414];
600 uint8_t reserved0x2_2504[0x23000-0x22504];
605 uint8_t reserved0x2_3000[0x23100-0x23000];
606 volatile uint16_t caplength;
607 volatile uint16_t hciversion;
608 volatile uint32_t hcsparams;
609 volatile uint32_t hccparams;
610 uint8_t reserved0x2_310c[0x23120-0x2310C];
611 volatile uint32_t dciversion;
612 volatile uint32_t dccparams;
613 uint8_t reserved0x2_3128[0x23140-0x23128];
614 volatile uint32_t usbcmd;
615 volatile uint32_t usbsts;
616 volatile uint32_t usbintr;
617 volatile uint32_t frindex;
618 uint8_t reserved0x2_3150[0x23154-0x23150];
620 volatile uint32_t periodiclistbase;
621 volatile uint32_t deviceaddr;
624 volatile uint32_t asynclistaddr;
625 volatile uint32_t addr;
627 uint8_t reserved0x2_315c[0x23160-0x2315c];
628 volatile uint32_t burstsize;
629 volatile uint32_t txfilltuning;
630 uint8_t reserved0x2_3168[0x23170-0x23168];
631 volatile uint32_t viewport;
632 uint8_t reserved0x2_3174[0x23180-0x23174];
633 volatile uint32_t configflag;
634 volatile uint32_t portsc1;
635 uint8_t reserved0x2_3188[0x231A4-0x23188];
636 volatile uint32_t otgsc;
637 volatile uint32_t usbmode;
638 volatile uint32_t endptsetupstat;
639 volatile uint32_t endpointprime;
640 volatile uint32_t endptflush;
641 volatile uint32_t endptstatus;
642 volatile uint32_t endptcomplete;
643 volatile uint32_t endptctrl[6];
644 uint8_t reserved0x2_31D8[0x23400-0x231D8];
645 volatile uint32_t snoop1;
646 volatile uint32_t snoop2;
647 volatile uint32_t age_cnt_thresh;
648 volatile uint32_t pri_ctrl;
649 volatile uint32_t si_ctrl;
650 uint8_t reserved0x2_3414[0x23500-0x23414];
652 uint8_t reserved0x2_3504[0x24000-0x23504];
658 volatile uint32_t reserved;##
659 volatile uint32_t imr;
660 volatile uint32_t isr;
661 volatile uint32_t icr;
662 volatile uint32_t id;
663 volatile uint32_t euasr;
664 volatile uint32_t mcr;
666 volatile uint32_t cccr1;
667 volatile uint32_t ccpsr1;
668 volatile uint32_t cdpr1;
674 volatile uint32_t deumr;
675 volatile uint32_t deuksr;
676 volatile uint32_t deudsr;
677 volatile uint32_t deurcr;
678 volatile uint32_t deusr;
679 volatile uint32_t deuisr;
680 volatile uint32_t deuicr;
681 volatile uint32_t deueug;
682 volatile uint32_t deuiv;
683 volatile uint32_t deuk1;
684 volatile uint32_t deuk2;
685 volatile uint32_t deuk3;
687DEU FIFO R/W 0x0000_0000_0000_0000 14.5.2.11/14-42
689 volatile uint32_t aesumr;
690 volatile uint32_t aesuksr;
691 volatile uint32_t aesudsr;
692 volatile uint32_t aesurcr;
693 volatile uint32_t aesusr;
694 volatile uint32_t aesuisr;
695 volatile uint32_t aesuicr;
696 volatile uint32_t aesuemr;
6970x3_4100 AESU
context memory registers R/W 0x0000_0000_0000_0000 14.5.6.9/14-77
699AESU key memory R/W 0x0000_0000_0000_0000 14.5.6.9.5/14-81
701AESU FIFO R/W 0x0000_0000_0000_0000 14.5.6.9.6/14-81
703 volatile uint32_t mdeumr;
704 volatile uint32_t mdeuksr;
705 volatile uint32_t mdeudsr;
706 volatile uint32_t mdeurcr;
707 volatile uint32_t mdeusr;
708 volatile uint32_t mdeuisr;
709 volatile uint32_t mdeuicr;
710 volatile uint32_t mdeueug;
712MDEU
context memory registers R/W 0x0000_0000_0000_0000 14.5.4.11/14-61
714MDEU key memory W 0x0000_0000_0000_0000 14.5.4.12/14-62
716MDEU FIFO W 0x0000_0000_0000_0000 14.5.4.13/14-63
718 volatile uint32_t afeumr;
719 volatile uint32_t afeuksr;
720 volatile uint32_t afeudsr;
721 volatile uint32_t afeurcr;
722 volatile uint32_t afeusr;
723 volatile uint32_t afeuisr;
724 volatile uint32_t afeuicr;
725 volatile uint32_t afeuemr;
727AFEU
context memory registers R/W 0x0000_0000_0000_0000 14.5.3.10.1/14-50
7280x3_8200 AFEU
context memory pointers R/W 0x0000_0000_0000_0000 14.5.3.10.2/14-51
729 volatile uint32_t afeuk0;
730 volatile uint32_t afeuk1;
732AFEU FIFO R/W 0x0000_0000_0000_0000 14.5.3.11.1/14-51
734 volatile uint32_t rngmr;
735 volatile uint32_t rngdsr;
736 volatile uint32_t rngrcr;
737 volatile uint32_t rngsr;
738 volatile uint32_t rngisr;
741 volatile uint32_t rngicr;
744 volatile uint32_t rngeug;
748RNG FIFO R 0x0000_0000
752 volatile uint32_t pkeumr;
753 volatile uint32_t pkeuksr;
754 volatile uint32_t pkeudsr;
755 volatile uint32_t pkeurcr;
756 volatile uint32_t pkeusr;
757 volatile uint32_t pkeuisr;
758 volatile uint32_t pkeuicr;
759 volatile uint32_t pkeuabs;
760 volatile uint32_t pkeueug;
762PKEU parameter memory A0 R/W 0x0000_0000_0000_0000 14.5.1.10/14-34
764PKEU parameter memory A1 R/W 0x0000_0000_0000_0000
766PKEU parameter memory A2 R/W 0x0000_0000_0000_0000
768PKEU parameter memory A3 R/W 0x0000_0000_0000_0000
770PKEU parameter memory B0 R/W 0x0000_0000_0000_0000
772PKEU parameter memory B1 R/W 0x0000_0000_0000_0000
774PKEU parameter memory B2 R/W 0x0000_0000_0000_0000
776PKEU parameter memory B3 R/W 0x0000_0000_0000_0000
778PKEU parameter memory E W 0x0000_0000_0000_0000
780PKEU parameter memory N R/W 0x0000_0000_0000_0000
786 uint8_t reserved0_0210[0x0300-0x0210];
788 uint8_t reserved0_0320[0x0400-0x0320];
797 uint8_t reserved0_0E00[0x1000-0x0E00];
799 uint8_t reserved0_1200[0x2000-0x1200];
801 uint8_t reserved0_2F00[0x3000-0x2F00];
803 uint8_t reserved0_3200[0x4000-0x3200];
804 uint8_t reserved0_4000[0x4500-0x4000];
806 uint8_t reserved0_4700[0x5000-0x4700];
808 uint8_t reserved0_5100[0x7000-0x5100];
810 uint8_t reserved0_7100[0x8000-0x7100];
815 uint8_t reserved0_8700[0x22000-0x8700];
823static inline void mpc83xx_reset(
void)
828 mpc83xx.res.rpr = 0x52535445;
834 while (mpc83xx.res.rcer != 0x00000001) {
839 mpc83xx.res.rcr = 0x00000002;
849#define IMMRBAR_DEFAULT 0xFF400000
853#define LBLAWBAR0_OFF 0x00020
854#define LBLAWAR0_OFF 0x00024
855#define LBLAWBAR1_OFF 0x00028
856#define LBLAWAR1_OFF 0x0002C
857#define LBLAWBAR2_OFF 0x00030
858#define LBLAWAR2_OFF 0x00034
859#define LBLAWBAR3_OFF 0x00038
860#define LBLAWAR3_OFF 0x0003C
861#define PCILAWBAR0_OFF 0x00060
862#define PCILAWAR0_OFF 0x00064
863#define PCILAWBAR1_OFF 0x00068
864#define PCILAWAR1_OFF 0x0006C
865#define DDRLAWBAR0_OFF 0x000A0
866#define DDRLAWAR0_OFF 0x000A4
867#define DDRLAWBAR1_OFF 0x000A8
868#define DDRLAWAR1_OFF 0x000AC
870#define BR0_OFF 0x05000
871#define OR0_OFF 0x05004
872#define BR1_OFF 0x05008
873#define OR1_OFF 0x0500C
874#define BR2_OFF 0x05010
875#define OR2_OFF 0x05014
876#define BR3_OFF 0x05018
877#define OR3_OFF 0x0501C
878#define BR4_OFF 0x05020
879#define OR4_OFF 0x05024
880#define BR5_OFF 0x05028
881#define OR5_OFF 0x0502C
882#define BR6_OFF 0x05030
883#define OR6_OFF 0x05034
884#define BR7_OFF 0x05038
885#define OR7_OFF 0x0503C
887#define MRPTR_OFF 0x05084
888#define LSDMR_OFF 0x05094
889#define LSRT_OFF 0x050A4
890#define LCRR_OFF 0x050d4
893#define CS0_BNDS_OFF 0x02000
894#define CS1_BNDS_OFF 0x02008
895#define CS2_BNDS_OFF 0x02010
896#define CS3_BNDS_OFF 0x02018
897#define CS0_CONFIG_OFF 0x02080
898#define CS1_CONFIG_OFF 0x02084
899#define CS2_CONFIG_OFF 0x02088
900#define CS3_CONFIG_OFF 0x0208C
901#define TIMING_CFG_3_OFF 0x02100
902#define TIMING_CFG_0_OFF 0x02104
903#define TIMING_CFG_1_OFF 0x02108
904#define TIMING_CFG_2_OFF 0x0210C
905#define DDR_SDRAM_CFG_OFF 0x02110
906#define DDR_SDRAM_CFG_2_OFF 0x02114
907#define DDR_SDRAM_MODE_OFF 0x02118
908#define DDR_SDRAM_MODE_2_OFF 0x0211C
909#define DDR_SDRAM_MD_CNTL_OFF 0x02120
910#define DDR_SDRAM_INTERVAL_OFF 0x02124
911#define DDR_SDRAM_DATA_INIT_OFF 0x02128
912#define DDRCDR_OFF 0x0012C
913#define DDR_SDRAM_CLK_CNTL_OFF 0x02130
914#define DDR_SDRAM_INIT_ADDR_OFF 0x02148
915#define DDR_ERR_DISABLE_OFF 0x02E44
920#define DDR_SDRAM_CFG_MEM_EN (1 << (31- 0))
924#define DDR_SDRAM_CFG_2_D_FRC_SR (1 << (31- 0))
925#define DDR_SDRAM_CFG_2_D_SR_IE (1 << (31- 1))
926#define DDR_SDRAM_CFG_2_D_DLL_RST_DIS (1 << (31- 2))
927#define DDR_SDRAM_CFG_2_D_DQS_CFG_DIF (1 << (31- 5))
928#define DDR_SDRAM_CFG_2_D_INIT (1 << (31-27))
934#define RCWLR_LBIUCM_1_1 (0 << (31- 0))
935#define RCWLR_LBIUCM_2_1 (1 << (31- 0))
937#define RCWLR_DDRCM_1_1 (0 << (31- 1))
938#define RCWLR_DDRCM_2_1 (1 << (31- 1))
940#define RCWLR_SPMF(n) (((n)&0xf)<<(31- 7))
942#define RCWLR_COREPLL(n) (((n)&0xff)<<(31-15))
945#define RCWLR_CEVCOD_1_8 (2<<(31-25))
946#define RCWLR_CEVCOD_1_4 (1<<(31-25))
947#define RCWLR_CEVCOD_1_2 (0<<(31-25))
949#define RCWLR_CEPDF_2 (1<<(31-26))
951#define RCWLR_CEPMF(n) (((n)&0x1f)<<(31-31))
954#define RCWHR_PCI_AGENT (0 << (31- 0))
955#define RCWHR_PCI_HOST (1 << (31- 0))
957#define RCWHR_PCI_32 (0 << (31- 1))
958#define RCWHR_PCI_64 (1 << (31- 1))
960#define RCWHR_PCI1ARB_DIS (0 << (31- 2))
961#define RCWHR_PCI1ARB_EN (1 << (31- 2))
962#define RCWHR_PCI2ARB_DIS (0 << (31- 3))
963#define RCWHR_PCI2ARB_EN (1 << (31- 3))
965#define RCWHR_CORE_DIS (1 << (31- 4))
966#define RCWHR_CORE_EN (0 << (31- 4))
968#define RCWHR_BMS_LOW (0 << (31- 5))
969#define RCWHR_BMS_HIGH (1 << (31- 5))
971#define RCWHR_BOOTSEQ_NONE (0 <<(31- 7))
972#define RCWHR_BOOTSEQ_NORM (1 <<(31- 7))
973#define RCWHR_BOOTSEQ_EXTD (2 <<(31- 7))
974#define RCWHR_BOOTSEQ_RSRV (3 <<(31- 7))
976#define RCWHR_SW_DIS (0 << (31- 8))
977#define RCWHR_SW_EN (1 << (31- 8))
979#define RCWHR_ROMLOC_DDR (0 << (31-11))
980#define RCWHR_ROMLOC_PCI1 (1 << (31-11))
981#define RCWHR_ROMLOC_PCI2 (2 << (31-11))
982#define RCWHR_ROMLOC_RSV1 (3 << (31-11))
983#define RCWHR_ROMLOC_RSV2 (4 << (31-11))
984#define RCWHR_ROMLOC_LB08 (5 << (31-11))
985#define RCWHR_ROMLOC_LB16 (6 << (31-11))
986#define RCWHR_ROMLOC_LB32 (7 << (31-11))
988#define RCWHR_TSEC1M_RGMII (0 << (31-17))
989#define RCWHR_TSEC1M_RTBI (1 << (31-17))
990#define RCWHR_TSEC1M_GMII (2 << (31-17))
991#define RCWHR_TSEC1M_TBI (3 << (31-17))
993#define RCWHR_TSEC2M_RGMII (0 << (31-19))
994#define RCWHR_TSEC2M_RTBI (1 << (31-19))
995#define RCWHR_TSEC2M_GMII (2 << (31-19))
996#define RCWHR_TSEC2M_TBI (3 << (31-19))
998#define RCWHR_ENDIAN_BIG (0 << (31-28))
999#define RCWHR_ENDIAN_LIT (1 << (31-28))
1001#define RCWHR_LALE_NORM (0 << (31-29))
1002#define RCWHR_LALE_EARLY (1 << (31-29))
1004#define RCWHR_LDP_PAR (0 << (31-30))
1005#define RCWHR_LDP_SPC (1 << (31-30))
1010#define RCWHR_RLEXT_LGCY (0 << (31-13))
1011#define RCWHR_RLEXT_NAND (1 << (31-13))
1012#define RCWHR_RLEXT_RSV2 (2 << (31-13))
1013#define RCWHR_RLEXT_RSV3 (3 << (31-13))
#define _ISR_Set_level(_new_level)
Set current interrupt level.
Definition: isrlevel.h:159
rtems_termios_device_context * context
Definition: console-config.c:62
This header file defines the RTEMS Classic API.
Definition: intercom.c:87
Definition: 8xx_immap.h:210
Definition: mpc83xx.h:157
Definition: mpc83xx.h:184
Definition: mpc83xx.h:222
Definition: mpc83xx.h:209
Definition: mpc83xx.h:400
Definition: mpc83xx.h:383
Definition: mpc83xx.h:291
Definition: mpc83xx.h:198
Definition: mpc83xx.h:111
Definition: mpc83xx.h:274
Definition: mpc83xx.h:129
Definition: mpc83xx.h:317
Definition: mpc83xx.h:476
Definition: mpc83xx.h:528
Definition: mpc83xx.h:484
Definition: mpc83xx.h:191
Definition: mpc83xx.h:171
Definition: mpc83xx.h:783
Definition: mpc83xx.h:349
Definition: mpc83xx.h:603
Definition: mpc83xx.h:565