Definitions used in MMU setup.
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#define | MMU_DESC_AF ( 1 << 10 ) |
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#define | MMU_DESC_SH_INNER ( ( 1 << 9 ) | ( 1 << 8 ) ) |
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#define | MMU_DESC_WRITE_DISABLE ( 1 << 7 ) |
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#define | MMU_DESC_TYPE_TABLE ( 1 << 1 ) |
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#define | MMU_DESC_TYPE_PAGE ( 1 << 1 ) |
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#define | MMU_DESC_VALID ( 1 << 0 ) |
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#define | MMU_DESC_MAIR_ATTR(val) ( ( val & 0x3 ) << 2 ) |
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#define | MMU_DESC_PAGE_TABLE_MASK 0xFFFFFFFFF000LL |
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#define | MMU_PAGE_BITS 12 |
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#define | MMU_PAGE_SIZE ( 1 << MMU_PAGE_BITS ) |
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#define | MMU_BITS_PER_LEVEL 9 |
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#define | AARCH64_MMU_FLAGS_BASE ( MMU_DESC_VALID | MMU_DESC_SH_INNER | MMU_DESC_AF ) |
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#define | AARCH64_MMU_DATA_RO_CACHED ( AARCH64_MMU_FLAGS_BASE | MMU_DESC_MAIR_ATTR( 3 ) | MMU_DESC_WRITE_DISABLE ) |
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#define | AARCH64_MMU_CODE_CACHED AARCH64_MMU_DATA_RO_CACHED |
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#define | AARCH64_MMU_CODE_RW_CACHED AARCH64_MMU_DATA_RW_CACHED |
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#define | AARCH64_MMU_DATA_RO ( AARCH64_MMU_FLAGS_BASE | MMU_DESC_MAIR_ATTR( 2 ) | MMU_DESC_WRITE_DISABLE ) |
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#define | AARCH64_MMU_CODE AARCH64_MMU_DATA_RO |
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#define | AARCH64_MMU_CODE_RW AARCH64_MMU_DATA_RW |
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#define | AARCH64_MMU_DATA_RW_CACHED ( AARCH64_MMU_FLAGS_BASE | MMU_DESC_MAIR_ATTR( 3 ) ) |
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#define | AARCH64_MMU_DATA_RW ( AARCH64_MMU_FLAGS_BASE | MMU_DESC_MAIR_ATTR( 2 ) ) |
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#define | AARCH64_MMU_DEVICE ( AARCH64_MMU_FLAGS_BASE | MMU_DESC_MAIR_ATTR( 0 ) ) |
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Definitions used in MMU setup.