RTEMS 6.1-rc5
Loading...
Searching...
No Matches
memscrub-regs.h
Go to the documentation of this file.
1/* SPDX-License-Identifier: BSD-2-Clause */
2
11/*
12 * Copyright (C) 2021 embedded brains GmbH & Co. KG
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions
16 * are met:
17 * 1. Redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer.
19 * 2. Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in the
21 * documentation and/or other materials provided with the distribution.
22 *
23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
33 * POSSIBILITY OF SUCH DAMAGE.
34 */
35
36/*
37 * This file is part of the RTEMS quality process and was automatically
38 * generated. If you find something that needs to be fixed or
39 * worded better please post a report or patch to an RTEMS mailing list
40 * or raise a bug report:
41 *
42 * https://www.rtems.org/bugs.html
43 *
44 * For information on updating and regenerating please refer to the How-To
45 * section in the Software Requirements Engineering chapter of the
46 * RTEMS Software Engineering manual. The manual is provided as a part of
47 * a release. For development sources please refer to the online
48 * documentation at:
49 *
50 * https://docs.rtems.org
51 */
52
53/* Generated from spec:/dev/grlib/if/memscrub-header */
54
55#ifndef _GRLIB_MEMSCRUB_REGS_H
56#define _GRLIB_MEMSCRUB_REGS_H
57
58#include <stdint.h>
59
60#ifdef __cplusplus
61extern "C" {
62#endif
63
64/* Generated from spec:/dev/grlib/if/memscrub */
65
84#define MEMSCRUB_AHBS_CECNT_SHIFT 22
85#define MEMSCRUB_AHBS_CECNT_MASK 0xffc00000U
86#define MEMSCRUB_AHBS_CECNT_GET( _reg ) \
87 ( ( ( _reg ) & MEMSCRUB_AHBS_CECNT_MASK ) >> \
88 MEMSCRUB_AHBS_CECNT_SHIFT )
89#define MEMSCRUB_AHBS_CECNT_SET( _reg, _val ) \
90 ( ( ( _reg ) & ~MEMSCRUB_AHBS_CECNT_MASK ) | \
91 ( ( ( _val ) << MEMSCRUB_AHBS_CECNT_SHIFT ) & \
92 MEMSCRUB_AHBS_CECNT_MASK ) )
93#define MEMSCRUB_AHBS_CECNT( _val ) \
94 ( ( ( _val ) << MEMSCRUB_AHBS_CECNT_SHIFT ) & \
95 MEMSCRUB_AHBS_CECNT_MASK )
96
97#define MEMSCRUB_AHBS_UECNT_SHIFT 14
98#define MEMSCRUB_AHBS_UECNT_MASK 0x3fc000U
99#define MEMSCRUB_AHBS_UECNT_GET( _reg ) \
100 ( ( ( _reg ) & MEMSCRUB_AHBS_UECNT_MASK ) >> \
101 MEMSCRUB_AHBS_UECNT_SHIFT )
102#define MEMSCRUB_AHBS_UECNT_SET( _reg, _val ) \
103 ( ( ( _reg ) & ~MEMSCRUB_AHBS_UECNT_MASK ) | \
104 ( ( ( _val ) << MEMSCRUB_AHBS_UECNT_SHIFT ) & \
105 MEMSCRUB_AHBS_UECNT_MASK ) )
106#define MEMSCRUB_AHBS_UECNT( _val ) \
107 ( ( ( _val ) << MEMSCRUB_AHBS_UECNT_SHIFT ) & \
108 MEMSCRUB_AHBS_UECNT_MASK )
109
110#define MEMSCRUB_AHBS_DONE 0x2000U
111
112#define MEMSCRUB_AHBS_SEC 0x800U
113
114#define MEMSCRUB_AHBS_SBC 0x400U
115
116#define MEMSCRUB_AHBS_CE 0x200U
117
118#define MEMSCRUB_AHBS_NE 0x100U
119
120#define MEMSCRUB_AHBS_HWRITE 0x80U
121
122#define MEMSCRUB_AHBS_HMASTER_SHIFT 3
123#define MEMSCRUB_AHBS_HMASTER_MASK 0x78U
124#define MEMSCRUB_AHBS_HMASTER_GET( _reg ) \
125 ( ( ( _reg ) & MEMSCRUB_AHBS_HMASTER_MASK ) >> \
126 MEMSCRUB_AHBS_HMASTER_SHIFT )
127#define MEMSCRUB_AHBS_HMASTER_SET( _reg, _val ) \
128 ( ( ( _reg ) & ~MEMSCRUB_AHBS_HMASTER_MASK ) | \
129 ( ( ( _val ) << MEMSCRUB_AHBS_HMASTER_SHIFT ) & \
130 MEMSCRUB_AHBS_HMASTER_MASK ) )
131#define MEMSCRUB_AHBS_HMASTER( _val ) \
132 ( ( ( _val ) << MEMSCRUB_AHBS_HMASTER_SHIFT ) & \
133 MEMSCRUB_AHBS_HMASTER_MASK )
134
135#define MEMSCRUB_AHBS_HSIZE_SHIFT 0
136#define MEMSCRUB_AHBS_HSIZE_MASK 0x7U
137#define MEMSCRUB_AHBS_HSIZE_GET( _reg ) \
138 ( ( ( _reg ) & MEMSCRUB_AHBS_HSIZE_MASK ) >> \
139 MEMSCRUB_AHBS_HSIZE_SHIFT )
140#define MEMSCRUB_AHBS_HSIZE_SET( _reg, _val ) \
141 ( ( ( _reg ) & ~MEMSCRUB_AHBS_HSIZE_MASK ) | \
142 ( ( ( _val ) << MEMSCRUB_AHBS_HSIZE_SHIFT ) & \
143 MEMSCRUB_AHBS_HSIZE_MASK ) )
144#define MEMSCRUB_AHBS_HSIZE( _val ) \
145 ( ( ( _val ) << MEMSCRUB_AHBS_HSIZE_SHIFT ) & \
146 MEMSCRUB_AHBS_HSIZE_MASK )
147
159#define MEMSCRUB_AHBFAR_AHB_FAILING_ADDRESS_SHIFT 0
160#define MEMSCRUB_AHBFAR_AHB_FAILING_ADDRESS_MASK 0xffffffffU
161#define MEMSCRUB_AHBFAR_AHB_FAILING_ADDRESS_GET( _reg ) \
162 ( ( ( _reg ) & MEMSCRUB_AHBFAR_AHB_FAILING_ADDRESS_MASK ) >> \
163 MEMSCRUB_AHBFAR_AHB_FAILING_ADDRESS_SHIFT )
164#define MEMSCRUB_AHBFAR_AHB_FAILING_ADDRESS_SET( _reg, _val ) \
165 ( ( ( _reg ) & ~MEMSCRUB_AHBFAR_AHB_FAILING_ADDRESS_MASK ) | \
166 ( ( ( _val ) << MEMSCRUB_AHBFAR_AHB_FAILING_ADDRESS_SHIFT ) & \
167 MEMSCRUB_AHBFAR_AHB_FAILING_ADDRESS_MASK ) )
168#define MEMSCRUB_AHBFAR_AHB_FAILING_ADDRESS( _val ) \
169 ( ( ( _val ) << MEMSCRUB_AHBFAR_AHB_FAILING_ADDRESS_SHIFT ) & \
170 MEMSCRUB_AHBFAR_AHB_FAILING_ADDRESS_MASK )
171
183#define MEMSCRUB_AHBERC_CECNTT_SHIFT 22
184#define MEMSCRUB_AHBERC_CECNTT_MASK 0xffc00000U
185#define MEMSCRUB_AHBERC_CECNTT_GET( _reg ) \
186 ( ( ( _reg ) & MEMSCRUB_AHBERC_CECNTT_MASK ) >> \
187 MEMSCRUB_AHBERC_CECNTT_SHIFT )
188#define MEMSCRUB_AHBERC_CECNTT_SET( _reg, _val ) \
189 ( ( ( _reg ) & ~MEMSCRUB_AHBERC_CECNTT_MASK ) | \
190 ( ( ( _val ) << MEMSCRUB_AHBERC_CECNTT_SHIFT ) & \
191 MEMSCRUB_AHBERC_CECNTT_MASK ) )
192#define MEMSCRUB_AHBERC_CECNTT( _val ) \
193 ( ( ( _val ) << MEMSCRUB_AHBERC_CECNTT_SHIFT ) & \
194 MEMSCRUB_AHBERC_CECNTT_MASK )
195
196#define MEMSCRUB_AHBERC_UECNTT_SHIFT 14
197#define MEMSCRUB_AHBERC_UECNTT_MASK 0x3fc000U
198#define MEMSCRUB_AHBERC_UECNTT_GET( _reg ) \
199 ( ( ( _reg ) & MEMSCRUB_AHBERC_UECNTT_MASK ) >> \
200 MEMSCRUB_AHBERC_UECNTT_SHIFT )
201#define MEMSCRUB_AHBERC_UECNTT_SET( _reg, _val ) \
202 ( ( ( _reg ) & ~MEMSCRUB_AHBERC_UECNTT_MASK ) | \
203 ( ( ( _val ) << MEMSCRUB_AHBERC_UECNTT_SHIFT ) & \
204 MEMSCRUB_AHBERC_UECNTT_MASK ) )
205#define MEMSCRUB_AHBERC_UECNTT( _val ) \
206 ( ( ( _val ) << MEMSCRUB_AHBERC_UECNTT_SHIFT ) & \
207 MEMSCRUB_AHBERC_UECNTT_MASK )
208
209#define MEMSCRUB_AHBERC_CECTE 0x2U
210
211#define MEMSCRUB_AHBERC_UECTE 0x1U
212
223#define MEMSCRUB_STAT_RUNCOUNT_SHIFT 22
224#define MEMSCRUB_STAT_RUNCOUNT_MASK 0xffc00000U
225#define MEMSCRUB_STAT_RUNCOUNT_GET( _reg ) \
226 ( ( ( _reg ) & MEMSCRUB_STAT_RUNCOUNT_MASK ) >> \
227 MEMSCRUB_STAT_RUNCOUNT_SHIFT )
228#define MEMSCRUB_STAT_RUNCOUNT_SET( _reg, _val ) \
229 ( ( ( _reg ) & ~MEMSCRUB_STAT_RUNCOUNT_MASK ) | \
230 ( ( ( _val ) << MEMSCRUB_STAT_RUNCOUNT_SHIFT ) & \
231 MEMSCRUB_STAT_RUNCOUNT_MASK ) )
232#define MEMSCRUB_STAT_RUNCOUNT( _val ) \
233 ( ( ( _val ) << MEMSCRUB_STAT_RUNCOUNT_SHIFT ) & \
234 MEMSCRUB_STAT_RUNCOUNT_MASK )
235
236#define MEMSCRUB_STAT_BLKCOUNT_SHIFT 14
237#define MEMSCRUB_STAT_BLKCOUNT_MASK 0x3fc000U
238#define MEMSCRUB_STAT_BLKCOUNT_GET( _reg ) \
239 ( ( ( _reg ) & MEMSCRUB_STAT_BLKCOUNT_MASK ) >> \
240 MEMSCRUB_STAT_BLKCOUNT_SHIFT )
241#define MEMSCRUB_STAT_BLKCOUNT_SET( _reg, _val ) \
242 ( ( ( _reg ) & ~MEMSCRUB_STAT_BLKCOUNT_MASK ) | \
243 ( ( ( _val ) << MEMSCRUB_STAT_BLKCOUNT_SHIFT ) & \
244 MEMSCRUB_STAT_BLKCOUNT_MASK ) )
245#define MEMSCRUB_STAT_BLKCOUNT( _val ) \
246 ( ( ( _val ) << MEMSCRUB_STAT_BLKCOUNT_SHIFT ) & \
247 MEMSCRUB_STAT_BLKCOUNT_MASK )
248
249#define MEMSCRUB_STAT_DONE 0x2000U
250
251#define MEMSCRUB_STAT_BURSTLEN_SHIFT 1
252#define MEMSCRUB_STAT_BURSTLEN_MASK 0x1eU
253#define MEMSCRUB_STAT_BURSTLEN_GET( _reg ) \
254 ( ( ( _reg ) & MEMSCRUB_STAT_BURSTLEN_MASK ) >> \
255 MEMSCRUB_STAT_BURSTLEN_SHIFT )
256#define MEMSCRUB_STAT_BURSTLEN_SET( _reg, _val ) \
257 ( ( ( _reg ) & ~MEMSCRUB_STAT_BURSTLEN_MASK ) | \
258 ( ( ( _val ) << MEMSCRUB_STAT_BURSTLEN_SHIFT ) & \
259 MEMSCRUB_STAT_BURSTLEN_MASK ) )
260#define MEMSCRUB_STAT_BURSTLEN( _val ) \
261 ( ( ( _val ) << MEMSCRUB_STAT_BURSTLEN_SHIFT ) & \
262 MEMSCRUB_STAT_BURSTLEN_MASK )
263
264#define MEMSCRUB_STAT_ACTIVE 0x1U
265
276#define MEMSCRUB_CONFIG_DELAY_SHIFT 8
277#define MEMSCRUB_CONFIG_DELAY_MASK 0xff00U
278#define MEMSCRUB_CONFIG_DELAY_GET( _reg ) \
279 ( ( ( _reg ) & MEMSCRUB_CONFIG_DELAY_MASK ) >> \
280 MEMSCRUB_CONFIG_DELAY_SHIFT )
281#define MEMSCRUB_CONFIG_DELAY_SET( _reg, _val ) \
282 ( ( ( _reg ) & ~MEMSCRUB_CONFIG_DELAY_MASK ) | \
283 ( ( ( _val ) << MEMSCRUB_CONFIG_DELAY_SHIFT ) & \
284 MEMSCRUB_CONFIG_DELAY_MASK ) )
285#define MEMSCRUB_CONFIG_DELAY( _val ) \
286 ( ( ( _val ) << MEMSCRUB_CONFIG_DELAY_SHIFT ) & \
287 MEMSCRUB_CONFIG_DELAY_MASK )
288
289#define MEMSCRUB_CONFIG_IRQD 0x80U
290
291#define MEMSCRUB_CONFIG_SERA 0x20U
292
293#define MEMSCRUB_CONFIG_LOOP 0x10U
294
295#define MEMSCRUB_CONFIG_MODE_SHIFT 2
296#define MEMSCRUB_CONFIG_MODE_MASK 0xcU
297#define MEMSCRUB_CONFIG_MODE_GET( _reg ) \
298 ( ( ( _reg ) & MEMSCRUB_CONFIG_MODE_MASK ) >> \
299 MEMSCRUB_CONFIG_MODE_SHIFT )
300#define MEMSCRUB_CONFIG_MODE_SET( _reg, _val ) \
301 ( ( ( _reg ) & ~MEMSCRUB_CONFIG_MODE_MASK ) | \
302 ( ( ( _val ) << MEMSCRUB_CONFIG_MODE_SHIFT ) & \
303 MEMSCRUB_CONFIG_MODE_MASK ) )
304#define MEMSCRUB_CONFIG_MODE( _val ) \
305 ( ( ( _val ) << MEMSCRUB_CONFIG_MODE_SHIFT ) & \
306 MEMSCRUB_CONFIG_MODE_MASK )
307
308#define MEMSCRUB_CONFIG_ES 0x2U
309
310#define MEMSCRUB_CONFIG_SCEN 0x1U
311
322#define MEMSCRUB_RANGEL_RLADDR_SHIFT 0
323#define MEMSCRUB_RANGEL_RLADDR_MASK 0xffffffffU
324#define MEMSCRUB_RANGEL_RLADDR_GET( _reg ) \
325 ( ( ( _reg ) & MEMSCRUB_RANGEL_RLADDR_MASK ) >> \
326 MEMSCRUB_RANGEL_RLADDR_SHIFT )
327#define MEMSCRUB_RANGEL_RLADDR_SET( _reg, _val ) \
328 ( ( ( _reg ) & ~MEMSCRUB_RANGEL_RLADDR_MASK ) | \
329 ( ( ( _val ) << MEMSCRUB_RANGEL_RLADDR_SHIFT ) & \
330 MEMSCRUB_RANGEL_RLADDR_MASK ) )
331#define MEMSCRUB_RANGEL_RLADDR( _val ) \
332 ( ( ( _val ) << MEMSCRUB_RANGEL_RLADDR_SHIFT ) & \
333 MEMSCRUB_RANGEL_RLADDR_MASK )
334
346#define MEMSCRUB_RANGEH_RHADDR_SHIFT 0
347#define MEMSCRUB_RANGEH_RHADDR_MASK 0xffffffffU
348#define MEMSCRUB_RANGEH_RHADDR_GET( _reg ) \
349 ( ( ( _reg ) & MEMSCRUB_RANGEH_RHADDR_MASK ) >> \
350 MEMSCRUB_RANGEH_RHADDR_SHIFT )
351#define MEMSCRUB_RANGEH_RHADDR_SET( _reg, _val ) \
352 ( ( ( _reg ) & ~MEMSCRUB_RANGEH_RHADDR_MASK ) | \
353 ( ( ( _val ) << MEMSCRUB_RANGEH_RHADDR_SHIFT ) & \
354 MEMSCRUB_RANGEH_RHADDR_MASK ) )
355#define MEMSCRUB_RANGEH_RHADDR( _val ) \
356 ( ( ( _val ) << MEMSCRUB_RANGEH_RHADDR_SHIFT ) & \
357 MEMSCRUB_RANGEH_RHADDR_MASK )
358
369#define MEMSCRUB_POS_POSITION_SHIFT 0
370#define MEMSCRUB_POS_POSITION_MASK 0xffffffffU
371#define MEMSCRUB_POS_POSITION_GET( _reg ) \
372 ( ( ( _reg ) & MEMSCRUB_POS_POSITION_MASK ) >> \
373 MEMSCRUB_POS_POSITION_SHIFT )
374#define MEMSCRUB_POS_POSITION_SET( _reg, _val ) \
375 ( ( ( _reg ) & ~MEMSCRUB_POS_POSITION_MASK ) | \
376 ( ( ( _val ) << MEMSCRUB_POS_POSITION_SHIFT ) & \
377 MEMSCRUB_POS_POSITION_MASK ) )
378#define MEMSCRUB_POS_POSITION( _val ) \
379 ( ( ( _val ) << MEMSCRUB_POS_POSITION_SHIFT ) & \
380 MEMSCRUB_POS_POSITION_MASK )
381
392#define MEMSCRUB_ETHRES_RECT_SHIFT 22
393#define MEMSCRUB_ETHRES_RECT_MASK 0xffc00000U
394#define MEMSCRUB_ETHRES_RECT_GET( _reg ) \
395 ( ( ( _reg ) & MEMSCRUB_ETHRES_RECT_MASK ) >> \
396 MEMSCRUB_ETHRES_RECT_SHIFT )
397#define MEMSCRUB_ETHRES_RECT_SET( _reg, _val ) \
398 ( ( ( _reg ) & ~MEMSCRUB_ETHRES_RECT_MASK ) | \
399 ( ( ( _val ) << MEMSCRUB_ETHRES_RECT_SHIFT ) & \
400 MEMSCRUB_ETHRES_RECT_MASK ) )
401#define MEMSCRUB_ETHRES_RECT( _val ) \
402 ( ( ( _val ) << MEMSCRUB_ETHRES_RECT_SHIFT ) & \
403 MEMSCRUB_ETHRES_RECT_MASK )
404
405#define MEMSCRUB_ETHRES_BECT_SHIFT 14
406#define MEMSCRUB_ETHRES_BECT_MASK 0x3fc000U
407#define MEMSCRUB_ETHRES_BECT_GET( _reg ) \
408 ( ( ( _reg ) & MEMSCRUB_ETHRES_BECT_MASK ) >> \
409 MEMSCRUB_ETHRES_BECT_SHIFT )
410#define MEMSCRUB_ETHRES_BECT_SET( _reg, _val ) \
411 ( ( ( _reg ) & ~MEMSCRUB_ETHRES_BECT_MASK ) | \
412 ( ( ( _val ) << MEMSCRUB_ETHRES_BECT_SHIFT ) & \
413 MEMSCRUB_ETHRES_BECT_MASK ) )
414#define MEMSCRUB_ETHRES_BECT( _val ) \
415 ( ( ( _val ) << MEMSCRUB_ETHRES_BECT_SHIFT ) & \
416 MEMSCRUB_ETHRES_BECT_MASK )
417
418#define MEMSCRUB_ETHRES_RECTE 0x2U
419
420#define MEMSCRUB_ETHRES_BECTE 0x1U
421
432#define MEMSCRUB_INIT_DATA_SHIFT 0
433#define MEMSCRUB_INIT_DATA_MASK 0xffffffffU
434#define MEMSCRUB_INIT_DATA_GET( _reg ) \
435 ( ( ( _reg ) & MEMSCRUB_INIT_DATA_MASK ) >> \
436 MEMSCRUB_INIT_DATA_SHIFT )
437#define MEMSCRUB_INIT_DATA_SET( _reg, _val ) \
438 ( ( ( _reg ) & ~MEMSCRUB_INIT_DATA_MASK ) | \
439 ( ( ( _val ) << MEMSCRUB_INIT_DATA_SHIFT ) & \
440 MEMSCRUB_INIT_DATA_MASK ) )
441#define MEMSCRUB_INIT_DATA( _val ) \
442 ( ( ( _val ) << MEMSCRUB_INIT_DATA_SHIFT ) & \
443 MEMSCRUB_INIT_DATA_MASK )
444
456#define MEMSCRUB_RANGEL2_RLADDR_SHIFT 0
457#define MEMSCRUB_RANGEL2_RLADDR_MASK 0xffffffffU
458#define MEMSCRUB_RANGEL2_RLADDR_GET( _reg ) \
459 ( ( ( _reg ) & MEMSCRUB_RANGEL2_RLADDR_MASK ) >> \
460 MEMSCRUB_RANGEL2_RLADDR_SHIFT )
461#define MEMSCRUB_RANGEL2_RLADDR_SET( _reg, _val ) \
462 ( ( ( _reg ) & ~MEMSCRUB_RANGEL2_RLADDR_MASK ) | \
463 ( ( ( _val ) << MEMSCRUB_RANGEL2_RLADDR_SHIFT ) & \
464 MEMSCRUB_RANGEL2_RLADDR_MASK ) )
465#define MEMSCRUB_RANGEL2_RLADDR( _val ) \
466 ( ( ( _val ) << MEMSCRUB_RANGEL2_RLADDR_SHIFT ) & \
467 MEMSCRUB_RANGEL2_RLADDR_MASK )
468
480#define MEMSCRUB_RANGEH2_RHADDR_SHIFT 0
481#define MEMSCRUB_RANGEH2_RHADDR_MASK 0xffffffffU
482#define MEMSCRUB_RANGEH2_RHADDR_GET( _reg ) \
483 ( ( ( _reg ) & MEMSCRUB_RANGEH2_RHADDR_MASK ) >> \
484 MEMSCRUB_RANGEH2_RHADDR_SHIFT )
485#define MEMSCRUB_RANGEH2_RHADDR_SET( _reg, _val ) \
486 ( ( ( _reg ) & ~MEMSCRUB_RANGEH2_RHADDR_MASK ) | \
487 ( ( ( _val ) << MEMSCRUB_RANGEH2_RHADDR_SHIFT ) & \
488 MEMSCRUB_RANGEH2_RHADDR_MASK ) )
489#define MEMSCRUB_RANGEH2_RHADDR( _val ) \
490 ( ( ( _val ) << MEMSCRUB_RANGEH2_RHADDR_SHIFT ) & \
491 MEMSCRUB_RANGEH2_RHADDR_MASK )
492
498typedef struct memscrub {
502 uint32_t ahbs;
503
507 uint32_t ahbfar;
508
512 uint32_t ahberc;
513
514 uint32_t reserved_c_10;
515
519 uint32_t stat;
520
524 uint32_t config;
525
529 uint32_t rangel;
530
534 uint32_t rangeh;
535
539 uint32_t pos;
540
544 uint32_t ethres;
545
549 uint32_t init;
550
554 uint32_t rangel2;
555
559 uint32_t rangeh2;
560} memscrub;
561
564#ifdef __cplusplus
565}
566#endif
567
568#endif /* _GRLIB_MEMSCRUB_REGS_H */
memscrub
This structure defines the MEMSCRUB register block memory map.
Definition: memscrub-regs.h:498
memscrub::ahbs
uint32_t ahbs
See AHB Status register (AHBS).
Definition: memscrub-regs.h:502
memscrub::ethres
uint32_t ethres
See Error threshold register (ETHRES).
Definition: memscrub-regs.h:544
memscrub::pos
uint32_t pos
See Position register (POS).
Definition: memscrub-regs.h:539
memscrub::rangel2
uint32_t rangel2
See Second range low address register (RANGEL2).
Definition: memscrub-regs.h:554
memscrub::rangeh2
uint32_t rangeh2
See Second range high address register (RANGEH2).
Definition: memscrub-regs.h:559
memscrub::config
uint32_t config
See Configuration register (CONFIG).
Definition: memscrub-regs.h:524
memscrub::ahbfar
uint32_t ahbfar
See AHB Failing Address Register (AHBFAR).
Definition: memscrub-regs.h:507
memscrub::ahberc
uint32_t ahberc
See AHB Error configuration register (AHBERC).
Definition: memscrub-regs.h:512
memscrub::rangel
uint32_t rangel
See Range low address register (RANGEL).
Definition: memscrub-regs.h:529
memscrub::init
uint32_t init
See Initialisation data register (INIT).
Definition: memscrub-regs.h:549
memscrub::stat
uint32_t stat
See Status register (STAT).
Definition: memscrub-regs.h:519
memscrub::rangeh
uint32_t rangeh
See Range high address register (RANGEH).
Definition: memscrub-regs.h:534
Generated by doxygen 1.9.6