RTEMS 6.1-rc5
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Adapted from virtex BSP
PORT: N/A ELECTRICAL: N/A BAUD: N/A BITS PER CHARACTER: N/A PARITY: N/A STOP BITS: N/A
clock rate: 350 MHz ROM: N/A RAM: 128MByte DRAM ```
Virtex only supports single processor operations.
This board support package is written for a naked Virtex 4/PPC FPGA system. The rough features of such a board are described above. The BSP itself makes no assumptions on what is loaded in the FPGA, other than that the CPU has access to some memory, either on-board or external, from which code can be run.
This BSP has been constructed so that an application of both firmware and software can be layered on top of it by supplying implementations for the various 'weak' symbols. These symbols are prefaced with the term 'app_'. Applications can thus be built outside of the RTEMS directory tree by linking with the appropriate libraries.
The linkcmds file describes the memory layout. Included in this definition is a section of memory named MsgArea. Output sent to stdout is recorded in this area and can be dumped using the JTAG interface, for example.
For adapting this BSP to other boards, the following files should be modified: