RTEMS 6.1-rc5
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mcan_config.h
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1/* ---------------------------------------------------------------------------- */
2/* Atmel Microcontroller Software Support */
3/* SAM Software Package License */
4/* ---------------------------------------------------------------------------- */
5/* Copyright (c) 2015, Atmel Corporation */
6/* */
7/* All rights reserved. */
8/* */
9/* Redistribution and use in source and binary forms, with or without */
10/* modification, are permitted provided that the following condition is met: */
11/* */
12/* - Redistributions of source code must retain the above copyright notice, */
13/* this list of conditions and the disclaimer below. */
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15/* Atmel's name may not be used to endorse or promote products derived from */
16/* this software without specific prior written permission. */
17/* */
18/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
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28/* ---------------------------------------------------------------------------- */
29
44#ifndef _MCAN_CONFIG_
45#define _MCAN_CONFIG_
46
47/*------------------------------------------------------------------------------
48 * Headers
49 *------------------------------------------------------------------------------*/
50
51
52/*------------------------------------------------------------------------------
53 * Global functions
54 *------------------------------------------------------------------------------*/
55
56#ifdef __cplusplus
57extern "C" {
58#endif
59
60/* Programmable Clock Source for Baud Rate is Common To Both MCAN Controllers */
61#define MCAN_PROG_CLK_PRESCALER 1 /* /1 to /256 */
62// select one of the following for the programmable clock source
63//#define MCAN_PROG_CLK_SELECT PMC_PCK_CSS_SLOW_CLK
64//#define MCAN_PROG_CLK_SELECT PMC_PCK_CSS_MAIN_CLK
65//#define MCAN_PROG_CLK_SELECT PMC_PCK_CSS_PLLA_CLK
66//#define MCAN_PROG_CLK_SELECT PMC_PCK_CSS_UPLL_CLK
67#define MCAN_PROG_CLK_SELECT PMC_PCK_CSS_MCK
68#define MCAN_PROG_CLK_FREQ_HZ \
69 ((float) 150000000 / (float) MCAN_PROG_CLK_PRESCALER)
70
71#define MCAN0_BIT_RATE_BPS 500000
72#define MCAN0_PROP_SEG 2
73#define MCAN0_PHASE_SEG1 11
74#define MCAN0_PHASE_SEG2 11
75#define MCAN0_SYNC_JUMP 4
76
77#define MCAN0_FAST_BIT_RATE_BPS 2000000
78#define MCAN0_FAST_PROP_SEG 2
79#define MCAN0_FAST_PHASE_SEG1 4
80#define MCAN0_FAST_PHASE_SEG2 4
81#define MCAN0_FAST_SYNC_JUMP 2
82
83#define MCAN0_NMBR_STD_FLTS 8 /* 128 max filters */
84#define MCAN0_NMBR_EXT_FLTS 8 /* 64 max filters */
85#define MCAN0_NMBR_RX_FIFO0_ELMTS 0 /* # of elements, 64 elements max */
86#define MCAN0_NMBR_RX_FIFO1_ELMTS 0 /* # of elements, 64 elements max */
87#define MCAN0_NMBR_RX_DED_BUF_ELMTS 16 /* # of elements, 64 elements max */
88#define MCAN0_NMBR_TX_EVT_FIFO_ELMTS 0 /* # of elements, 32 elements max */
89#define MCAN0_NMBR_TX_DED_BUF_ELMTS 4 /* # of elements, 32 elements max */
90#define MCAN0_NMBR_TX_FIFO_Q_ELMTS 0 /* # of elements, 32 elements max */
91#define MCAN0_RX_FIFO0_ELMT_SZ 8 /* 8, 12, 16, 20, 24, 32, 48, 64 bytes */
92#define MCAN0_RX_FIFO1_ELMT_SZ 8 /* 8, 12, 16, 20, 24, 32, 48, 64 bytes */
93#define MCAN0_RX_BUF_ELMT_SZ 8 /* 8, 12, 16, 20, 24, 32, 48, 64 bytes */
94#define MCAN0_TX_BUF_ELMT_SZ 8 /* 8, 12, 16, 20, 24, 32, 48, 64 bytes */
95
96#define MCAN1_BIT_RATE_BPS 500000
97#define MCAN1_PROP_SEG 2
98#define MCAN1_PHASE_SEG1 11
99#define MCAN1_PHASE_SEG2 11
100#define MCAN1_SYNC_JUMP 4
101
102#define MCAN1_FAST_BIT_RATE_BPS 2000000
103#define MCAN1_FAST_PROP_SEG 2
104#define MCAN1_FAST_PHASE_SEG1 4
105#define MCAN1_FAST_PHASE_SEG2 4
106#define MCAN1_FAST_SYNC_JUMP 2
107
108#define MCAN1_NMBR_STD_FLTS 8 /* 128 max filters */
109#define MCAN1_NMBR_EXT_FLTS 8 /* 64 max filters */
110#define MCAN1_NMBR_RX_FIFO0_ELMTS 12 /* # of elements, 64 elements max */
111#define MCAN1_NMBR_RX_FIFO1_ELMTS 0 /* # of elements, 64 elements max */
112#define MCAN1_NMBR_RX_DED_BUF_ELMTS 4 /* # of elements, 64 elements max */
113#define MCAN1_NMBR_TX_EVT_FIFO_ELMTS 0 /* # of elements, 32 elements max */
114#define MCAN1_NMBR_TX_DED_BUF_ELMTS 4 /* # of elements, 32 elements max */
115#define MCAN1_NMBR_TX_FIFO_Q_ELMTS 4 /* # of elements, 32 elements max */
116#define MCAN1_RX_FIFO0_ELMT_SZ 8 /* 8, 12, 16, 20, 24, 32, 48, 64 bytes */
117#define MCAN1_RX_FIFO1_ELMT_SZ 8 /* 8, 12, 16, 20, 24, 32, 48, 64 bytes */
118#define MCAN1_RX_BUF_ELMT_SZ 64 /* 8, 12, 16, 20, 24, 32, 48, 64 bytes */
119#define MCAN1_TX_BUF_ELMT_SZ 32 /* 8, 12, 16, 20, 24, 32, 48, 64 bytes */
120
121#ifdef __cplusplus
122}
123#endif
124
125#endif /* #ifndef _MCAN_CONFIG_ */
126
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