RTEMS 6.1-rc5
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imx_gpcreg.h
1/* SPDX-License-Identifier: BSD-2-Clause */
2
3/*
4 * Copyright (c) 2017 embedded brains GmbH & Co. KG
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
26 */
27
28#ifndef IMX_GPCREG_H
29#define IMX_GPCREG_H
30
31#include <bsp/utility.h>
32
33typedef struct {
34 uint32_t lpcr_a7_bsc;
35 uint32_t lpcr_a7_ad;
36 uint32_t lpcr_m4;
37 uint32_t reserved_0c[2];
38 uint32_t slpcr;
39 uint32_t reserved_18[2];
40 uint32_t mlpcr;
41 uint32_t pgc_ack_sel_a7;
42 uint32_t pgc_ack_sel_m4;
43 uint32_t misc;
44 uint32_t imr1_core0_a7;
45 uint32_t imr2_core0_a7;
46 uint32_t imr3_core0_a7;
47 uint32_t imr4_core0_a7;
48 uint32_t imr1_core1_a7;
49 uint32_t imr2_core1_a7;
50 uint32_t imr3_core1_a7;
51 uint32_t imr4_core1_a7;
52 uint32_t imr1_m4;
53 uint32_t imr2_m4;
54 uint32_t imr3_m4;
55 uint32_t imr4_m4;
56 uint32_t reserved_60[4];
57 uint32_t isr1_a7;
58 uint32_t isr2_a7;
59 uint32_t isr3_a7;
60 uint32_t isr4_a7;
61 uint32_t isr1_m4;
62 uint32_t isr2_m4;
63 uint32_t isr3_m4;
64 uint32_t isr4_m4;
65 uint32_t reserved_90[8];
66 uint32_t slt0_cfg;
67 uint32_t slt1_cfg;
68 uint32_t slt2_cfg;
69 uint32_t slt3_cfg;
70 uint32_t slt4_cfg;
71 uint32_t slt5_cfg;
72 uint32_t slt6_cfg;
73 uint32_t slt7_cfg;
74 uint32_t slt8_cfg;
75 uint32_t slt9_cfg;
76 uint32_t reserved_d8[5];
77 uint32_t pgc_cpu_mapping;
78#define IMX_GPC_CPU_PGC_SCU_A7 BSP_BIT32(2)
79#define IMX_GPC_CPU_PGC_CORE1_A7 BSP_BIT32(1)
80#define IMX_GPC_CPU_PGC_CORE0_A7 BSP_BIT32(0)
81#define IMX_GPC_PU_PGC_USB_HSIC_PHY BSP_BIT32(4)
82#define IMX_GPC_PU_PGC_USB_OTG2_PHY BSP_BIT32(3)
83#define IMX_GPC_PU_PGC_USB_OTG1_PHY BSP_BIT32(2)
84#define IMX_GPC_PU_PGC_PCIE_PHY BSP_BIT32(1)
85#define IMX_GPC_PU_PGC_MIPI_PHY BSP_BIT32(0)
86 uint32_t cpu_pgc_sw_pup_req;
87 uint32_t reserved_f4;
88 uint32_t pu_pgc_sw_pup_req;
89 uint32_t cpu_pgc_sw_pdn_req;
90 uint32_t reserved_100;
91 uint32_t pu_pgc_sw_pdn_req;
92 uint32_t reserved_108[10];
93 uint32_t cpu_pgc_pup_status1;
94 uint32_t a7_mix_pgc_pup_status0;
95 uint32_t a7_mix_pgc_pup_status1;
96 uint32_t a7_mix_pgc_pup_status2;
97 uint32_t m4_mix_pgc_pup_status0;
98 uint32_t m4_mix_pgc_pup_status1;
99 uint32_t m4_mix_pgc_pup_status2;
100 uint32_t a7_pu_pgc_pup_status0;
101 uint32_t a7_pu_pgc_pup_status1;
102 uint32_t a7_pu_pgc_pup_status2;
103 uint32_t m4_pu_pgc_pup_status0;
104 uint32_t m4_pu_pgc_pup_status1;
105 uint32_t m4_pu_pgc_pup_status2;
106 uint32_t reserved_164[3];
107 uint32_t cpu_pgc_pdn_status1;
108 uint32_t reserved_174[6];
109 uint32_t a7_pu_pgc_pdn_status0;
110 uint32_t a7_pu_pgc_pdn_status1;
111 uint32_t a7_pu_pgc_pdn_status2;
112 uint32_t m4_pu_pgc_pdn_status0;
113 uint32_t m4_pu_pgc_pdn_status1;
114 uint32_t m4_pu_pgc_pdn_status2;
115 uint32_t reserved_1a4[3];
116 uint32_t a7_mix_pdn_flg;
117 uint32_t a7_pu_pdn_flg;
118 uint32_t m4_mix_pdn_flg;
119 uint32_t m4_pu_pdn_flg;
120#define IMX_GPC_PGC_CTRL_MEMPWR_TCD1_TDR_TRM(val) BSP_FLD32(val, 24, 29)
121#define IMX_GPC_PGC_CTRL_MEMPWR_TCD1_TDR_TRM_GET(reg) BSP_FLD32GET(reg, 24, 29)
122#define IMX_GPC_PGC_CTRL_MEMPWR_TCD1_TDR_TRM_SET(reg, val) BSP_FLD32SET(reg, val, 24, 29)
123#define IMX_GPC_PGC_CTRL_L2RETN_TCD1_TDR(val) BSP_FLD32(val, 16, 21)
124#define IMX_GPC_PGC_CTRL_L2RETN_TCD1_TDR_GET(reg) BSP_FLD32GET(reg, 16, 21)
125#define IMX_GPC_PGC_CTRL_L2RETN_TCD1_TDR_SET(reg, val) BSP_FLD32SET(reg, val, 16, 21)
126#define IMX_GPC_PGC_CTRL_DFTRAM_TCD1(val) BSP_FLD32(val, 8, 13)
127#define IMX_GPC_PGC_CTRL_DFTRAM_TCD1_GET(reg) BSP_FLD32GET(reg, 8, 13)
128#define IMX_GPC_PGC_CTRL_DFTRAM_TCD1_SET(reg, val) BSP_FLD32SET(reg, val, 8, 13)
129#define IMX_GPC_PGC_CTRL_L2RSTDIS(val) BSP_FLD32(val, 1, 6)
130#define IMX_GPC_PGC_CTRL_L2RSTDIS_GET(reg) BSP_FLD32GET(reg, 1, 6)
131#define IMX_GPC_PGC_CTRL_L2RSTDIS_SET(reg, val) BSP_FLD32SET(reg, val, 1, 6)
132#define IMX_GPC_PGC_CTRL_PCR BSP_BIT32(0)
133 uint32_t reserved_1c0[400];
134 uint32_t pgc_a7core0_ctrl;
135 uint32_t pgc_a7core0_pupscr;
136 uint32_t pgc_a7core0_pdnscr;
137 uint32_t pgc_a7core0_sr;
138 uint32_t reserved_810[12];
139 uint32_t pgc_a7core1_ctrl;
140 uint32_t pgc_a7core1_pupscr;
141 uint32_t pgc_a7core1_pdnscr;
142 uint32_t pgc_a7core1_sr;
143 uint32_t reserved_850[12];
144 uint32_t pgc_a7scu_ctrl;
145 uint32_t pgc_a7scu_pupscr;
146 uint32_t pgc_a7scu_pdnscr;
147 uint32_t pgc_a7scu_sr;
148 uint32_t pgc_scu_auxsw;
149 uint32_t reserved_894[11];
150 uint32_t pgc_mix_ctrl;
151 uint32_t pgc_mix_pupscr;
152 uint32_t pgc_mix_pdnscr;
153 uint32_t pgc_mix_sr;
154 uint32_t reserved_8d0[12];
155 uint32_t pgc_mipi_ctrl;
156 uint32_t pgc_mipi_pupscr;
157 uint32_t pgc_mipi_pdnscr;
158 uint32_t pgc_mipi_sr;
159 uint32_t reserved_910[12];
160 uint32_t pgc_pcie_ctrl;
161 uint32_t pgc_pcie_pupscr;
162 uint32_t pgc_pcie_pdnscr;
163 uint32_t pgc_pcie_sr;
164 uint32_t reserved_950[176];
165 uint32_t pgc_mipi_auxsw;
166 uint32_t reserved_c14[15];
167 uint32_t pgc_pcie_auxsw;
168 uint32_t reserved_c54[43];
169 uint32_t pgc_hsic_ctrl;
170 uint32_t pgc_hsic_pupscr;
171 uint32_t pgc_hsic_pdnscr;
172 uint32_t pgc_hsic_sr;
173} imx_gpc;
174
175#endif /* IMX_GPCREG_H */
utility.h
This header file provides utility macros for BSPs.
imx_gpc
Definition: imx_gpcreg.h:33
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