Intel Architecture local and I/O APIC definitions.
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#define | APIC_BCAST_ID 0xFF |
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#define | APIC_VERSION(x) ((x) & 0xFF) |
| APIC version register.
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#define | APIC_MAXREDIR(x) (((x) >> 16) & 0xFF) |
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#define | APIC_ID(x) ((x) >> 24) |
| APIC id register.
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#define | APIC_VER_NEW 0x10 |
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#define | IOAPIC_REGSEL 0 |
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#define | IOAPIC_RW 0x10 |
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#define | IOAPIC_ID 0 |
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#define | IOAPIC_VER 1 |
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#define | IOAPIC_REDIR 0x10 |
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#define | LAPIC_ID 0x20 |
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#define | LAPIC_VER 0x30 |
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#define | LAPIC_TPR 0x80 |
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#define | LAPIC_APR 0x90 |
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#define | LAPIC_PPR 0xA0 |
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#define | LAPIC_EOI 0xB0 |
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#define | LAPIC_LDR 0xD0 |
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#define | LAPIC_DFR 0xE0 |
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#define | LAPIC_SPIV 0xF0 |
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#define | LAPIC_SPIV_ENABLE_APIC 0x100 |
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#define | LAPIC_ISR 0x100 |
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#define | LAPIC_TMR 0x180 |
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#define | LAPIC_IRR 0x200 |
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#define | LAPIC_ESR 0x280 |
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#define | LAPIC_ICR 0x300 |
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#define | LAPIC_ICR_DS_SELF 0x40000 |
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#define | LAPIC_ICR_DS_ALLINC 0x80000 |
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#define | LAPIC_ICR_DS_ALLEX 0xC0000 |
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#define | LAPIC_ICR_TM_LEVEL 0x8000 |
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#define | LAPIC_ICR_LEVELASSERT 0x4000 |
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#define | LAPIC_ICR_STATUS_PEND 0x1000 |
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#define | LAPIC_ICR_DM_LOGICAL 0x800 |
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#define | LAPIC_ICR_DM_LOWPRI 0x100 |
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#define | LAPIC_ICR_DM_SMI 0x200 |
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#define | LAPIC_ICR_DM_NMI 0x400 |
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#define | LAPIC_ICR_DM_INIT 0x500 |
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#define | LAPIC_ICR_DM_SIPI 0x600 |
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#define | LAPIC_LVTT 0x320 |
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#define | LAPIC_LVTPC 0x340 |
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#define | LAPIC_LVT0 0x350 |
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#define | LAPIC_LVT1 0x360 |
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#define | LAPIC_LVTE 0x370 |
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#define | LAPIC_TICR 0x380 |
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#define | LAPIC_TCCR 0x390 |
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#define | LAPIC_TDCR 0x3E0 |
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Intel Architecture local and I/O APIC definitions.