RTEMS 6.1-rc5
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This header file defines the GRIOMMU register block interface. More...
#include <stdint.h>
Go to the source code of this file.
Data Structures | |
struct | griommu |
This structure defines the GRIOMMU register block memory map. More... | |
Macros | |
#define | GRIOMMU_CAP0_A 0x80000000U |
#define | GRIOMMU_CAP0_AC 0x40000000U |
#define | GRIOMMU_CAP0_CA 0x20000000U |
#define | GRIOMMU_CAP0_CP 0x10000000U |
#define | GRIOMMU_CAP0_NARB_SHIFT 20 |
#define | GRIOMMU_CAP0_NARB_MASK 0xf00000U |
#define | GRIOMMU_CAP0_NARB_GET(_reg) |
#define | GRIOMMU_CAP0_NARB_SET(_reg, _val) |
#define | GRIOMMU_CAP0_NARB(_val) |
#define | GRIOMMU_CAP0_CS 0x80000U |
#define | GRIOMMU_CAP0_FT_SHIFT 17 |
#define | GRIOMMU_CAP0_FT_MASK 0x60000U |
#define | GRIOMMU_CAP0_FT_GET(_reg) |
#define | GRIOMMU_CAP0_FT_SET(_reg, _val) |
#define | GRIOMMU_CAP0_FT(_val) |
#define | GRIOMMU_CAP0_ST 0x10000U |
#define | GRIOMMU_CAP0_I 0x8000U |
#define | GRIOMMU_CAP0_IT 0x4000U |
#define | GRIOMMU_CAP0_IA 0x2000U |
#define | GRIOMMU_CAP0_IP 0x1000U |
#define | GRIOMMU_CAP0_MB 0x100U |
#define | GRIOMMU_CAP0_GRPS_SHIFT 4 |
#define | GRIOMMU_CAP0_GRPS_MASK 0xf0U |
#define | GRIOMMU_CAP0_GRPS_GET(_reg) |
#define | GRIOMMU_CAP0_GRPS_SET(_reg, _val) |
#define | GRIOMMU_CAP0_GRPS(_val) |
#define | GRIOMMU_CAP0_MSTS_SHIFT 0 |
#define | GRIOMMU_CAP0_MSTS_MASK 0xfU |
#define | GRIOMMU_CAP0_MSTS_GET(_reg) |
#define | GRIOMMU_CAP0_MSTS_SET(_reg, _val) |
#define | GRIOMMU_CAP0_MSTS(_val) |
#define | GRIOMMU_CAP1_CADDR_SHIFT 20 |
#define | GRIOMMU_CAP1_CADDR_MASK 0xfff00000U |
#define | GRIOMMU_CAP1_CADDR_GET(_reg) |
#define | GRIOMMU_CAP1_CADDR_SET(_reg, _val) |
#define | GRIOMMU_CAP1_CADDR(_val) |
#define | GRIOMMU_CAP1_CMASK_SHIFT 16 |
#define | GRIOMMU_CAP1_CMASK_MASK 0xf0000U |
#define | GRIOMMU_CAP1_CMASK_GET(_reg) |
#define | GRIOMMU_CAP1_CMASK_SET(_reg, _val) |
#define | GRIOMMU_CAP1_CMASK(_val) |
#define | GRIOMMU_CAP1_CTAGBITS_SHIFT 8 |
#define | GRIOMMU_CAP1_CTAGBITS_MASK 0xff00U |
#define | GRIOMMU_CAP1_CTAGBITS_GET(_reg) |
#define | GRIOMMU_CAP1_CTAGBITS_SET(_reg, _val) |
#define | GRIOMMU_CAP1_CTAGBITS(_val) |
#define | GRIOMMU_CAP1_CISIZE_SHIFT 5 |
#define | GRIOMMU_CAP1_CISIZE_MASK 0xe0U |
#define | GRIOMMU_CAP1_CISIZE_GET(_reg) |
#define | GRIOMMU_CAP1_CISIZE_SET(_reg, _val) |
#define | GRIOMMU_CAP1_CISIZE(_val) |
#define | GRIOMMU_CAP1_CLINES_SHIFT 0 |
#define | GRIOMMU_CAP1_CLINES_MASK 0x1fU |
#define | GRIOMMU_CAP1_CLINES_GET(_reg) |
#define | GRIOMMU_CAP1_CLINES_SET(_reg, _val) |
#define | GRIOMMU_CAP1_CLINES(_val) |
#define | GRIOMMU_CAP2_TMASK_SHIFT 24 |
#define | GRIOMMU_CAP2_TMASK_MASK 0xff000000U |
#define | GRIOMMU_CAP2_TMASK_GET(_reg) |
#define | GRIOMMU_CAP2_TMASK_SET(_reg, _val) |
#define | GRIOMMU_CAP2_TMASK(_val) |
#define | GRIOMMU_CAP2_MTYPE_SHIFT 18 |
#define | GRIOMMU_CAP2_MTYPE_MASK 0xc0000U |
#define | GRIOMMU_CAP2_MTYPE_GET(_reg) |
#define | GRIOMMU_CAP2_MTYPE_SET(_reg, _val) |
#define | GRIOMMU_CAP2_MTYPE(_val) |
#define | GRIOMMU_CAP2_TTYPE_SHIFT 16 |
#define | GRIOMMU_CAP2_TTYPE_MASK 0x30000U |
#define | GRIOMMU_CAP2_TTYPE_GET(_reg) |
#define | GRIOMMU_CAP2_TTYPE_SET(_reg, _val) |
#define | GRIOMMU_CAP2_TTYPE(_val) |
#define | GRIOMMU_CAP2_TTAGBITS_SHIFT 8 |
#define | GRIOMMU_CAP2_TTAGBITS_MASK 0xff00U |
#define | GRIOMMU_CAP2_TTAGBITS_GET(_reg) |
#define | GRIOMMU_CAP2_TTAGBITS_SET(_reg, _val) |
#define | GRIOMMU_CAP2_TTAGBITS(_val) |
#define | GRIOMMU_CAP2_ISIZE_SHIFT 5 |
#define | GRIOMMU_CAP2_ISIZE_MASK 0xe0U |
#define | GRIOMMU_CAP2_ISIZE_GET(_reg) |
#define | GRIOMMU_CAP2_ISIZE_SET(_reg, _val) |
#define | GRIOMMU_CAP2_ISIZE(_val) |
#define | GRIOMMU_CAP2_TLBENT_SHIFT 0 |
#define | GRIOMMU_CAP2_TLBENT_MASK 0x1fU |
#define | GRIOMMU_CAP2_TLBENT_GET(_reg) |
#define | GRIOMMU_CAP2_TLBENT_SET(_reg, _val) |
#define | GRIOMMU_CAP2_TLBENT(_val) |
#define | GRIOMMU_CTRL_PGSZ_SHIFT 18 |
#define | GRIOMMU_CTRL_PGSZ_MASK 0x1c0000U |
#define | GRIOMMU_CTRL_PGSZ_GET(_reg) |
#define | GRIOMMU_CTRL_PGSZ_SET(_reg, _val) |
#define | GRIOMMU_CTRL_PGSZ(_val) |
#define | GRIOMMU_CTRL_LB 0x20000U |
#define | GRIOMMU_CTRL_SP 0x10000U |
#define | GRIOMMU_CTRL_ITR_SHIFT 12 |
#define | GRIOMMU_CTRL_ITR_MASK 0xf000U |
#define | GRIOMMU_CTRL_ITR_GET(_reg) |
#define | GRIOMMU_CTRL_ITR_SET(_reg, _val) |
#define | GRIOMMU_CTRL_ITR(_val) |
#define | GRIOMMU_CTRL_DP 0x800U |
#define | GRIOMMU_CTRL_SIV 0x400U |
#define | GRIOMMU_CTRL_HPROT_SHIFT 8 |
#define | GRIOMMU_CTRL_HPROT_MASK 0x300U |
#define | GRIOMMU_CTRL_HPROT_GET(_reg) |
#define | GRIOMMU_CTRL_HPROT_SET(_reg, _val) |
#define | GRIOMMU_CTRL_HPROT(_val) |
#define | GRIOMMU_CTRL_AU 0x80U |
#define | GRIOMMU_CTRL_WP 0x40U |
#define | GRIOMMU_CTRL_DM 0x20U |
#define | GRIOMMU_CTRL_GS 0x10U |
#define | GRIOMMU_CTRL_CE 0x8U |
#define | GRIOMMU_CTRL_PM_SHIFT 1 |
#define | GRIOMMU_CTRL_PM_MASK 0x6U |
#define | GRIOMMU_CTRL_PM_GET(_reg) |
#define | GRIOMMU_CTRL_PM_SET(_reg, _val) |
#define | GRIOMMU_CTRL_PM(_val) |
#define | GRIOMMU_CTRL_EN 0x1U |
#define | GRIOMMU_FLUSH_FGRP_SHIFT 4 |
#define | GRIOMMU_FLUSH_FGRP_MASK 0xf0U |
#define | GRIOMMU_FLUSH_FGRP_GET(_reg) |
#define | GRIOMMU_FLUSH_FGRP_SET(_reg, _val) |
#define | GRIOMMU_FLUSH_FGRP(_val) |
#define | GRIOMMU_FLUSH_GF 0x2U |
#define | GRIOMMU_FLUSH_F 0x1U |
#define | GRIOMMU_STATUS_PE 0x20U |
#define | GRIOMMU_STATUS_DE 0x10U |
#define | GRIOMMU_STATUS_FC 0x8U |
#define | GRIOMMU_STATUS_FL 0x4U |
#define | GRIOMMU_STATUS_AD 0x2U |
#define | GRIOMMU_STATUS_TE 0x1U |
#define | GRIOMMU_IMASK_PEI 0x20U |
#define | GRIOMMU_IMASK_FCI 0x8U |
#define | GRIOMMU_IMASK_FLI 0x4U |
#define | GRIOMMU_IMASK_ADI 0x2U |
#define | GRIOMMU_IMASK_TEI 0x1U |
#define | GRIOMMU_AHBFAS_FADDR_31_5_SHIFT 5 |
#define | GRIOMMU_AHBFAS_FADDR_31_5_MASK 0xffffffe0U |
#define | GRIOMMU_AHBFAS_FADDR_31_5_GET(_reg) |
#define | GRIOMMU_AHBFAS_FADDR_31_5_SET(_reg, _val) |
#define | GRIOMMU_AHBFAS_FADDR_31_5(_val) |
#define | GRIOMMU_AHBFAS_FW 0x10U |
#define | GRIOMMU_AHBFAS_FMASTER_SHIFT 0 |
#define | GRIOMMU_AHBFAS_FMASTER_MASK 0xfU |
#define | GRIOMMU_AHBFAS_FMASTER_GET(_reg) |
#define | GRIOMMU_AHBFAS_FMASTER_SET(_reg, _val) |
#define | GRIOMMU_AHBFAS_FMASTER(_val) |
#define | GRIOMMU_MSTCFG_VENDOR_SHIFT 24 |
#define | GRIOMMU_MSTCFG_VENDOR_MASK 0xff000000U |
#define | GRIOMMU_MSTCFG_VENDOR_GET(_reg) |
#define | GRIOMMU_MSTCFG_VENDOR_SET(_reg, _val) |
#define | GRIOMMU_MSTCFG_VENDOR(_val) |
#define | GRIOMMU_MSTCFG_DEVICE_SHIFT 12 |
#define | GRIOMMU_MSTCFG_DEVICE_MASK 0xfff000U |
#define | GRIOMMU_MSTCFG_DEVICE_GET(_reg) |
#define | GRIOMMU_MSTCFG_DEVICE_SET(_reg, _val) |
#define | GRIOMMU_MSTCFG_DEVICE(_val) |
#define | GRIOMMU_MSTCFG_BS 0x10U |
#define | GRIOMMU_MSTCFG_GROUP_SHIFT 0 |
#define | GRIOMMU_MSTCFG_GROUP_MASK 0xfU |
#define | GRIOMMU_MSTCFG_GROUP_GET(_reg) |
#define | GRIOMMU_MSTCFG_GROUP_SET(_reg, _val) |
#define | GRIOMMU_MSTCFG_GROUP(_val) |
#define | GRIOMMU_GRPCTRL_BASE_31_4_SHIFT 4 |
#define | GRIOMMU_GRPCTRL_BASE_31_4_MASK 0xfffffff0U |
#define | GRIOMMU_GRPCTRL_BASE_31_4_GET(_reg) |
#define | GRIOMMU_GRPCTRL_BASE_31_4_SET(_reg, _val) |
#define | GRIOMMU_GRPCTRL_BASE_31_4(_val) |
#define | GRIOMMU_GRPCTRL_P 0x2U |
#define | GRIOMMU_GRPCTRL_AG 0x1U |
#define | GRIOMMU_DIAGCTRL_DA 0x80000000U |
#define | GRIOMMU_DIAGCTRL_RW 0x40000000U |
#define | GRIOMMU_DIAGCTRL_DP 0x200000U |
#define | GRIOMMU_DIAGCTRL_TP 0x100000U |
#define | GRIOMMU_DIAGCTRL_SETADDR_SHIFT 0 |
#define | GRIOMMU_DIAGCTRL_SETADDR_MASK 0x7ffffU |
#define | GRIOMMU_DIAGCTRL_SETADDR_GET(_reg) |
#define | GRIOMMU_DIAGCTRL_SETADDR_SET(_reg, _val) |
#define | GRIOMMU_DIAGCTRL_SETADDR(_val) |
#define | GRIOMMU_DIAGD_CDATAN_SHIFT 0 |
#define | GRIOMMU_DIAGD_CDATAN_MASK 0xffffffffU |
#define | GRIOMMU_DIAGD_CDATAN_GET(_reg) |
#define | GRIOMMU_DIAGD_CDATAN_SET(_reg, _val) |
#define | GRIOMMU_DIAGD_CDATAN(_val) |
#define | GRIOMMU_DIAGT_TAG_SHIFT 1 |
#define | GRIOMMU_DIAGT_TAG_MASK 0xfffffffeU |
#define | GRIOMMU_DIAGT_TAG_GET(_reg) |
#define | GRIOMMU_DIAGT_TAG_SET(_reg, _val) |
#define | GRIOMMU_DIAGT_TAG(_val) |
#define | GRIOMMU_DIAGT_V 0x1U |
#define | GRIOMMU_DERRI_DPERRINJ_SHIFT 0 |
#define | GRIOMMU_DERRI_DPERRINJ_MASK 0xffffffffU |
#define | GRIOMMU_DERRI_DPERRINJ_GET(_reg) |
#define | GRIOMMU_DERRI_DPERRINJ_SET(_reg, _val) |
#define | GRIOMMU_DERRI_DPERRINJ(_val) |
#define | GRIOMMU_TERRI_TPERRINJ_SHIFT 0 |
#define | GRIOMMU_TERRI_TPERRINJ_MASK 0xffffffffU |
#define | GRIOMMU_TERRI_TPERRINJ_GET(_reg) |
#define | GRIOMMU_TERRI_TPERRINJ_SET(_reg, _val) |
#define | GRIOMMU_TERRI_TPERRINJ(_val) |
#define | GRIOMMU_ASMPCTRL_FC 0x40000U |
#define | GRIOMMU_ASMPCTRL_SC 0x20000U |
#define | GRIOMMU_ASMPCTRL_MC 0x10000U |
#define | GRIOMMU_ASMPCTRL_GRPACCSZCTRL_SHIFT 0 |
#define | GRIOMMU_ASMPCTRL_GRPACCSZCTRL_MASK 0xffffU |
#define | GRIOMMU_ASMPCTRL_GRPACCSZCTRL_GET(_reg) |
#define | GRIOMMU_ASMPCTRL_GRPACCSZCTRL_SET(_reg, _val) |
#define | GRIOMMU_ASMPCTRL_GRPACCSZCTRL(_val) |
Typedefs | |
typedef struct griommu | griommu |
This structure defines the GRIOMMU register block memory map. | |
This header file defines the GRIOMMU register block interface.