RTEMS 6.1-rc5
Loading...
Searching...
No Matches
gr1553b-regs.h
Go to the documentation of this file.
1/* SPDX-License-Identifier: BSD-2-Clause */
2
11/*
12 * Copyright (C) 2021 embedded brains GmbH & Co. KG
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions
16 * are met:
17 * 1. Redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer.
19 * 2. Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in the
21 * documentation and/or other materials provided with the distribution.
22 *
23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
33 * POSSIBILITY OF SUCH DAMAGE.
34 */
35
36/*
37 * This file is part of the RTEMS quality process and was automatically
38 * generated. If you find something that needs to be fixed or
39 * worded better please post a report or patch to an RTEMS mailing list
40 * or raise a bug report:
41 *
42 * https://www.rtems.org/bugs.html
43 *
44 * For information on updating and regenerating please refer to the How-To
45 * section in the Software Requirements Engineering chapter of the
46 * RTEMS Software Engineering manual. The manual is provided as a part of
47 * a release. For development sources please refer to the online
48 * documentation at:
49 *
50 * https://docs.rtems.org
51 */
52
53/* Generated from spec:/dev/grlib/if/gr1553b-header */
54
55#ifndef _GRLIB_GR1553B_REGS_H
56#define _GRLIB_GR1553B_REGS_H
57
58#include <stdint.h>
59
60#ifdef __cplusplus
61extern "C" {
62#endif
63
64/* Generated from spec:/dev/grlib/if/gr1553b */
65
84#define GR1553B_IRQ_BMTOF 0x20000U
85
86#define GR1553B_IRQ_BMD 0x10000U
87
88#define GR1553B_IRQ_RTTE 0x400U
89
90#define GR1553B_IRQ_RTD 0x200U
91
92#define GR1553B_IRQ_RTEV 0x100U
93
94#define GR1553B_IRQ_BCWK 0x4U
95
96#define GR1553B_IRQ_BCD 0x2U
97
98#define GR1553B_IRQ_BCEV 0x1U
99
110#define GR1553B_IRQE_BMTOE 0x20000U
111
112#define GR1553B_IRQE_BMDE 0x10000U
113
114#define GR1553B_IRQE_RTTEE 0x400U
115
116#define GR1553B_IRQE_RTDE 0x200U
117
118#define GR1553B_IRQE_RTEVE 0x100U
119
120#define GR1553B_IRQE_BCWKE 0x4U
121
122#define GR1553B_IRQE_BCDE 0x2U
123
124#define GR1553B_IRQE_BCEVE 0x1U
125
136#define GR1553B_HC_MOD 0x80000000U
137
138#define GR1553B_HC_CVER 0x1000U
139
140#define GR1553B_HC_XKEYS 0x800U
141
142#define GR1553B_HC_ENDIAN_SHIFT 9
143#define GR1553B_HC_ENDIAN_MASK 0x600U
144#define GR1553B_HC_ENDIAN_GET( _reg ) \
145 ( ( ( _reg ) & GR1553B_HC_ENDIAN_MASK ) >> \
146 GR1553B_HC_ENDIAN_SHIFT )
147#define GR1553B_HC_ENDIAN_SET( _reg, _val ) \
148 ( ( ( _reg ) & ~GR1553B_HC_ENDIAN_MASK ) | \
149 ( ( ( _val ) << GR1553B_HC_ENDIAN_SHIFT ) & \
150 GR1553B_HC_ENDIAN_MASK ) )
151#define GR1553B_HC_ENDIAN( _val ) \
152 ( ( ( _val ) << GR1553B_HC_ENDIAN_SHIFT ) & \
153 GR1553B_HC_ENDIAN_MASK )
154
155#define GR1553B_HC_SCLK 0x100U
156
157#define GR1553B_HC_CCFREQ_SHIFT 0
158#define GR1553B_HC_CCFREQ_MASK 0xffU
159#define GR1553B_HC_CCFREQ_GET( _reg ) \
160 ( ( ( _reg ) & GR1553B_HC_CCFREQ_MASK ) >> \
161 GR1553B_HC_CCFREQ_SHIFT )
162#define GR1553B_HC_CCFREQ_SET( _reg, _val ) \
163 ( ( ( _reg ) & ~GR1553B_HC_CCFREQ_MASK ) | \
164 ( ( ( _val ) << GR1553B_HC_CCFREQ_SHIFT ) & \
165 GR1553B_HC_CCFREQ_MASK ) )
166#define GR1553B_HC_CCFREQ( _val ) \
167 ( ( ( _val ) << GR1553B_HC_CCFREQ_SHIFT ) & \
168 GR1553B_HC_CCFREQ_MASK )
169
181#define GR1553B_BCSC_BCSUP 0x80000000U
182
183#define GR1553B_BCSC_BCFEAT_SHIFT 28
184#define GR1553B_BCSC_BCFEAT_MASK 0x70000000U
185#define GR1553B_BCSC_BCFEAT_GET( _reg ) \
186 ( ( ( _reg ) & GR1553B_BCSC_BCFEAT_MASK ) >> \
187 GR1553B_BCSC_BCFEAT_SHIFT )
188#define GR1553B_BCSC_BCFEAT_SET( _reg, _val ) \
189 ( ( ( _reg ) & ~GR1553B_BCSC_BCFEAT_MASK ) | \
190 ( ( ( _val ) << GR1553B_BCSC_BCFEAT_SHIFT ) & \
191 GR1553B_BCSC_BCFEAT_MASK ) )
192#define GR1553B_BCSC_BCFEAT( _val ) \
193 ( ( ( _val ) << GR1553B_BCSC_BCFEAT_SHIFT ) & \
194 GR1553B_BCSC_BCFEAT_MASK )
195
196#define GR1553B_BCSC_BCCHK 0x10000U
197
198#define GR1553B_BCSC_ASADL_SHIFT 11
199#define GR1553B_BCSC_ASADL_MASK 0xf800U
200#define GR1553B_BCSC_ASADL_GET( _reg ) \
201 ( ( ( _reg ) & GR1553B_BCSC_ASADL_MASK ) >> \
202 GR1553B_BCSC_ASADL_SHIFT )
203#define GR1553B_BCSC_ASADL_SET( _reg, _val ) \
204 ( ( ( _reg ) & ~GR1553B_BCSC_ASADL_MASK ) | \
205 ( ( ( _val ) << GR1553B_BCSC_ASADL_SHIFT ) & \
206 GR1553B_BCSC_ASADL_MASK ) )
207#define GR1553B_BCSC_ASADL( _val ) \
208 ( ( ( _val ) << GR1553B_BCSC_ASADL_SHIFT ) & \
209 GR1553B_BCSC_ASADL_MASK )
210
211#define GR1553B_BCSC_ASST_SHIFT 8
212#define GR1553B_BCSC_ASST_MASK 0x300U
213#define GR1553B_BCSC_ASST_GET( _reg ) \
214 ( ( ( _reg ) & GR1553B_BCSC_ASST_MASK ) >> \
215 GR1553B_BCSC_ASST_SHIFT )
216#define GR1553B_BCSC_ASST_SET( _reg, _val ) \
217 ( ( ( _reg ) & ~GR1553B_BCSC_ASST_MASK ) | \
218 ( ( ( _val ) << GR1553B_BCSC_ASST_SHIFT ) & \
219 GR1553B_BCSC_ASST_MASK ) )
220#define GR1553B_BCSC_ASST( _val ) \
221 ( ( ( _val ) << GR1553B_BCSC_ASST_SHIFT ) & \
222 GR1553B_BCSC_ASST_MASK )
223
224#define GR1553B_BCSC_SCADL_SHIFT 3
225#define GR1553B_BCSC_SCADL_MASK 0xf8U
226#define GR1553B_BCSC_SCADL_GET( _reg ) \
227 ( ( ( _reg ) & GR1553B_BCSC_SCADL_MASK ) >> \
228 GR1553B_BCSC_SCADL_SHIFT )
229#define GR1553B_BCSC_SCADL_SET( _reg, _val ) \
230 ( ( ( _reg ) & ~GR1553B_BCSC_SCADL_MASK ) | \
231 ( ( ( _val ) << GR1553B_BCSC_SCADL_SHIFT ) & \
232 GR1553B_BCSC_SCADL_MASK ) )
233#define GR1553B_BCSC_SCADL( _val ) \
234 ( ( ( _val ) << GR1553B_BCSC_SCADL_SHIFT ) & \
235 GR1553B_BCSC_SCADL_MASK )
236
237#define GR1553B_BCSC_SCST_SHIFT 0
238#define GR1553B_BCSC_SCST_MASK 0x7U
239#define GR1553B_BCSC_SCST_GET( _reg ) \
240 ( ( ( _reg ) & GR1553B_BCSC_SCST_MASK ) >> \
241 GR1553B_BCSC_SCST_SHIFT )
242#define GR1553B_BCSC_SCST_SET( _reg, _val ) \
243 ( ( ( _reg ) & ~GR1553B_BCSC_SCST_MASK ) | \
244 ( ( ( _val ) << GR1553B_BCSC_SCST_SHIFT ) & \
245 GR1553B_BCSC_SCST_MASK ) )
246#define GR1553B_BCSC_SCST( _val ) \
247 ( ( ( _val ) << GR1553B_BCSC_SCST_SHIFT ) & \
248 GR1553B_BCSC_SCST_MASK )
249
260#define GR1553B_BCA_BCKEY_SHIFT 16
261#define GR1553B_BCA_BCKEY_MASK 0xffff0000U
262#define GR1553B_BCA_BCKEY_GET( _reg ) \
263 ( ( ( _reg ) & GR1553B_BCA_BCKEY_MASK ) >> \
264 GR1553B_BCA_BCKEY_SHIFT )
265#define GR1553B_BCA_BCKEY_SET( _reg, _val ) \
266 ( ( ( _reg ) & ~GR1553B_BCA_BCKEY_MASK ) | \
267 ( ( ( _val ) << GR1553B_BCA_BCKEY_SHIFT ) & \
268 GR1553B_BCA_BCKEY_MASK ) )
269#define GR1553B_BCA_BCKEY( _val ) \
270 ( ( ( _val ) << GR1553B_BCA_BCKEY_SHIFT ) & \
271 GR1553B_BCA_BCKEY_MASK )
272
273#define GR1553B_BCA_ASSTP 0x200U
274
275#define GR1553B_BCA_ASSRT 0x100U
276
277#define GR1553B_BCA_CLRT 0x10U
278
279#define GR1553B_BCA_SETT 0x8U
280
281#define GR1553B_BCA_SCSTP 0x4U
282
283#define GR1553B_BCA_SCSUS 0x2U
284
285#define GR1553B_BCA_SCSRT 0x1U
286
298#define GR1553B_BCTNP_POINTER_SHIFT 0
299#define GR1553B_BCTNP_POINTER_MASK 0xffffffffU
300#define GR1553B_BCTNP_POINTER_GET( _reg ) \
301 ( ( ( _reg ) & GR1553B_BCTNP_POINTER_MASK ) >> \
302 GR1553B_BCTNP_POINTER_SHIFT )
303#define GR1553B_BCTNP_POINTER_SET( _reg, _val ) \
304 ( ( ( _reg ) & ~GR1553B_BCTNP_POINTER_MASK ) | \
305 ( ( ( _val ) << GR1553B_BCTNP_POINTER_SHIFT ) & \
306 GR1553B_BCTNP_POINTER_MASK ) )
307#define GR1553B_BCTNP_POINTER( _val ) \
308 ( ( ( _val ) << GR1553B_BCTNP_POINTER_SHIFT ) & \
309 GR1553B_BCTNP_POINTER_MASK )
310
322#define GR1553B_BCANP_POINTER_SHIFT 0
323#define GR1553B_BCANP_POINTER_MASK 0xffffffffU
324#define GR1553B_BCANP_POINTER_GET( _reg ) \
325 ( ( ( _reg ) & GR1553B_BCANP_POINTER_MASK ) >> \
326 GR1553B_BCANP_POINTER_SHIFT )
327#define GR1553B_BCANP_POINTER_SET( _reg, _val ) \
328 ( ( ( _reg ) & ~GR1553B_BCANP_POINTER_MASK ) | \
329 ( ( ( _val ) << GR1553B_BCANP_POINTER_SHIFT ) & \
330 GR1553B_BCANP_POINTER_MASK ) )
331#define GR1553B_BCANP_POINTER( _val ) \
332 ( ( ( _val ) << GR1553B_BCANP_POINTER_SHIFT ) & \
333 GR1553B_BCANP_POINTER_MASK )
334
345#define GR1553B_BCT_SCTM_SHIFT 0
346#define GR1553B_BCT_SCTM_MASK 0xffffffU
347#define GR1553B_BCT_SCTM_GET( _reg ) \
348 ( ( ( _reg ) & GR1553B_BCT_SCTM_MASK ) >> \
349 GR1553B_BCT_SCTM_SHIFT )
350#define GR1553B_BCT_SCTM_SET( _reg, _val ) \
351 ( ( ( _reg ) & ~GR1553B_BCT_SCTM_MASK ) | \
352 ( ( ( _val ) << GR1553B_BCT_SCTM_SHIFT ) & \
353 GR1553B_BCT_SCTM_MASK ) )
354#define GR1553B_BCT_SCTM( _val ) \
355 ( ( ( _val ) << GR1553B_BCT_SCTM_SHIFT ) & \
356 GR1553B_BCT_SCTM_MASK )
357
369#define GR1553B_BCRP_POSITION_SHIFT 0
370#define GR1553B_BCRP_POSITION_MASK 0xffffffffU
371#define GR1553B_BCRP_POSITION_GET( _reg ) \
372 ( ( ( _reg ) & GR1553B_BCRP_POSITION_MASK ) >> \
373 GR1553B_BCRP_POSITION_SHIFT )
374#define GR1553B_BCRP_POSITION_SET( _reg, _val ) \
375 ( ( ( _reg ) & ~GR1553B_BCRP_POSITION_MASK ) | \
376 ( ( ( _val ) << GR1553B_BCRP_POSITION_SHIFT ) & \
377 GR1553B_BCRP_POSITION_MASK ) )
378#define GR1553B_BCRP_POSITION( _val ) \
379 ( ( ( _val ) << GR1553B_BCRP_POSITION_SHIFT ) & \
380 GR1553B_BCRP_POSITION_MASK )
381
392#define GR1553B_BCBS_SWAP_SHIFT 0
393#define GR1553B_BCBS_SWAP_MASK 0xffffffffU
394#define GR1553B_BCBS_SWAP_GET( _reg ) \
395 ( ( ( _reg ) & GR1553B_BCBS_SWAP_MASK ) >> \
396 GR1553B_BCBS_SWAP_SHIFT )
397#define GR1553B_BCBS_SWAP_SET( _reg, _val ) \
398 ( ( ( _reg ) & ~GR1553B_BCBS_SWAP_MASK ) | \
399 ( ( ( _val ) << GR1553B_BCBS_SWAP_SHIFT ) & \
400 GR1553B_BCBS_SWAP_MASK ) )
401#define GR1553B_BCBS_SWAP( _val ) \
402 ( ( ( _val ) << GR1553B_BCBS_SWAP_SHIFT ) & \
403 GR1553B_BCBS_SWAP_MASK )
404
416#define GR1553B_BCTCP_POINTER_SHIFT 0
417#define GR1553B_BCTCP_POINTER_MASK 0xffffffffU
418#define GR1553B_BCTCP_POINTER_GET( _reg ) \
419 ( ( ( _reg ) & GR1553B_BCTCP_POINTER_MASK ) >> \
420 GR1553B_BCTCP_POINTER_SHIFT )
421#define GR1553B_BCTCP_POINTER_SET( _reg, _val ) \
422 ( ( ( _reg ) & ~GR1553B_BCTCP_POINTER_MASK ) | \
423 ( ( ( _val ) << GR1553B_BCTCP_POINTER_SHIFT ) & \
424 GR1553B_BCTCP_POINTER_MASK ) )
425#define GR1553B_BCTCP_POINTER( _val ) \
426 ( ( ( _val ) << GR1553B_BCTCP_POINTER_SHIFT ) & \
427 GR1553B_BCTCP_POINTER_MASK )
428
440#define GR1553B_BCACP_POINTER_SHIFT 0
441#define GR1553B_BCACP_POINTER_MASK 0xffffffffU
442#define GR1553B_BCACP_POINTER_GET( _reg ) \
443 ( ( ( _reg ) & GR1553B_BCACP_POINTER_MASK ) >> \
444 GR1553B_BCACP_POINTER_SHIFT )
445#define GR1553B_BCACP_POINTER_SET( _reg, _val ) \
446 ( ( ( _reg ) & ~GR1553B_BCACP_POINTER_MASK ) | \
447 ( ( ( _val ) << GR1553B_BCACP_POINTER_SHIFT ) & \
448 GR1553B_BCACP_POINTER_MASK ) )
449#define GR1553B_BCACP_POINTER( _val ) \
450 ( ( ( _val ) << GR1553B_BCACP_POINTER_SHIFT ) & \
451 GR1553B_BCACP_POINTER_MASK )
452
463#define GR1553B_RTS_RTSUP 0x80000000U
464
465#define GR1553B_RTS_ACT 0x8U
466
467#define GR1553B_RTS_SHDA 0x4U
468
469#define GR1553B_RTS_SHDB 0x2U
470
471#define GR1553B_RTS_RUN 0x1U
472
483#define GR1553B_RTC_RTKEY_SHIFT 16
484#define GR1553B_RTC_RTKEY_MASK 0xffff0000U
485#define GR1553B_RTC_RTKEY_GET( _reg ) \
486 ( ( ( _reg ) & GR1553B_RTC_RTKEY_MASK ) >> \
487 GR1553B_RTC_RTKEY_SHIFT )
488#define GR1553B_RTC_RTKEY_SET( _reg, _val ) \
489 ( ( ( _reg ) & ~GR1553B_RTC_RTKEY_MASK ) | \
490 ( ( ( _val ) << GR1553B_RTC_RTKEY_SHIFT ) & \
491 GR1553B_RTC_RTKEY_MASK ) )
492#define GR1553B_RTC_RTKEY( _val ) \
493 ( ( ( _val ) << GR1553B_RTC_RTKEY_SHIFT ) & \
494 GR1553B_RTC_RTKEY_MASK )
495
496#define GR1553B_RTC_SYS 0x8000U
497
498#define GR1553B_RTC_SYDS 0x4000U
499
500#define GR1553B_RTC_BRS 0x2000U
501
502#define GR1553B_RTC_RTEIS 0x40U
503
504#define GR1553B_RTC_RTADDR_SHIFT 1
505#define GR1553B_RTC_RTADDR_MASK 0x3eU
506#define GR1553B_RTC_RTADDR_GET( _reg ) \
507 ( ( ( _reg ) & GR1553B_RTC_RTADDR_MASK ) >> \
508 GR1553B_RTC_RTADDR_SHIFT )
509#define GR1553B_RTC_RTADDR_SET( _reg, _val ) \
510 ( ( ( _reg ) & ~GR1553B_RTC_RTADDR_MASK ) | \
511 ( ( ( _val ) << GR1553B_RTC_RTADDR_SHIFT ) & \
512 GR1553B_RTC_RTADDR_MASK ) )
513#define GR1553B_RTC_RTADDR( _val ) \
514 ( ( ( _val ) << GR1553B_RTC_RTADDR_SHIFT ) & \
515 GR1553B_RTC_RTADDR_MASK )
516
517#define GR1553B_RTC_RTEN 0x1U
518
529#define GR1553B_RTBS_TFDE 0x100U
530
531#define GR1553B_RTBS_SREQ 0x10U
532
533#define GR1553B_RTBS_BUSY 0x8U
534
535#define GR1553B_RTBS_SSF 0x4U
536
537#define GR1553B_RTBS_DBCA 0x2U
538
539#define GR1553B_RTBS_TFLG 0x1U
540
551#define GR1553B_RTSW_BITW_SHIFT 16
552#define GR1553B_RTSW_BITW_MASK 0xffff0000U
553#define GR1553B_RTSW_BITW_GET( _reg ) \
554 ( ( ( _reg ) & GR1553B_RTSW_BITW_MASK ) >> \
555 GR1553B_RTSW_BITW_SHIFT )
556#define GR1553B_RTSW_BITW_SET( _reg, _val ) \
557 ( ( ( _reg ) & ~GR1553B_RTSW_BITW_MASK ) | \
558 ( ( ( _val ) << GR1553B_RTSW_BITW_SHIFT ) & \
559 GR1553B_RTSW_BITW_MASK ) )
560#define GR1553B_RTSW_BITW( _val ) \
561 ( ( ( _val ) << GR1553B_RTSW_BITW_SHIFT ) & \
562 GR1553B_RTSW_BITW_MASK )
563
564#define GR1553B_RTSW_VECW_SHIFT 0
565#define GR1553B_RTSW_VECW_MASK 0xffffU
566#define GR1553B_RTSW_VECW_GET( _reg ) \
567 ( ( ( _reg ) & GR1553B_RTSW_VECW_MASK ) >> \
568 GR1553B_RTSW_VECW_SHIFT )
569#define GR1553B_RTSW_VECW_SET( _reg, _val ) \
570 ( ( ( _reg ) & ~GR1553B_RTSW_VECW_MASK ) | \
571 ( ( ( _val ) << GR1553B_RTSW_VECW_SHIFT ) & \
572 GR1553B_RTSW_VECW_MASK ) )
573#define GR1553B_RTSW_VECW( _val ) \
574 ( ( ( _val ) << GR1553B_RTSW_VECW_SHIFT ) & \
575 GR1553B_RTSW_VECW_MASK )
576
587#define GR1553B_RTSY_SYTM_SHIFT 16
588#define GR1553B_RTSY_SYTM_MASK 0xffff0000U
589#define GR1553B_RTSY_SYTM_GET( _reg ) \
590 ( ( ( _reg ) & GR1553B_RTSY_SYTM_MASK ) >> \
591 GR1553B_RTSY_SYTM_SHIFT )
592#define GR1553B_RTSY_SYTM_SET( _reg, _val ) \
593 ( ( ( _reg ) & ~GR1553B_RTSY_SYTM_MASK ) | \
594 ( ( ( _val ) << GR1553B_RTSY_SYTM_SHIFT ) & \
595 GR1553B_RTSY_SYTM_MASK ) )
596#define GR1553B_RTSY_SYTM( _val ) \
597 ( ( ( _val ) << GR1553B_RTSY_SYTM_SHIFT ) & \
598 GR1553B_RTSY_SYTM_MASK )
599
600#define GR1553B_RTSY_SYD_SHIFT 0
601#define GR1553B_RTSY_SYD_MASK 0xffffU
602#define GR1553B_RTSY_SYD_GET( _reg ) \
603 ( ( ( _reg ) & GR1553B_RTSY_SYD_MASK ) >> \
604 GR1553B_RTSY_SYD_SHIFT )
605#define GR1553B_RTSY_SYD_SET( _reg, _val ) \
606 ( ( ( _reg ) & ~GR1553B_RTSY_SYD_MASK ) | \
607 ( ( ( _val ) << GR1553B_RTSY_SYD_SHIFT ) & \
608 GR1553B_RTSY_SYD_MASK ) )
609#define GR1553B_RTSY_SYD( _val ) \
610 ( ( ( _val ) << GR1553B_RTSY_SYD_SHIFT ) & \
611 GR1553B_RTSY_SYD_MASK )
612
624#define GR1553B_RTSTBA_SATB_SHIFT 9
625#define GR1553B_RTSTBA_SATB_MASK 0xfffffe00U
626#define GR1553B_RTSTBA_SATB_GET( _reg ) \
627 ( ( ( _reg ) & GR1553B_RTSTBA_SATB_MASK ) >> \
628 GR1553B_RTSTBA_SATB_SHIFT )
629#define GR1553B_RTSTBA_SATB_SET( _reg, _val ) \
630 ( ( ( _reg ) & ~GR1553B_RTSTBA_SATB_MASK ) | \
631 ( ( ( _val ) << GR1553B_RTSTBA_SATB_SHIFT ) & \
632 GR1553B_RTSTBA_SATB_MASK ) )
633#define GR1553B_RTSTBA_SATB( _val ) \
634 ( ( ( _val ) << GR1553B_RTSTBA_SATB_SHIFT ) & \
635 GR1553B_RTSTBA_SATB_MASK )
636
648#define GR1553B_RTMCC_RRTB_SHIFT 28
649#define GR1553B_RTMCC_RRTB_MASK 0x30000000U
650#define GR1553B_RTMCC_RRTB_GET( _reg ) \
651 ( ( ( _reg ) & GR1553B_RTMCC_RRTB_MASK ) >> \
652 GR1553B_RTMCC_RRTB_SHIFT )
653#define GR1553B_RTMCC_RRTB_SET( _reg, _val ) \
654 ( ( ( _reg ) & ~GR1553B_RTMCC_RRTB_MASK ) | \
655 ( ( ( _val ) << GR1553B_RTMCC_RRTB_SHIFT ) & \
656 GR1553B_RTMCC_RRTB_MASK ) )
657#define GR1553B_RTMCC_RRTB( _val ) \
658 ( ( ( _val ) << GR1553B_RTMCC_RRTB_SHIFT ) & \
659 GR1553B_RTMCC_RRTB_MASK )
660
661#define GR1553B_RTMCC_RRT_SHIFT 26
662#define GR1553B_RTMCC_RRT_MASK 0xc000000U
663#define GR1553B_RTMCC_RRT_GET( _reg ) \
664 ( ( ( _reg ) & GR1553B_RTMCC_RRT_MASK ) >> \
665 GR1553B_RTMCC_RRT_SHIFT )
666#define GR1553B_RTMCC_RRT_SET( _reg, _val ) \
667 ( ( ( _reg ) & ~GR1553B_RTMCC_RRT_MASK ) | \
668 ( ( ( _val ) << GR1553B_RTMCC_RRT_SHIFT ) & \
669 GR1553B_RTMCC_RRT_MASK ) )
670#define GR1553B_RTMCC_RRT( _val ) \
671 ( ( ( _val ) << GR1553B_RTMCC_RRT_SHIFT ) & \
672 GR1553B_RTMCC_RRT_MASK )
673
674#define GR1553B_RTMCC_ITFB_SHIFT 24
675#define GR1553B_RTMCC_ITFB_MASK 0x3000000U
676#define GR1553B_RTMCC_ITFB_GET( _reg ) \
677 ( ( ( _reg ) & GR1553B_RTMCC_ITFB_MASK ) >> \
678 GR1553B_RTMCC_ITFB_SHIFT )
679#define GR1553B_RTMCC_ITFB_SET( _reg, _val ) \
680 ( ( ( _reg ) & ~GR1553B_RTMCC_ITFB_MASK ) | \
681 ( ( ( _val ) << GR1553B_RTMCC_ITFB_SHIFT ) & \
682 GR1553B_RTMCC_ITFB_MASK ) )
683#define GR1553B_RTMCC_ITFB( _val ) \
684 ( ( ( _val ) << GR1553B_RTMCC_ITFB_SHIFT ) & \
685 GR1553B_RTMCC_ITFB_MASK )
686
687#define GR1553B_RTMCC_ITF_SHIFT 22
688#define GR1553B_RTMCC_ITF_MASK 0xc00000U
689#define GR1553B_RTMCC_ITF_GET( _reg ) \
690 ( ( ( _reg ) & GR1553B_RTMCC_ITF_MASK ) >> \
691 GR1553B_RTMCC_ITF_SHIFT )
692#define GR1553B_RTMCC_ITF_SET( _reg, _val ) \
693 ( ( ( _reg ) & ~GR1553B_RTMCC_ITF_MASK ) | \
694 ( ( ( _val ) << GR1553B_RTMCC_ITF_SHIFT ) & \
695 GR1553B_RTMCC_ITF_MASK ) )
696#define GR1553B_RTMCC_ITF( _val ) \
697 ( ( ( _val ) << GR1553B_RTMCC_ITF_SHIFT ) & \
698 GR1553B_RTMCC_ITF_MASK )
699
700#define GR1553B_RTMCC_ISTB_SHIFT 20
701#define GR1553B_RTMCC_ISTB_MASK 0x300000U
702#define GR1553B_RTMCC_ISTB_GET( _reg ) \
703 ( ( ( _reg ) & GR1553B_RTMCC_ISTB_MASK ) >> \
704 GR1553B_RTMCC_ISTB_SHIFT )
705#define GR1553B_RTMCC_ISTB_SET( _reg, _val ) \
706 ( ( ( _reg ) & ~GR1553B_RTMCC_ISTB_MASK ) | \
707 ( ( ( _val ) << GR1553B_RTMCC_ISTB_SHIFT ) & \
708 GR1553B_RTMCC_ISTB_MASK ) )
709#define GR1553B_RTMCC_ISTB( _val ) \
710 ( ( ( _val ) << GR1553B_RTMCC_ISTB_SHIFT ) & \
711 GR1553B_RTMCC_ISTB_MASK )
712
713#define GR1553B_RTMCC_IST_SHIFT 18
714#define GR1553B_RTMCC_IST_MASK 0xc0000U
715#define GR1553B_RTMCC_IST_GET( _reg ) \
716 ( ( ( _reg ) & GR1553B_RTMCC_IST_MASK ) >> \
717 GR1553B_RTMCC_IST_SHIFT )
718#define GR1553B_RTMCC_IST_SET( _reg, _val ) \
719 ( ( ( _reg ) & ~GR1553B_RTMCC_IST_MASK ) | \
720 ( ( ( _val ) << GR1553B_RTMCC_IST_SHIFT ) & \
721 GR1553B_RTMCC_IST_MASK ) )
722#define GR1553B_RTMCC_IST( _val ) \
723 ( ( ( _val ) << GR1553B_RTMCC_IST_SHIFT ) & \
724 GR1553B_RTMCC_IST_MASK )
725
726#define GR1553B_RTMCC_DBC_SHIFT 16
727#define GR1553B_RTMCC_DBC_MASK 0x30000U
728#define GR1553B_RTMCC_DBC_GET( _reg ) \
729 ( ( ( _reg ) & GR1553B_RTMCC_DBC_MASK ) >> \
730 GR1553B_RTMCC_DBC_SHIFT )
731#define GR1553B_RTMCC_DBC_SET( _reg, _val ) \
732 ( ( ( _reg ) & ~GR1553B_RTMCC_DBC_MASK ) | \
733 ( ( ( _val ) << GR1553B_RTMCC_DBC_SHIFT ) & \
734 GR1553B_RTMCC_DBC_MASK ) )
735#define GR1553B_RTMCC_DBC( _val ) \
736 ( ( ( _val ) << GR1553B_RTMCC_DBC_SHIFT ) & \
737 GR1553B_RTMCC_DBC_MASK )
738
739#define GR1553B_RTMCC_TBW_SHIFT 14
740#define GR1553B_RTMCC_TBW_MASK 0xc000U
741#define GR1553B_RTMCC_TBW_GET( _reg ) \
742 ( ( ( _reg ) & GR1553B_RTMCC_TBW_MASK ) >> \
743 GR1553B_RTMCC_TBW_SHIFT )
744#define GR1553B_RTMCC_TBW_SET( _reg, _val ) \
745 ( ( ( _reg ) & ~GR1553B_RTMCC_TBW_MASK ) | \
746 ( ( ( _val ) << GR1553B_RTMCC_TBW_SHIFT ) & \
747 GR1553B_RTMCC_TBW_MASK ) )
748#define GR1553B_RTMCC_TBW( _val ) \
749 ( ( ( _val ) << GR1553B_RTMCC_TBW_SHIFT ) & \
750 GR1553B_RTMCC_TBW_MASK )
751
752#define GR1553B_RTMCC_TVW_SHIFT 12
753#define GR1553B_RTMCC_TVW_MASK 0x3000U
754#define GR1553B_RTMCC_TVW_GET( _reg ) \
755 ( ( ( _reg ) & GR1553B_RTMCC_TVW_MASK ) >> \
756 GR1553B_RTMCC_TVW_SHIFT )
757#define GR1553B_RTMCC_TVW_SET( _reg, _val ) \
758 ( ( ( _reg ) & ~GR1553B_RTMCC_TVW_MASK ) | \
759 ( ( ( _val ) << GR1553B_RTMCC_TVW_SHIFT ) & \
760 GR1553B_RTMCC_TVW_MASK ) )
761#define GR1553B_RTMCC_TVW( _val ) \
762 ( ( ( _val ) << GR1553B_RTMCC_TVW_SHIFT ) & \
763 GR1553B_RTMCC_TVW_MASK )
764
765#define GR1553B_RTMCC_TSB_SHIFT 10
766#define GR1553B_RTMCC_TSB_MASK 0xc00U
767#define GR1553B_RTMCC_TSB_GET( _reg ) \
768 ( ( ( _reg ) & GR1553B_RTMCC_TSB_MASK ) >> \
769 GR1553B_RTMCC_TSB_SHIFT )
770#define GR1553B_RTMCC_TSB_SET( _reg, _val ) \
771 ( ( ( _reg ) & ~GR1553B_RTMCC_TSB_MASK ) | \
772 ( ( ( _val ) << GR1553B_RTMCC_TSB_SHIFT ) & \
773 GR1553B_RTMCC_TSB_MASK ) )
774#define GR1553B_RTMCC_TSB( _val ) \
775 ( ( ( _val ) << GR1553B_RTMCC_TSB_SHIFT ) & \
776 GR1553B_RTMCC_TSB_MASK )
777
778#define GR1553B_RTMCC_TS_SHIFT 8
779#define GR1553B_RTMCC_TS_MASK 0x300U
780#define GR1553B_RTMCC_TS_GET( _reg ) \
781 ( ( ( _reg ) & GR1553B_RTMCC_TS_MASK ) >> \
782 GR1553B_RTMCC_TS_SHIFT )
783#define GR1553B_RTMCC_TS_SET( _reg, _val ) \
784 ( ( ( _reg ) & ~GR1553B_RTMCC_TS_MASK ) | \
785 ( ( ( _val ) << GR1553B_RTMCC_TS_SHIFT ) & \
786 GR1553B_RTMCC_TS_MASK ) )
787#define GR1553B_RTMCC_TS( _val ) \
788 ( ( ( _val ) << GR1553B_RTMCC_TS_SHIFT ) & \
789 GR1553B_RTMCC_TS_MASK )
790
791#define GR1553B_RTMCC_SDB_SHIFT 6
792#define GR1553B_RTMCC_SDB_MASK 0xc0U
793#define GR1553B_RTMCC_SDB_GET( _reg ) \
794 ( ( ( _reg ) & GR1553B_RTMCC_SDB_MASK ) >> \
795 GR1553B_RTMCC_SDB_SHIFT )
796#define GR1553B_RTMCC_SDB_SET( _reg, _val ) \
797 ( ( ( _reg ) & ~GR1553B_RTMCC_SDB_MASK ) | \
798 ( ( ( _val ) << GR1553B_RTMCC_SDB_SHIFT ) & \
799 GR1553B_RTMCC_SDB_MASK ) )
800#define GR1553B_RTMCC_SDB( _val ) \
801 ( ( ( _val ) << GR1553B_RTMCC_SDB_SHIFT ) & \
802 GR1553B_RTMCC_SDB_MASK )
803
804#define GR1553B_RTMCC_SD_SHIFT 4
805#define GR1553B_RTMCC_SD_MASK 0x30U
806#define GR1553B_RTMCC_SD_GET( _reg ) \
807 ( ( ( _reg ) & GR1553B_RTMCC_SD_MASK ) >> \
808 GR1553B_RTMCC_SD_SHIFT )
809#define GR1553B_RTMCC_SD_SET( _reg, _val ) \
810 ( ( ( _reg ) & ~GR1553B_RTMCC_SD_MASK ) | \
811 ( ( ( _val ) << GR1553B_RTMCC_SD_SHIFT ) & \
812 GR1553B_RTMCC_SD_MASK ) )
813#define GR1553B_RTMCC_SD( _val ) \
814 ( ( ( _val ) << GR1553B_RTMCC_SD_SHIFT ) & \
815 GR1553B_RTMCC_SD_MASK )
816
817#define GR1553B_RTMCC_SB_SHIFT 2
818#define GR1553B_RTMCC_SB_MASK 0xcU
819#define GR1553B_RTMCC_SB_GET( _reg ) \
820 ( ( ( _reg ) & GR1553B_RTMCC_SB_MASK ) >> \
821 GR1553B_RTMCC_SB_SHIFT )
822#define GR1553B_RTMCC_SB_SET( _reg, _val ) \
823 ( ( ( _reg ) & ~GR1553B_RTMCC_SB_MASK ) | \
824 ( ( ( _val ) << GR1553B_RTMCC_SB_SHIFT ) & \
825 GR1553B_RTMCC_SB_MASK ) )
826#define GR1553B_RTMCC_SB( _val ) \
827 ( ( ( _val ) << GR1553B_RTMCC_SB_SHIFT ) & \
828 GR1553B_RTMCC_SB_MASK )
829
830#define GR1553B_RTMCC_S_SHIFT 0
831#define GR1553B_RTMCC_S_MASK 0x3U
832#define GR1553B_RTMCC_S_GET( _reg ) \
833 ( ( ( _reg ) & GR1553B_RTMCC_S_MASK ) >> \
834 GR1553B_RTMCC_S_SHIFT )
835#define GR1553B_RTMCC_S_SET( _reg, _val ) \
836 ( ( ( _reg ) & ~GR1553B_RTMCC_S_MASK ) | \
837 ( ( ( _val ) << GR1553B_RTMCC_S_SHIFT ) & \
838 GR1553B_RTMCC_S_MASK ) )
839#define GR1553B_RTMCC_S( _val ) \
840 ( ( ( _val ) << GR1553B_RTMCC_S_SHIFT ) & \
841 GR1553B_RTMCC_S_MASK )
842
854#define GR1553B_RTTTC_TRES_SHIFT 16
855#define GR1553B_RTTTC_TRES_MASK 0xffff0000U
856#define GR1553B_RTTTC_TRES_GET( _reg ) \
857 ( ( ( _reg ) & GR1553B_RTTTC_TRES_MASK ) >> \
858 GR1553B_RTTTC_TRES_SHIFT )
859#define GR1553B_RTTTC_TRES_SET( _reg, _val ) \
860 ( ( ( _reg ) & ~GR1553B_RTTTC_TRES_MASK ) | \
861 ( ( ( _val ) << GR1553B_RTTTC_TRES_SHIFT ) & \
862 GR1553B_RTTTC_TRES_MASK ) )
863#define GR1553B_RTTTC_TRES( _val ) \
864 ( ( ( _val ) << GR1553B_RTTTC_TRES_SHIFT ) & \
865 GR1553B_RTTTC_TRES_MASK )
866
867#define GR1553B_RTTTC_TVAL_SHIFT 0
868#define GR1553B_RTTTC_TVAL_MASK 0xffffU
869#define GR1553B_RTTTC_TVAL_GET( _reg ) \
870 ( ( ( _reg ) & GR1553B_RTTTC_TVAL_MASK ) >> \
871 GR1553B_RTTTC_TVAL_SHIFT )
872#define GR1553B_RTTTC_TVAL_SET( _reg, _val ) \
873 ( ( ( _reg ) & ~GR1553B_RTTTC_TVAL_MASK ) | \
874 ( ( ( _val ) << GR1553B_RTTTC_TVAL_SHIFT ) & \
875 GR1553B_RTTTC_TVAL_MASK ) )
876#define GR1553B_RTTTC_TVAL( _val ) \
877 ( ( ( _val ) << GR1553B_RTTTC_TVAL_SHIFT ) & \
878 GR1553B_RTTTC_TVAL_MASK )
879
891#define GR1553B_RTELM_MASK_SHIFT 0
892#define GR1553B_RTELM_MASK_MASK 0xffffffffU
893#define GR1553B_RTELM_MASK_GET( _reg ) \
894 ( ( ( _reg ) & GR1553B_RTELM_MASK_MASK ) >> \
895 GR1553B_RTELM_MASK_SHIFT )
896#define GR1553B_RTELM_MASK_SET( _reg, _val ) \
897 ( ( ( _reg ) & ~GR1553B_RTELM_MASK_MASK ) | \
898 ( ( ( _val ) << GR1553B_RTELM_MASK_SHIFT ) & \
899 GR1553B_RTELM_MASK_MASK ) )
900#define GR1553B_RTELM_MASK( _val ) \
901 ( ( ( _val ) << GR1553B_RTELM_MASK_SHIFT ) & \
902 GR1553B_RTELM_MASK_MASK )
903
915#define GR1553B_RTELP_POINTER_SHIFT 0
916#define GR1553B_RTELP_POINTER_MASK 0xffffffffU
917#define GR1553B_RTELP_POINTER_GET( _reg ) \
918 ( ( ( _reg ) & GR1553B_RTELP_POINTER_MASK ) >> \
919 GR1553B_RTELP_POINTER_SHIFT )
920#define GR1553B_RTELP_POINTER_SET( _reg, _val ) \
921 ( ( ( _reg ) & ~GR1553B_RTELP_POINTER_MASK ) | \
922 ( ( ( _val ) << GR1553B_RTELP_POINTER_SHIFT ) & \
923 GR1553B_RTELP_POINTER_MASK ) )
924#define GR1553B_RTELP_POINTER( _val ) \
925 ( ( ( _val ) << GR1553B_RTELP_POINTER_SHIFT ) & \
926 GR1553B_RTELP_POINTER_MASK )
927
939#define GR1553B_RTELIP_POINTER_SHIFT 0
940#define GR1553B_RTELIP_POINTER_MASK 0xffffffffU
941#define GR1553B_RTELIP_POINTER_GET( _reg ) \
942 ( ( ( _reg ) & GR1553B_RTELIP_POINTER_MASK ) >> \
943 GR1553B_RTELIP_POINTER_SHIFT )
944#define GR1553B_RTELIP_POINTER_SET( _reg, _val ) \
945 ( ( ( _reg ) & ~GR1553B_RTELIP_POINTER_MASK ) | \
946 ( ( ( _val ) << GR1553B_RTELIP_POINTER_SHIFT ) & \
947 GR1553B_RTELIP_POINTER_MASK ) )
948#define GR1553B_RTELIP_POINTER( _val ) \
949 ( ( ( _val ) << GR1553B_RTELIP_POINTER_SHIFT ) & \
950 GR1553B_RTELIP_POINTER_MASK )
951
962#define GR1553B_BMS_BMSUP 0x80000000U
963
964#define GR1553B_BMS_KEYEN 0x40000000U
965
976#define GR1553B_BMC_BMKEY_SHIFT 16
977#define GR1553B_BMC_BMKEY_MASK 0xffff0000U
978#define GR1553B_BMC_BMKEY_GET( _reg ) \
979 ( ( ( _reg ) & GR1553B_BMC_BMKEY_MASK ) >> \
980 GR1553B_BMC_BMKEY_SHIFT )
981#define GR1553B_BMC_BMKEY_SET( _reg, _val ) \
982 ( ( ( _reg ) & ~GR1553B_BMC_BMKEY_MASK ) | \
983 ( ( ( _val ) << GR1553B_BMC_BMKEY_SHIFT ) & \
984 GR1553B_BMC_BMKEY_MASK ) )
985#define GR1553B_BMC_BMKEY( _val ) \
986 ( ( ( _val ) << GR1553B_BMC_BMKEY_SHIFT ) & \
987 GR1553B_BMC_BMKEY_MASK )
988
989#define GR1553B_BMC_WRSTP 0x20U
990
991#define GR1553B_BMC_EXST 0x10U
992
993#define GR1553B_BMC_IMCL 0x8U
994
995#define GR1553B_BMC_UDWL 0x4U
996
997#define GR1553B_BMC_MANL 0x2U
998
999#define GR1553B_BMC_BMEN 0x1U
1000
1012#define GR1553B_BMRTAF_MASK_SHIFT 0
1013#define GR1553B_BMRTAF_MASK_MASK 0xffffffffU
1014#define GR1553B_BMRTAF_MASK_GET( _reg ) \
1015 ( ( ( _reg ) & GR1553B_BMRTAF_MASK_MASK ) >> \
1016 GR1553B_BMRTAF_MASK_SHIFT )
1017#define GR1553B_BMRTAF_MASK_SET( _reg, _val ) \
1018 ( ( ( _reg ) & ~GR1553B_BMRTAF_MASK_MASK ) | \
1019 ( ( ( _val ) << GR1553B_BMRTAF_MASK_SHIFT ) & \
1020 GR1553B_BMRTAF_MASK_MASK ) )
1021#define GR1553B_BMRTAF_MASK( _val ) \
1022 ( ( ( _val ) << GR1553B_BMRTAF_MASK_SHIFT ) & \
1023 GR1553B_BMRTAF_MASK_MASK )
1024
1036#define GR1553B_BMRTSF_MASK_SHIFT 0
1037#define GR1553B_BMRTSF_MASK_MASK 0xffffffffU
1038#define GR1553B_BMRTSF_MASK_GET( _reg ) \
1039 ( ( ( _reg ) & GR1553B_BMRTSF_MASK_MASK ) >> \
1040 GR1553B_BMRTSF_MASK_SHIFT )
1041#define GR1553B_BMRTSF_MASK_SET( _reg, _val ) \
1042 ( ( ( _reg ) & ~GR1553B_BMRTSF_MASK_MASK ) | \
1043 ( ( ( _val ) << GR1553B_BMRTSF_MASK_SHIFT ) & \
1044 GR1553B_BMRTSF_MASK_MASK ) )
1045#define GR1553B_BMRTSF_MASK( _val ) \
1046 ( ( ( _val ) << GR1553B_BMRTSF_MASK_SHIFT ) & \
1047 GR1553B_BMRTSF_MASK_MASK )
1048
1060#define GR1553B_BMRTMC_STSB 0x40000U
1061
1062#define GR1553B_BMRTMC_STS 0x20000U
1063
1064#define GR1553B_BMRTMC_TLC 0x10000U
1065
1066#define GR1553B_BMRTMC_TSW 0x8000U
1067
1068#define GR1553B_BMRTMC_RRTB 0x4000U
1069
1070#define GR1553B_BMRTMC_RRT 0x2000U
1071
1072#define GR1553B_BMRTMC_ITFB 0x1000U
1073
1074#define GR1553B_BMRTMC_ITF 0x800U
1075
1076#define GR1553B_BMRTMC_ISTB 0x400U
1077
1078#define GR1553B_BMRTMC_IST 0x200U
1079
1080#define GR1553B_BMRTMC_DBC 0x100U
1081
1082#define GR1553B_BMRTMC_TBW 0x80U
1083
1084#define GR1553B_BMRTMC_TVW 0x40U
1085
1086#define GR1553B_BMRTMC_TSB 0x20U
1087
1088#define GR1553B_BMRTMC_TS 0x10U
1089
1090#define GR1553B_BMRTMC_SDB 0x8U
1091
1092#define GR1553B_BMRTMC_SD 0x4U
1093
1094#define GR1553B_BMRTMC_SB 0x2U
1095
1096#define GR1553B_BMRTMC_S 0x1U
1097
1108#define GR1553B_BMLBS_START_SHIFT 0
1109#define GR1553B_BMLBS_START_MASK 0xffffffffU
1110#define GR1553B_BMLBS_START_GET( _reg ) \
1111 ( ( ( _reg ) & GR1553B_BMLBS_START_MASK ) >> \
1112 GR1553B_BMLBS_START_SHIFT )
1113#define GR1553B_BMLBS_START_SET( _reg, _val ) \
1114 ( ( ( _reg ) & ~GR1553B_BMLBS_START_MASK ) | \
1115 ( ( ( _val ) << GR1553B_BMLBS_START_SHIFT ) & \
1116 GR1553B_BMLBS_START_MASK ) )
1117#define GR1553B_BMLBS_START( _val ) \
1118 ( ( ( _val ) << GR1553B_BMLBS_START_SHIFT ) & \
1119 GR1553B_BMLBS_START_MASK )
1120
1131#define GR1553B_BMLBE_END_SHIFT 0
1132#define GR1553B_BMLBE_END_MASK 0xffffffffU
1133#define GR1553B_BMLBE_END_GET( _reg ) \
1134 ( ( ( _reg ) & GR1553B_BMLBE_END_MASK ) >> \
1135 GR1553B_BMLBE_END_SHIFT )
1136#define GR1553B_BMLBE_END_SET( _reg, _val ) \
1137 ( ( ( _reg ) & ~GR1553B_BMLBE_END_MASK ) | \
1138 ( ( ( _val ) << GR1553B_BMLBE_END_SHIFT ) & \
1139 GR1553B_BMLBE_END_MASK ) )
1140#define GR1553B_BMLBE_END( _val ) \
1141 ( ( ( _val ) << GR1553B_BMLBE_END_SHIFT ) & \
1142 GR1553B_BMLBE_END_MASK )
1143
1154#define GR1553B_BMLBP_POSITION_SHIFT 0
1155#define GR1553B_BMLBP_POSITION_MASK 0xffffffffU
1156#define GR1553B_BMLBP_POSITION_GET( _reg ) \
1157 ( ( ( _reg ) & GR1553B_BMLBP_POSITION_MASK ) >> \
1158 GR1553B_BMLBP_POSITION_SHIFT )
1159#define GR1553B_BMLBP_POSITION_SET( _reg, _val ) \
1160 ( ( ( _reg ) & ~GR1553B_BMLBP_POSITION_MASK ) | \
1161 ( ( ( _val ) << GR1553B_BMLBP_POSITION_SHIFT ) & \
1162 GR1553B_BMLBP_POSITION_MASK ) )
1163#define GR1553B_BMLBP_POSITION( _val ) \
1164 ( ( ( _val ) << GR1553B_BMLBP_POSITION_SHIFT ) & \
1165 GR1553B_BMLBP_POSITION_MASK )
1166
1178#define GR1553B_BMTTC_TRES_SHIFT 24
1179#define GR1553B_BMTTC_TRES_MASK 0xff000000U
1180#define GR1553B_BMTTC_TRES_GET( _reg ) \
1181 ( ( ( _reg ) & GR1553B_BMTTC_TRES_MASK ) >> \
1182 GR1553B_BMTTC_TRES_SHIFT )
1183#define GR1553B_BMTTC_TRES_SET( _reg, _val ) \
1184 ( ( ( _reg ) & ~GR1553B_BMTTC_TRES_MASK ) | \
1185 ( ( ( _val ) << GR1553B_BMTTC_TRES_SHIFT ) & \
1186 GR1553B_BMTTC_TRES_MASK ) )
1187#define GR1553B_BMTTC_TRES( _val ) \
1188 ( ( ( _val ) << GR1553B_BMTTC_TRES_SHIFT ) & \
1189 GR1553B_BMTTC_TRES_MASK )
1190
1191#define GR1553B_BMTTC_TVAL_SHIFT 0
1192#define GR1553B_BMTTC_TVAL_MASK 0xffffffU
1193#define GR1553B_BMTTC_TVAL_GET( _reg ) \
1194 ( ( ( _reg ) & GR1553B_BMTTC_TVAL_MASK ) >> \
1195 GR1553B_BMTTC_TVAL_SHIFT )
1196#define GR1553B_BMTTC_TVAL_SET( _reg, _val ) \
1197 ( ( ( _reg ) & ~GR1553B_BMTTC_TVAL_MASK ) | \
1198 ( ( ( _val ) << GR1553B_BMTTC_TVAL_SHIFT ) & \
1199 GR1553B_BMTTC_TVAL_MASK ) )
1200#define GR1553B_BMTTC_TVAL( _val ) \
1201 ( ( ( _val ) << GR1553B_BMTTC_TVAL_SHIFT ) & \
1202 GR1553B_BMTTC_TVAL_MASK )
1203
1209typedef struct gr1553b {
1213 uint32_t irq;
1214
1218 uint32_t irqe;
1219
1220 uint32_t reserved_8_10[ 2 ];
1221
1225 uint32_t hc;
1226
1227 uint32_t reserved_14_40[ 11 ];
1228
1232 uint32_t bcsc;
1233
1237 uint32_t bca;
1238
1242 uint32_t bctnp;
1243
1247 uint32_t bcanp;
1248
1252 uint32_t bct;
1253
1254 uint32_t reserved_54_58;
1255
1259 uint32_t bcrp;
1260
1264 uint32_t bcbs;
1265
1266 uint32_t reserved_60_68[ 2 ];
1267
1271 uint32_t bctcp;
1272
1276 uint32_t bcacp;
1277
1278 uint32_t reserved_70_80[ 4 ];
1279
1283 uint32_t rts;
1284
1288 uint32_t rtc;
1289
1293 uint32_t rtbs;
1294
1298 uint32_t rtsw;
1299
1303 uint32_t rtsy;
1304
1308 uint32_t rtstba;
1309
1313 uint32_t rtmcc;
1314
1315 uint32_t reserved_9c_a4[ 2 ];
1316
1320 uint32_t rtttc;
1321
1322 uint32_t reserved_a8_ac;
1323
1327 uint32_t rtelm;
1328
1332 uint32_t rtelp;
1333
1337 uint32_t rtelip;
1338
1339 uint32_t reserved_b8_c0[ 2 ];
1340
1344 uint32_t bms;
1345
1349 uint32_t bmc;
1350
1354 uint32_t bmrtaf;
1355
1359 uint32_t bmrtsf;
1360
1364 uint32_t bmrtmc;
1365
1369 uint32_t bmlbs;
1370
1374 uint32_t bmlbe;
1375
1379 uint32_t bmlbp;
1380
1384 uint32_t bmttc;
1385} gr1553b;
1386
1389#ifdef __cplusplus
1390}
1391#endif
1392
1393#endif /* _GRLIB_GR1553B_REGS_H */
gr1553b
This structure defines the GR1553B register block memory map.
Definition: gr1553b-regs.h:1209
gr1553b::rtsw
uint32_t rtsw
See GR1553B RT Status words register (RTSW).
Definition: gr1553b-regs.h:1298
gr1553b::rtttc
uint32_t rtttc
See GR1553B RT Time tag control register (RTTTC).
Definition: gr1553b-regs.h:1320
gr1553b::bct
uint32_t bct
See GR1553B BC Timer register (BCT).
Definition: gr1553b-regs.h:1252
gr1553b::irq
uint32_t irq
See GR1553B IRQ Register (IRQ).
Definition: gr1553b-regs.h:1213
gr1553b::bcanp
uint32_t bcanp
See GR1553B BC Asynchronous list next pointer register (BCANP).
Definition: gr1553b-regs.h:1247
gr1553b::bmttc
uint32_t bmttc
See GR1553B BM Time tag control register (BMTTC).
Definition: gr1553b-regs.h:1384
gr1553b::bmrtmc
uint32_t bmrtmc
See GR1553B BM RT Mode code filter register (BMRTMC).
Definition: gr1553b-regs.h:1364
gr1553b::bmrtsf
uint32_t bmrtsf
See GR1553B BM RT Subaddress filter register (BMRTSF).
Definition: gr1553b-regs.h:1359
gr1553b::rtelip
uint32_t rtelip
See GR1553B RT Event Log interrupt position register (RTELIP).
Definition: gr1553b-regs.h:1337
gr1553b::rtmcc
uint32_t rtmcc
See GR1553B RT Mode code control register (RTMCC).
Definition: gr1553b-regs.h:1313
gr1553b::rtelp
uint32_t rtelp
See GR1553B RT Event log position register (RTELP).
Definition: gr1553b-regs.h:1332
gr1553b::bcacp
uint32_t bcacp
See GR1553B BC Asynchronous list current slot pointer (BCACP).
Definition: gr1553b-regs.h:1276
gr1553b::bctcp
uint32_t bctcp
See GR1553B BC Transfer list current slot pointer (BCTCP).
Definition: gr1553b-regs.h:1271
gr1553b::rtc
uint32_t rtc
See GR1553B RT Config register (RTC).
Definition: gr1553b-regs.h:1288
gr1553b::bmrtaf
uint32_t bmrtaf
See GR1553B BM RT Address filter register (BMRTAF).
Definition: gr1553b-regs.h:1354
gr1553b::bcrp
uint32_t bcrp
See GR1553B BC Transfer-triggered IRQ ring position register (BCRP).
Definition: gr1553b-regs.h:1259
gr1553b::irqe
uint32_t irqe
See GR1553B IRQ Enable Register (IRQE).
Definition: gr1553b-regs.h:1218
gr1553b::rtelm
uint32_t rtelm
See GR1553B RT Event log size mask register (RTELM).
Definition: gr1553b-regs.h:1327
gr1553b::rts
uint32_t rts
See GR1553B RT Status register (RTS).
Definition: gr1553b-regs.h:1283
gr1553b::bcbs
uint32_t bcbs
See GR1553B BC per-RT Bus swap register (BCBS).
Definition: gr1553b-regs.h:1264
gr1553b::bms
uint32_t bms
See GR1553B BM Status register (BMS).
Definition: gr1553b-regs.h:1344
gr1553b::bca
uint32_t bca
See GR1553B BC Action Register (BCA).
Definition: gr1553b-regs.h:1237
gr1553b::rtbs
uint32_t rtbs
See GR1553B RT Bus status register (RTBS).
Definition: gr1553b-regs.h:1293
gr1553b::bctnp
uint32_t bctnp
See GR1553B BC Transfer list next pointer register (BCTNP).
Definition: gr1553b-regs.h:1242
gr1553b::bmlbe
uint32_t bmlbe
See GR1553B BM Log buffer end (BMLBE).
Definition: gr1553b-regs.h:1374
gr1553b::rtstba
uint32_t rtstba
See GR1553B RT Subaddress table base address register (RTSTBA).
Definition: gr1553b-regs.h:1308
gr1553b::hc
uint32_t hc
See GR1553B Hardware Configuration Register (HC).
Definition: gr1553b-regs.h:1225
gr1553b::bcsc
uint32_t bcsc
See GR1553B BC Status and Config Register (BCSC).
Definition: gr1553b-regs.h:1232
gr1553b::rtsy
uint32_t rtsy
See GR1553B RT Sync register (RTSY).
Definition: gr1553b-regs.h:1303
gr1553b::bmc
uint32_t bmc
See GR1553B BM Control register (BMC).
Definition: gr1553b-regs.h:1349
gr1553b::bmlbs
uint32_t bmlbs
See GR1553B BM Log buffer start (BMLBS).
Definition: gr1553b-regs.h:1369
gr1553b::bmlbp
uint32_t bmlbp
See GR1553B BM Log buffer position (BMLBP).
Definition: gr1553b-regs.h:1379
Generated by doxygen 1.9.6