fsl_usdhc.h

/*
 * Copyright (c) 2016, Freescale Semiconductor, Inc.
 * Copyright 2016-2021 NXP
 * All rights reserved.
 *
 * SPDX-License-Identifier: BSD-3-Clause
 */
#ifndef _FSL_USDHC_H_
#define _FSL_USDHC_H_
 
#include "fsl_common.h"
 
/******************************************************************************
 * Definitions.
 *****************************************************************************/
 
#define FSL_USDHC_DRIVER_VERSION (MAKE_VERSION(2U, 8U, 2U))
#define USDHC_MAX_BLOCK_COUNT (USDHC_BLK_ATT_BLKCNT_MASK >> USDHC_BLK_ATT_BLKCNT_SHIFT)
 
#ifndef FSL_USDHC_ENABLE_SCATTER_GATHER_TRANSFER
#define FSL_USDHC_ENABLE_SCATTER_GATHER_TRANSFER 0U
#endif
 
enum
{
    kStatus_USDHC_BusyTransferring            = MAKE_STATUS(kStatusGroup_USDHC, 0U),  
    kStatus_USDHC_PrepareAdmaDescriptorFailed = MAKE_STATUS(kStatusGroup_USDHC, 1U),  
    kStatus_USDHC_SendCommandFailed           = MAKE_STATUS(kStatusGroup_USDHC, 2U),  
    kStatus_USDHC_TransferDataFailed          = MAKE_STATUS(kStatusGroup_USDHC, 3U),  
    kStatus_USDHC_DMADataAddrNotAlign         = MAKE_STATUS(kStatusGroup_USDHC, 4U),  
    kStatus_USDHC_ReTuningRequest             = MAKE_STATUS(kStatusGroup_USDHC, 5U),  
    kStatus_USDHC_TuningError                 = MAKE_STATUS(kStatusGroup_USDHC, 6U),  
    kStatus_USDHC_NotSupport                  = MAKE_STATUS(kStatusGroup_USDHC, 7U),  
    kStatus_USDHC_TransferDataComplete        = MAKE_STATUS(kStatusGroup_USDHC, 8U),  
    kStatus_USDHC_SendCommandSuccess          = MAKE_STATUS(kStatusGroup_USDHC, 9U),  
    kStatus_USDHC_TransferDMAComplete         = MAKE_STATUS(kStatusGroup_USDHC, 10U), 
};
 
enum
{
    kUSDHC_SupportAdmaFlag          = USDHC_HOST_CTRL_CAP_ADMAS_MASK, 
    kUSDHC_SupportHighSpeedFlag     = USDHC_HOST_CTRL_CAP_HSS_MASK,   
    kUSDHC_SupportDmaFlag           = USDHC_HOST_CTRL_CAP_DMAS_MASK,  
    kUSDHC_SupportSuspendResumeFlag = USDHC_HOST_CTRL_CAP_SRS_MASK,   
    kUSDHC_SupportV330Flag          = USDHC_HOST_CTRL_CAP_VS33_MASK,  
    kUSDHC_SupportV300Flag          = USDHC_HOST_CTRL_CAP_VS30_MASK,  
    kUSDHC_SupportV180Flag          = USDHC_HOST_CTRL_CAP_VS18_MASK,  
    kUSDHC_Support4BitFlag          = (USDHC_HOST_CTRL_CAP_MBL_SHIFT << 0U),
    kUSDHC_Support8BitFlag = (USDHC_HOST_CTRL_CAP_MBL_SHIFT << 1U),
    kUSDHC_SupportDDR50Flag = USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK,
#if defined(FSL_FEATURE_USDHC_HAS_SDR104_MODE) && (!FSL_FEATURE_USDHC_HAS_SDR104_MODE)
    kUSDHC_SupportSDR104Flag = 0, 
#else
    kUSDHC_SupportSDR104Flag   = USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK, 
#endif
#if defined(FSL_FEATURE_USDHC_HAS_SDR50_MODE) && (!FSL_FEATURE_USDHC_HAS_SDR50_MODE)
    kUSDHC_SupportSDR50Flag = 0U, 
#else
    kUSDHC_SupportSDR50Flag    = USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK,  
#endif
};
 
enum
{
    kUSDHC_WakeupEventOnCardInt    = USDHC_PROT_CTRL_WECINT_MASK, 
    kUSDHC_WakeupEventOnCardInsert = USDHC_PROT_CTRL_WECINS_MASK, 
    kUSDHC_WakeupEventOnCardRemove = USDHC_PROT_CTRL_WECRM_MASK,  
    kUSDHC_WakeupEventsAll =
        (kUSDHC_WakeupEventOnCardInt | kUSDHC_WakeupEventOnCardInsert | kUSDHC_WakeupEventOnCardRemove),
};
 
enum
{
    kUSDHC_ResetAll     = USDHC_SYS_CTRL_RSTA_MASK, 
    kUSDHC_ResetCommand = USDHC_SYS_CTRL_RSTC_MASK, 
    kUSDHC_ResetData    = USDHC_SYS_CTRL_RSTD_MASK, 
#if defined(FSL_FEATURE_USDHC_HAS_SDR50_MODE) && (!FSL_FEATURE_USDHC_HAS_SDR50_MODE)
    kUSDHC_ResetTuning = 0U, 
#else
    kUSDHC_ResetTuning         = USDHC_SYS_CTRL_RSTT_MASK,                
#endif
 
    kUSDHC_ResetsAll = (kUSDHC_ResetAll | kUSDHC_ResetCommand | kUSDHC_ResetData | kUSDHC_ResetTuning),
};
 
enum
{
    kUSDHC_EnableDmaFlag = USDHC_MIX_CTRL_DMAEN_MASK, 
    kUSDHC_CommandTypeSuspendFlag = USDHC_CMD_XFR_TYP_CMDTYP(1U), 
    kUSDHC_CommandTypeResumeFlag  = USDHC_CMD_XFR_TYP_CMDTYP(2U), 
    kUSDHC_CommandTypeAbortFlag   = USDHC_CMD_XFR_TYP_CMDTYP(3U), 
    kUSDHC_EnableBlockCountFlag    = USDHC_MIX_CTRL_BCEN_MASK,   
    kUSDHC_EnableAutoCommand12Flag = USDHC_MIX_CTRL_AC12EN_MASK, 
    kUSDHC_DataReadFlag            = USDHC_MIX_CTRL_DTDSEL_MASK, 
    kUSDHC_MultipleBlockFlag       = USDHC_MIX_CTRL_MSBSEL_MASK, 
    kUSDHC_EnableAutoCommand23Flag = USDHC_MIX_CTRL_AC23EN_MASK, 
    kUSDHC_ResponseLength136Flag    = USDHC_CMD_XFR_TYP_RSPTYP(1U), 
    kUSDHC_ResponseLength48Flag     = USDHC_CMD_XFR_TYP_RSPTYP(2U), 
    kUSDHC_ResponseLength48BusyFlag = USDHC_CMD_XFR_TYP_RSPTYP(3U), 
    kUSDHC_EnableCrcCheckFlag   = USDHC_CMD_XFR_TYP_CCCEN_MASK, 
    kUSDHC_EnableIndexCheckFlag = USDHC_CMD_XFR_TYP_CICEN_MASK, 
    kUSDHC_DataPresentFlag      = USDHC_CMD_XFR_TYP_DPSEL_MASK, 
};
 
enum
{
    kUSDHC_CommandInhibitFlag      = USDHC_PRES_STATE_CIHB_MASK,  
    kUSDHC_DataInhibitFlag         = USDHC_PRES_STATE_CDIHB_MASK, 
    kUSDHC_DataLineActiveFlag      = USDHC_PRES_STATE_DLA_MASK,   
    kUSDHC_SdClockStableFlag       = USDHC_PRES_STATE_SDSTB_MASK, 
    kUSDHC_WriteTransferActiveFlag = USDHC_PRES_STATE_WTA_MASK,   
    kUSDHC_ReadTransferActiveFlag  = USDHC_PRES_STATE_RTA_MASK,   
    kUSDHC_BufferWriteEnableFlag   = USDHC_PRES_STATE_BWEN_MASK,  
    kUSDHC_BufferReadEnableFlag    = USDHC_PRES_STATE_BREN_MASK,  
#if defined(FSL_FEATURE_USDHC_HAS_SDR50_MODE) && (!FSL_FEATURE_USDHC_HAS_SDR50_MODE)
    kUSDHC_DelaySettingFinishedFlag = 0U, 
    kUSDHC_ReTuningRequestFlag      = 0U, 
#else
    kUSDHC_ReTuningRequestFlag = USDHC_PRES_STATE_RTR_MASK, 
    kUSDHC_DelaySettingFinishedFlag = USDHC_PRES_STATE_TSCD_MASK, 
#endif
 
    kUSDHC_CardInsertedFlag     = USDHC_PRES_STATE_CINST_MASK, 
    kUSDHC_CommandLineLevelFlag = USDHC_PRES_STATE_CLSL_MASK,  
    kUSDHC_Data0LineLevelFlag = 1U << USDHC_PRES_STATE_DLSL_SHIFT,               
    kUSDHC_Data1LineLevelFlag = 1U << (USDHC_PRES_STATE_DLSL_SHIFT + 1U),        
    kUSDHC_Data2LineLevelFlag = 1U << (USDHC_PRES_STATE_DLSL_SHIFT + 2U),        
    kUSDHC_Data3LineLevelFlag = 1U << (USDHC_PRES_STATE_DLSL_SHIFT + 3U),        
    kUSDHC_Data4LineLevelFlag = 1U << (USDHC_PRES_STATE_DLSL_SHIFT + 4U),        
    kUSDHC_Data5LineLevelFlag = 1U << (USDHC_PRES_STATE_DLSL_SHIFT + 5U),        
    kUSDHC_Data6LineLevelFlag = 1U << (USDHC_PRES_STATE_DLSL_SHIFT + 6U),        
    kUSDHC_Data7LineLevelFlag = (int)(1U << (USDHC_PRES_STATE_DLSL_SHIFT + 7U)), 
};
 
enum
{
    kUSDHC_CommandCompleteFlag  = USDHC_INT_STATUS_CC_MASK,   
    kUSDHC_DataCompleteFlag     = USDHC_INT_STATUS_TC_MASK,   
    kUSDHC_BlockGapEventFlag    = USDHC_INT_STATUS_BGE_MASK,  
    kUSDHC_DmaCompleteFlag      = USDHC_INT_STATUS_DINT_MASK, 
    kUSDHC_BufferWriteReadyFlag = USDHC_INT_STATUS_BWR_MASK,  
    kUSDHC_BufferReadReadyFlag  = USDHC_INT_STATUS_BRR_MASK,  
    kUSDHC_CardInsertionFlag    = USDHC_INT_STATUS_CINS_MASK, 
    kUSDHC_CardRemovalFlag      = USDHC_INT_STATUS_CRM_MASK,  
    kUSDHC_CardInterruptFlag    = USDHC_INT_STATUS_CINT_MASK, 
#if defined(FSL_FEATURE_USDHC_HAS_SDR50_MODE) && (!FSL_FEATURE_USDHC_HAS_SDR50_MODE)
    kUSDHC_ReTuningEventFlag = 0U, 
    kUSDHC_TuningPassFlag    = 0U, 
    kUSDHC_TuningErrorFlag   = 0U, 
#else
    kUSDHC_ReTuningEventFlag        = USDHC_INT_STATUS_RTE_MASK,  
    kUSDHC_TuningPassFlag           = USDHC_INT_STATUS_TP_MASK,   
    kUSDHC_TuningErrorFlag          = USDHC_INT_STATUS_TNE_MASK,  
#endif
 
    kUSDHC_CommandTimeoutFlag     = USDHC_INT_STATUS_CTOE_MASK,  
    kUSDHC_CommandCrcErrorFlag    = USDHC_INT_STATUS_CCE_MASK,   
    kUSDHC_CommandEndBitErrorFlag = USDHC_INT_STATUS_CEBE_MASK,  
    kUSDHC_CommandIndexErrorFlag  = USDHC_INT_STATUS_CIE_MASK,   
    kUSDHC_DataTimeoutFlag        = USDHC_INT_STATUS_DTOE_MASK,  
    kUSDHC_DataCrcErrorFlag       = USDHC_INT_STATUS_DCE_MASK,   
    kUSDHC_DataEndBitErrorFlag    = USDHC_INT_STATUS_DEBE_MASK,  
    kUSDHC_AutoCommand12ErrorFlag = USDHC_INT_STATUS_AC12E_MASK, 
    kUSDHC_DmaErrorFlag           = USDHC_INT_STATUS_DMAE_MASK,  
    kUSDHC_CommandErrorFlag = (kUSDHC_CommandTimeoutFlag | kUSDHC_CommandCrcErrorFlag | kUSDHC_CommandEndBitErrorFlag |
                               kUSDHC_CommandIndexErrorFlag), 
    kUSDHC_DataErrorFlag    = (kUSDHC_DataTimeoutFlag | kUSDHC_DataCrcErrorFlag | kUSDHC_DataEndBitErrorFlag |
                            kUSDHC_AutoCommand12ErrorFlag),                                        
    kUSDHC_ErrorFlag        = (kUSDHC_CommandErrorFlag | kUSDHC_DataErrorFlag | kUSDHC_DmaErrorFlag), 
    kUSDHC_DataFlag = (kUSDHC_DataCompleteFlag | kUSDHC_BufferWriteReadyFlag | kUSDHC_BufferReadReadyFlag |
                       kUSDHC_DataErrorFlag), 
    kUSDHC_DataDMAFlag = (kUSDHC_DataCompleteFlag | kUSDHC_DataErrorFlag | kUSDHC_DmaErrorFlag), 
    kUSDHC_CommandFlag      = (kUSDHC_CommandErrorFlag | kUSDHC_CommandCompleteFlag), 
    kUSDHC_CardDetectFlag   = (kUSDHC_CardInsertionFlag | kUSDHC_CardRemovalFlag),    
    kUSDHC_SDR104TuningFlag = (kUSDHC_TuningErrorFlag | kUSDHC_TuningPassFlag | kUSDHC_ReTuningEventFlag),
    kUSDHC_AllInterruptFlags =
        (kUSDHC_BlockGapEventFlag | kUSDHC_CardInterruptFlag | kUSDHC_CommandFlag | kUSDHC_DataFlag | kUSDHC_ErrorFlag |
         kUSDHC_SDR104TuningFlag | kUSDHC_DmaCompleteFlag), 
};
 
enum
{
    kUSDHC_AutoCommand12NotExecutedFlag = USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK,    
    kUSDHC_AutoCommand12TimeoutFlag     = USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK,   
    kUSDHC_AutoCommand12EndBitErrorFlag = USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK,   
    kUSDHC_AutoCommand12CrcErrorFlag    = USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK,    
    kUSDHC_AutoCommand12IndexErrorFlag  = USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK,    
    kUSDHC_AutoCommand12NotIssuedFlag   = USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK, 
};
 
enum
{
#if defined(FSL_FEATURE_USDHC_HAS_SDR50_MODE) && (!FSL_FEATURE_USDHC_HAS_SDR50_MODE)
    kUSDHC_ExecuteTuning        = 0U, 
    kUSDHC_TuningSampleClockSel = 0U, 
#else
    kUSDHC_ExecuteTuning = USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK, 
    kUSDHC_TuningSampleClockSel =
        USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK,               
#endif
};
 
enum
{
    kUSDHC_AdmaLenghMismatchFlag   = USDHC_ADMA_ERR_STATUS_ADMALME_MASK, 
    kUSDHC_AdmaDescriptorErrorFlag = USDHC_ADMA_ERR_STATUS_ADMADCE_MASK, 
};
 
enum
{
    kUSDHC_AdmaErrorStateStopDma = 0x00U,
    kUSDHC_AdmaErrorStateFetchDescriptor = 0x01U,
    kUSDHC_AdmaErrorStateChangeAddress = 0x02U, 
    kUSDHC_AdmaErrorStateTransferData  = 0x03U,
    kUSDHC_AdmaErrorStateInvalidLength     = 0x04U, 
    kUSDHC_AdmaErrorStateInvalidDescriptor = 0x08U, 
    kUSDHC_AdmaErrorState = kUSDHC_AdmaErrorStateInvalidLength | kUSDHC_AdmaErrorStateInvalidDescriptor |
                            kUSDHC_AdmaErrorStateFetchDescriptor, 
};
 
enum
{
    kUSDHC_ForceEventAutoCommand12NotExecuted =
        USDHC_FORCE_EVENT_FEVTAC12NE_MASK, 
    kUSDHC_ForceEventAutoCommand12Timeout    = USDHC_FORCE_EVENT_FEVTAC12TOE_MASK,  
    kUSDHC_ForceEventAutoCommand12CrcError   = USDHC_FORCE_EVENT_FEVTAC12CE_MASK,   
    kUSDHC_ForceEventEndBitError             = USDHC_FORCE_EVENT_FEVTAC12EBE_MASK,  
    kUSDHC_ForceEventAutoCommand12IndexError = USDHC_FORCE_EVENT_FEVTAC12IE_MASK,   
    kUSDHC_ForceEventAutoCommand12NotIssued = USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK, 
    kUSDHC_ForceEventCommandTimeout         = USDHC_FORCE_EVENT_FEVTCTOE_MASK,      
    kUSDHC_ForceEventCommandCrcError        = USDHC_FORCE_EVENT_FEVTCCE_MASK,       
    kUSDHC_ForceEventCommandEndBitError     = USDHC_FORCE_EVENT_FEVTCEBE_MASK,      
    kUSDHC_ForceEventCommandIndexError      = USDHC_FORCE_EVENT_FEVTCIE_MASK,       
    kUSDHC_ForceEventDataTimeout            = USDHC_FORCE_EVENT_FEVTDTOE_MASK,      
    kUSDHC_ForceEventDataCrcError           = USDHC_FORCE_EVENT_FEVTDCE_MASK,       
    kUSDHC_ForceEventDataEndBitError        = USDHC_FORCE_EVENT_FEVTDEBE_MASK,      
    kUSDHC_ForceEventAutoCommand12Error     = USDHC_FORCE_EVENT_FEVTAC12E_MASK,     
    kUSDHC_ForceEventCardInt                = (int)USDHC_FORCE_EVENT_FEVTCINT_MASK, 
    kUSDHC_ForceEventDmaError               = USDHC_FORCE_EVENT_FEVTDMAE_MASK,      
#if defined(FSL_FEATURE_USDHC_HAS_SDR50_MODE) && (!FSL_FEATURE_USDHC_HAS_SDR50_MODE)
    kUSDHC_ForceEventTuningError = 0U, 
#else
    kUSDHC_ForceEventTuningError = USDHC_FORCE_EVENT_FEVTTNE_MASK, 
#endif
 
    kUSDHC_ForceEventsAll =
        (int)(USDHC_FORCE_EVENT_FEVTAC12NE_MASK | USDHC_FORCE_EVENT_FEVTAC12TOE_MASK |
              USDHC_FORCE_EVENT_FEVTAC12CE_MASK | USDHC_FORCE_EVENT_FEVTAC12EBE_MASK |
              USDHC_FORCE_EVENT_FEVTAC12IE_MASK | USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK |
              USDHC_FORCE_EVENT_FEVTCTOE_MASK | USDHC_FORCE_EVENT_FEVTCCE_MASK | USDHC_FORCE_EVENT_FEVTCEBE_MASK |
              USDHC_FORCE_EVENT_FEVTCIE_MASK | USDHC_FORCE_EVENT_FEVTDTOE_MASK | USDHC_FORCE_EVENT_FEVTDCE_MASK |
              USDHC_FORCE_EVENT_FEVTDEBE_MASK | USDHC_FORCE_EVENT_FEVTAC12E_MASK | USDHC_FORCE_EVENT_FEVTCINT_MASK |
              USDHC_FORCE_EVENT_FEVTDMAE_MASK | kUSDHC_ForceEventTuningError), 
};
 
typedef enum _usdhc_transfer_direction
{
    kUSDHC_TransferDirectionReceive = 1U, 
    kUSDHC_TransferDirectionSend    = 0U, 
} usdhc_transfer_direction_t;
 
typedef enum _usdhc_data_bus_width
{
    kUSDHC_DataBusWidth1Bit = 0U, 
    kUSDHC_DataBusWidth4Bit = 1U, 
    kUSDHC_DataBusWidth8Bit = 2U, 
} usdhc_data_bus_width_t;
 
typedef enum _usdhc_endian_mode
{
    kUSDHC_EndianModeBig         = 0U, 
    kUSDHC_EndianModeHalfWordBig = 1U, 
    kUSDHC_EndianModeLittle      = 2U, 
} usdhc_endian_mode_t;
 
typedef enum _usdhc_dma_mode
{
    kUSDHC_DmaModeSimple = 0U, 
    kUSDHC_DmaModeAdma1  = 1U, 
    kUSDHC_DmaModeAdma2  = 2U, 
    kUSDHC_ExternalDMA   = 3U, 
} usdhc_dma_mode_t;
 
enum
{
    kUSDHC_StopAtBlockGapFlag      = USDHC_PROT_CTRL_SABGREQ_MASK, 
    kUSDHC_ReadWaitControlFlag     = USDHC_PROT_CTRL_RWCTL_MASK,   
    kUSDHC_InterruptAtBlockGapFlag = USDHC_PROT_CTRL_IABG_MASK,    
    kUSDHC_ReadDoneNo8CLK = USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK,  
    kUSDHC_ExactBlockNumberReadFlag = USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK, 
};
 
typedef enum _usdhc_boot_mode
{
    kUSDHC_BootModeNormal      = 0U, 
    kUSDHC_BootModeAlternative = 1U, 
} usdhc_boot_mode_t;
 
typedef enum _usdhc_card_command_type
{
    kCARD_CommandTypeNormal  = 0U, 
    kCARD_CommandTypeSuspend = 1U, 
    kCARD_CommandTypeResume  = 2U, 
    kCARD_CommandTypeAbort   = 3U, 
    kCARD_CommandTypeEmpty   = 4U, 
} usdhc_card_command_type_t;
 
typedef enum _usdhc_card_response_type
{
    kCARD_ResponseTypeNone = 0U, 
    kCARD_ResponseTypeR1   = 1U, 
    kCARD_ResponseTypeR1b  = 2U, 
    kCARD_ResponseTypeR2   = 3U, 
    kCARD_ResponseTypeR3   = 4U, 
    kCARD_ResponseTypeR4   = 5U, 
    kCARD_ResponseTypeR5   = 6U, 
    kCARD_ResponseTypeR5b  = 7U, 
    kCARD_ResponseTypeR6   = 8U, 
    kCARD_ResponseTypeR7   = 9U, 
} usdhc_card_response_type_t;
 
#define USDHC_ADMA1_ADDRESS_ALIGN (4096U)
#define USDHC_ADMA1_LENGTH_ALIGN (4096U)
#define USDHC_ADMA2_ADDRESS_ALIGN (4U)
#define USDHC_ADMA2_LENGTH_ALIGN (4U)
 
/* ADMA1 descriptor table:
 * |------------------------|---------|--------------------------|
 * | Address/page field     |Reserved |         Attribute        |
 * |------------------------|---------|--------------------------|
 * |31                    12|11      6|05  |04  |03|02 |01 |00   |
 * |------------------------|---------|----|----|--|---|---|-----|
 * | address or data length | 000000  |Act2|Act1| 0|Int|End|Valid|
 * |------------------------|---------|----|----|--|---|---|-----|
 *
 * ADMA2 action table:
 * |------|------|-----------------|-------|-------------|
 * | Act2 | Act1 |     Comment     | 31-28 | 27 - 12     |
 * |------|------|-----------------|---------------------|
 * |   0  |   0  | No op           | Don't care          |
 * |------|------|-----------------|-------|-------------|
 * |   0  |   1  | Set data length |  0000 | Data Length |
 * |------|------|-----------------|-------|-------------|
 * |   1  |   0  | Transfer data   | Data address        |
 * |------|------|-----------------|---------------------|
 * |   1  |   1  | Link descriptor | Descriptor address  |
 * |------|------|-----------------|---------------------|
 */
/****************************tables below are created only for Doxygen*********************************/
#define USDHC_ADMA1_DESCRIPTOR_ADDRESS_SHIFT (12U)
#define USDHC_ADMA1_DESCRIPTOR_ADDRESS_MASK (0xFFFFFU)
#define USDHC_ADMA1_DESCRIPTOR_LENGTH_SHIFT (12U)
#define USDHC_ADMA1_DESCRIPTOR_LENGTH_MASK (0xFFFFU)
#define USDHC_ADMA1_DESCRIPTOR_MAX_LENGTH_PER_ENTRY (USDHC_ADMA1_DESCRIPTOR_LENGTH_MASK + 1U - 4096U)
 
enum
{
    kUSDHC_Adma1DescriptorValidFlag     = (1U << 0U),                        
    kUSDHC_Adma1DescriptorEndFlag       = (1U << 1U),                        
    kUSDHC_Adma1DescriptorInterrupFlag  = (1U << 2U),                        
    kUSDHC_Adma1DescriptorActivity1Flag = (1U << 4U),                        
    kUSDHC_Adma1DescriptorActivity2Flag = (1U << 5U),                        
    kUSDHC_Adma1DescriptorTypeNop       = (kUSDHC_Adma1DescriptorValidFlag), 
    kUSDHC_Adma1DescriptorTypeTransfer  = (kUSDHC_Adma1DescriptorActivity2Flag | kUSDHC_Adma1DescriptorValidFlag),
    kUSDHC_Adma1DescriptorTypeLink      = (kUSDHC_Adma1DescriptorActivity1Flag | kUSDHC_Adma1DescriptorActivity2Flag |
                                      kUSDHC_Adma1DescriptorValidFlag), 
    kUSDHC_Adma1DescriptorTypeSetLength = (kUSDHC_Adma1DescriptorActivity1Flag | kUSDHC_Adma1DescriptorValidFlag),
};
 
/* ADMA2 descriptor table:
 * |----------------|---------------|-------------|--------------------------|
 * | Address field  |     Length    | Reserved    |         Attribute        |
 * |----------------|---------------|-------------|--------------------------|
 * |63            32|31           16|15         06|05  |04  |03|02 |01 |00   |
 * |----------------|---------------|-------------|----|----|--|---|---|-----|
 * | 32-bit address | 16-bit length | 0000000000  |Act2|Act1| 0|Int|End|Valid|
 * |----------------|---------------|-------------|----|----|--|---|---|-----|
 *
 * ADMA2 action table:
 * | Act2 | Act1 |     Comment     | Operation                                                         |
 * |------|------|-----------------|-------------------------------------------------------------------|
 * |   0  |   0  | No op           | Don't care                                                        |
 * |------|------|-----------------|-------------------------------------------------------------------|
 * |   0  |   1  | Reserved        | Read this line and go to next one                                 |
 * |------|------|-----------------|-------------------------------------------------------------------|
 * |   1  |   0  | Transfer data   | Transfer data with address and length set in this descriptor line |
 * |------|------|-----------------|-------------------------------------------------------------------|
 * |   1  |   1  | Link descriptor | Link to another descriptor                                        |
 * |------|------|-----------------|-------------------------------------------------------------------|
 */
/**********************************tables below are created only for Doxygen***********************************/
#define USDHC_ADMA2_DESCRIPTOR_LENGTH_SHIFT (16U)
#define USDHC_ADMA2_DESCRIPTOR_LENGTH_MASK (0xFFFFU)
#define USDHC_ADMA2_DESCRIPTOR_MAX_LENGTH_PER_ENTRY (USDHC_ADMA2_DESCRIPTOR_LENGTH_MASK - 3U)
 
enum
{
    kUSDHC_Adma2DescriptorValidFlag     = (1U << 0U), 
    kUSDHC_Adma2DescriptorEndFlag       = (1U << 1U), 
    kUSDHC_Adma2DescriptorInterruptFlag = (1U << 2U), 
    kUSDHC_Adma2DescriptorActivity1Flag = (1U << 4U), 
    kUSDHC_Adma2DescriptorActivity2Flag = (1U << 5U), 
    kUSDHC_Adma2DescriptorTypeNop      = (kUSDHC_Adma2DescriptorValidFlag), 
    kUSDHC_Adma2DescriptorTypeReserved = (kUSDHC_Adma2DescriptorActivity1Flag | kUSDHC_Adma2DescriptorValidFlag),
    kUSDHC_Adma2DescriptorTypeTransfer = (kUSDHC_Adma2DescriptorActivity2Flag | kUSDHC_Adma2DescriptorValidFlag),
    kUSDHC_Adma2DescriptorTypeLink = (kUSDHC_Adma2DescriptorActivity1Flag | kUSDHC_Adma2DescriptorActivity2Flag |
                                      kUSDHC_Adma2DescriptorValidFlag), 
};
 
enum
{
    kUSDHC_AdmaDescriptorSingleFlag = 0U,
    kUSDHC_AdmaDescriptorMultipleFlag =
        1U, 
};
 
typedef enum _usdhc_burst_len
{
    kUSDHC_EnBurstLenForINCR         = 0x01U, 
    kUSDHC_EnBurstLenForINCR4816     = 0x02U, 
    kUSDHC_EnBurstLenForINCR4816WRAP = 0x04U, 
} usdhc_burst_len_t;
 
enum
{
    kUSDHC_TransferDataNormal        = 0U, 
    kUSDHC_TransferDataTuning        = 1U, 
    kUSDHC_TransferDataBoot          = 2U, 
    kUSDHC_TransferDataBootcontinous = 3U, 
};
 
typedef uint32_t usdhc_adma1_descriptor_t;
 
typedef struct _usdhc_adma2_descriptor
{
    uint32_t attribute;      
    const uint32_t *address; 
} usdhc_adma2_descriptor_t;
 
typedef struct _usdhc_capability
{
    uint32_t sdVersion;      
    uint32_t mmcVersion;     
    uint32_t maxBlockLength; 
    uint32_t maxBlockCount;  
    uint32_t flags;          
} usdhc_capability_t;
 
typedef struct _usdhc_boot_config
{
    uint32_t ackTimeoutCount;      
    usdhc_boot_mode_t bootMode;    
    uint32_t blockCount;           
    size_t blockSize;              
    bool enableBootAck;            
    bool enableAutoStopAtBlockGap; 
} usdhc_boot_config_t;
 
typedef struct _usdhc_config
{
    uint32_t dataTimeout;           
    usdhc_endian_mode_t endianMode; 
    uint8_t readWatermarkLevel;     
    uint8_t writeWatermarkLevel;    
#if !(defined(FSL_FEATURE_USDHC_HAS_NO_RW_BURST_LEN) && FSL_FEATURE_USDHC_HAS_NO_RW_BURST_LEN)
    uint8_t readBurstLen;  
    uint8_t writeBurstLen; 
#endif
} usdhc_config_t;
 
typedef struct _usdhc_command
{
    uint32_t index;                          
    uint32_t argument;                       
    usdhc_card_command_type_t type;          
    usdhc_card_response_type_t responseType; 
    uint32_t response[4U];                   
    uint32_t responseErrorFlags;             
    uint32_t flags;                          
} usdhc_command_t;
 
typedef struct _usdhc_adma_config
{
    usdhc_dma_mode_t dmaMode; 
#if !(defined(FSL_FEATURE_USDHC_HAS_NO_RW_BURST_LEN) && FSL_FEATURE_USDHC_HAS_NO_RW_BURST_LEN)
    usdhc_burst_len_t burstLen; 
#endif
    uint32_t *admaTable;     
    uint32_t admaTableWords; 
} usdhc_adma_config_t;
 
typedef struct _usdhc_scatter_gather_data_list
{
    uint32_t *dataAddr;
    uint32_t dataSize;
    struct _usdhc_scatter_gather_data_list *dataList;
} usdhc_scatter_gather_data_list_t;
 
typedef struct _usdhc_scatter_gather_data
{
    bool enableAutoCommand12; 
    bool enableAutoCommand23; 
    bool enableIgnoreError;   
    usdhc_transfer_direction_t dataDirection; 
    uint8_t dataType;                         
    size_t blockSize;                         
    usdhc_scatter_gather_data_list_t sgData; 
} usdhc_scatter_gather_data_t;
 
typedef struct _usdhc_scatter_gather_transfer
{
    usdhc_scatter_gather_data_t *data; 
    usdhc_command_t *command;          
} usdhc_scatter_gather_transfer_t;
 
typedef struct _usdhc_data
{
    bool enableAutoCommand12; 
    bool enableAutoCommand23; 
    bool enableIgnoreError;   
    uint8_t dataType;         
    size_t blockSize;         
    uint32_t blockCount;      
    uint32_t *rxData;         
    const uint32_t *txData;   
} usdhc_data_t;
 
typedef struct _usdhc_transfer
{
    usdhc_data_t *data;       
    usdhc_command_t *command; 
} usdhc_transfer_t;
 
typedef struct _usdhc_handle usdhc_handle_t;
 
typedef struct _usdhc_transfer_callback
{
    void (*CardInserted)(USDHC_Type *base,
                         void *userData); 
    void (*CardRemoved)(USDHC_Type *base, void *userData);   
    void (*SdioInterrupt)(USDHC_Type *base, void *userData); 
    void (*BlockGap)(USDHC_Type *base, void *userData);      
    void (*TransferComplete)(USDHC_Type *base,
                             usdhc_handle_t *handle,
                             status_t status,
                             void *userData);           
    void (*ReTuning)(USDHC_Type *base, void *userData); 
} usdhc_transfer_callback_t;
 
struct _usdhc_handle
{
#if (defined FSL_USDHC_ENABLE_SCATTER_GATHER_TRANSFER) && FSL_USDHC_ENABLE_SCATTER_GATHER_TRANSFER
    usdhc_scatter_gather_data_t *volatile data; 
#else
    usdhc_data_t *volatile data;                                   
#endif
    usdhc_command_t *volatile command; 
    volatile uint32_t transferredWords; 
    usdhc_transfer_callback_t callback; 
    void *userData;                     
};
 
typedef status_t (*usdhc_transfer_function_t)(USDHC_Type *base, usdhc_transfer_t *content);
 
typedef struct _usdhc_host
{
    USDHC_Type *base;                   
    uint32_t sourceClock_Hz;            
    usdhc_config_t config;              
    usdhc_capability_t capability;      
    usdhc_transfer_function_t transfer; 
} usdhc_host_t;
 
/*************************************************************************************************
 * API
 ************************************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif
 
void USDHC_Init(USDHC_Type *base, const usdhc_config_t *config);
 
void USDHC_Deinit(USDHC_Type *base);
 
bool USDHC_Reset(USDHC_Type *base, uint32_t mask, uint32_t timeout);
 
/* @} */
 
status_t USDHC_SetAdmaTableConfig(USDHC_Type *base,
                                  usdhc_adma_config_t *dmaConfig,
                                  usdhc_data_t *dataConfig,
                                  uint32_t flags);
 
status_t USDHC_SetInternalDmaConfig(USDHC_Type *base,
                                    usdhc_adma_config_t *dmaConfig,
                                    const uint32_t *dataAddr,
                                    bool enAutoCmd23);
 
status_t USDHC_SetADMA2Descriptor(
    uint32_t *admaTable, uint32_t admaTableWords, const uint32_t *dataBufferAddr, uint32_t dataBytes, uint32_t flags);
 
status_t USDHC_SetADMA1Descriptor(
    uint32_t *admaTable, uint32_t admaTableWords, const uint32_t *dataBufferAddr, uint32_t dataBytes, uint32_t flags);
 
static inline void USDHC_EnableInternalDMA(USDHC_Type *base, bool enable)
{
    if (enable)
    {
        base->MIX_CTRL |= USDHC_MIX_CTRL_DMAEN_MASK;
    }
    else
    {
        base->MIX_CTRL &= ~USDHC_MIX_CTRL_DMAEN_MASK;
        base->PROT_CTRL &= ~USDHC_PROT_CTRL_DMASEL_MASK;
    }
}
 
/* @} */
 
static inline void USDHC_EnableInterruptStatus(USDHC_Type *base, uint32_t mask)
{
    base->INT_STATUS_EN |= mask;
}
 
static inline void USDHC_DisableInterruptStatus(USDHC_Type *base, uint32_t mask)
{
    base->INT_STATUS_EN &= ~mask;
}
 
static inline void USDHC_EnableInterruptSignal(USDHC_Type *base, uint32_t mask)
{
    base->INT_SIGNAL_EN |= mask;
}
 
static inline void USDHC_DisableInterruptSignal(USDHC_Type *base, uint32_t mask)
{
    base->INT_SIGNAL_EN &= ~mask;
}
 
/* @} */
 
static inline uint32_t USDHC_GetEnabledInterruptStatusFlags(USDHC_Type *base)
{
    uint32_t intStatus = base->INT_STATUS;
 
    return intStatus & base->INT_SIGNAL_EN;
}
 
static inline uint32_t USDHC_GetInterruptStatusFlags(USDHC_Type *base)
{
    return base->INT_STATUS;
}
 
static inline void USDHC_ClearInterruptStatusFlags(USDHC_Type *base, uint32_t mask)
{
    base->INT_STATUS = mask;
}
 
static inline uint32_t USDHC_GetAutoCommand12ErrorStatusFlags(USDHC_Type *base)
{
    return base->AUTOCMD12_ERR_STATUS;
}
 
static inline uint32_t USDHC_GetAdmaErrorStatusFlags(USDHC_Type *base)
{
    return base->ADMA_ERR_STATUS & 0xFUL;
}
 
static inline uint32_t USDHC_GetPresentStatusFlags(USDHC_Type *base)
{
    return base->PRES_STATE;
}
 
/* @} */
 
void USDHC_GetCapability(USDHC_Type *base, usdhc_capability_t *capability);
 
static inline void USDHC_ForceClockOn(USDHC_Type *base, bool enable)
{
    if (enable)
    {
        base->VEND_SPEC |= USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK;
    }
    else
    {
        base->VEND_SPEC &= ~USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK;
    }
}
 
uint32_t USDHC_SetSdClock(USDHC_Type *base, uint32_t srcClock_Hz, uint32_t busClock_Hz);
 
bool USDHC_SetCardActive(USDHC_Type *base, uint32_t timeout);
 
static inline void USDHC_AssertHardwareReset(USDHC_Type *base, bool high)
{
    if (high)
    {
        base->SYS_CTRL |= USDHC_SYS_CTRL_IPP_RST_N_MASK;
    }
    else
    {
        base->SYS_CTRL &= ~USDHC_SYS_CTRL_IPP_RST_N_MASK;
    }
}
 
static inline void USDHC_SetDataBusWidth(USDHC_Type *base, usdhc_data_bus_width_t width)
{
    base->PROT_CTRL = ((base->PROT_CTRL & ~USDHC_PROT_CTRL_DTW_MASK) | USDHC_PROT_CTRL_DTW(width));
}
 
static inline void USDHC_WriteData(USDHC_Type *base, uint32_t data)
{
    base->DATA_BUFF_ACC_PORT = data;
}
 
static inline uint32_t USDHC_ReadData(USDHC_Type *base)
{
    return base->DATA_BUFF_ACC_PORT;
}
 
void USDHC_SendCommand(USDHC_Type *base, usdhc_command_t *command);
 
static inline void USDHC_EnableWakeupEvent(USDHC_Type *base, uint32_t mask, bool enable)
{
    if (enable)
    {
        base->PROT_CTRL |= mask;
    }
    else
    {
        base->PROT_CTRL &= ~mask;
    }
}
 
static inline void USDHC_CardDetectByData3(USDHC_Type *base, bool enable)
{
    if (enable)
    {
        base->PROT_CTRL |= USDHC_PROT_CTRL_D3CD_MASK;
    }
    else
    {
        base->PROT_CTRL &= ~USDHC_PROT_CTRL_D3CD_MASK;
    }
}
 
static inline bool USDHC_DetectCardInsert(USDHC_Type *base)
{
    return ((base->PRES_STATE & (uint32_t)kUSDHC_CardInsertedFlag) != 0UL) ? true : false;
}
 
static inline void USDHC_EnableSdioControl(USDHC_Type *base, uint32_t mask, bool enable)
{
    if (enable)
    {
        base->PROT_CTRL |= mask;
    }
    else
    {
        base->PROT_CTRL &= ~mask;
    }
}
 
static inline void USDHC_SetContinueRequest(USDHC_Type *base)
{
    base->PROT_CTRL |= USDHC_PROT_CTRL_CREQ_MASK;
}
 
static inline void USDHC_RequestStopAtBlockGap(USDHC_Type *base, bool enable)
{
    if (enable)
    {
        base->PROT_CTRL |= USDHC_PROT_CTRL_SABGREQ_MASK;
    }
    else
    {
        base->PROT_CTRL &= ~USDHC_PROT_CTRL_SABGREQ_MASK;
    }
}
 
void USDHC_SetMmcBootConfig(USDHC_Type *base, const usdhc_boot_config_t *config);
 
static inline void USDHC_EnableMmcBoot(USDHC_Type *base, bool enable)
{
    if (enable)
    {
        base->MMC_BOOT |= USDHC_MMC_BOOT_BOOT_EN_MASK;
    }
    else
    {
        base->MMC_BOOT &= ~USDHC_MMC_BOOT_BOOT_EN_MASK;
    }
}
 
static inline void USDHC_SetForceEvent(USDHC_Type *base, uint32_t mask)
{
    base->FORCE_EVENT = mask;
}
 
#if !(defined(FSL_FEATURE_USDHC_HAS_NO_VOLTAGE_SELECT) && (FSL_FEATURE_USDHC_HAS_NO_VOLTAGE_SELECT))
static inline void UDSHC_SelectVoltage(USDHC_Type *base, bool en18v)
{
    if (en18v)
    {
        base->VEND_SPEC |= USDHC_VEND_SPEC_VSELECT_MASK;
    }
    else
    {
        base->VEND_SPEC &= ~USDHC_VEND_SPEC_VSELECT_MASK;
    }
}
#endif
 
#if defined(FSL_FEATURE_USDHC_HAS_SDR50_MODE) && (FSL_FEATURE_USDHC_HAS_SDR50_MODE)
static inline bool USDHC_RequestTuningForSDR50(USDHC_Type *base)
{
    return ((base->HOST_CTRL_CAP & USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK) != 0UL) ? true : false;
}
 
static inline bool USDHC_RequestReTuning(USDHC_Type *base)
{
    return ((base->PRES_STATE & USDHC_PRES_STATE_RTR_MASK) != 0UL) ? true : false;
}
 
static inline void USDHC_EnableAutoTuning(USDHC_Type *base, bool enable)
{
    if (enable)
    {
        base->MIX_CTRL |= USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK;
    }
    else
    {
        base->MIX_CTRL &= ~USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK;
    }
}
 
#if !(defined(FSL_FEATURE_USDHC_REGISTER_HOST_CTRL_CAP_HAS_NO_RETUNING_TIME_COUNTER) && \
      FSL_FEATURE_USDHC_REGISTER_HOST_CTRL_CAP_HAS_NO_RETUNING_TIME_COUNTER)
static inline void USDHC_SetRetuningTimer(USDHC_Type *base, uint32_t counter)
{
    base->HOST_CTRL_CAP &= ~USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_MASK;
    base->HOST_CTRL_CAP |= USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING(counter);
}
#endif /* FSL_FEATURE_USDHC_REGISTER_HOST_CTRL_CAP_HAS_RETUNING_TIME_COUNTER */
 
void USDHC_EnableAutoTuningForCmdAndData(USDHC_Type *base);
 
void USDHC_EnableManualTuning(USDHC_Type *base, bool enable);
 
static inline uint32_t USDHC_GetTuningDelayStatus(USDHC_Type *base)
{
    return base->CLK_TUNE_CTRL_STATUS >> 16U;
}
 
status_t USDHC_SetTuningDelay(USDHC_Type *base, uint32_t preDelay, uint32_t outDelay, uint32_t postDelay);
 
status_t USDHC_AdjustDelayForManualTuning(USDHC_Type *base, uint32_t delay);
 
static inline void USDHC_SetStandardTuningCounter(USDHC_Type *base, uint8_t counter)
{
    base->TUNING_CTRL =
        (base->TUNING_CTRL & (~USDHC_TUNING_CTRL_TUNING_COUNTER_MASK)) | USDHC_TUNING_CTRL_TUNING_COUNTER(counter);
}
 
void USDHC_EnableStandardTuning(USDHC_Type *base, uint32_t tuningStartTap, uint32_t step, bool enable);
 
static inline uint32_t USDHC_GetExecuteStdTuningStatus(USDHC_Type *base)
{
    return (base->AUTOCMD12_ERR_STATUS & USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK);
}
 
static inline uint32_t USDHC_CheckStdTuningResult(USDHC_Type *base)
{
    return (base->AUTOCMD12_ERR_STATUS & USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK);
}
 
static inline uint32_t USDHC_CheckTuningError(USDHC_Type *base)
{
    return (base->CLK_TUNE_CTRL_STATUS &
            (USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK | USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK));
}
 
#endif
void USDHC_EnableDDRMode(USDHC_Type *base, bool enable, uint32_t nibblePos);
 
#if FSL_FEATURE_USDHC_HAS_HS400_MODE
static inline void USDHC_EnableHS400Mode(USDHC_Type *base, bool enable)
{
    if (enable)
    {
        base->MIX_CTRL |= USDHC_MIX_CTRL_HS400_MODE_MASK;
    }
    else
    {
        base->MIX_CTRL &= ~USDHC_MIX_CTRL_HS400_MODE_MASK;
    }
}
 
static inline void USDHC_ResetStrobeDLL(USDHC_Type *base)
{
    base->STROBE_DLL_CTRL |= USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_MASK;
}
 
static inline void USDHC_EnableStrobeDLL(USDHC_Type *base, bool enable)
{
    if (enable)
    {
        base->STROBE_DLL_CTRL |= USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_MASK;
    }
    else
    {
        base->STROBE_DLL_CTRL &= ~USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_MASK;
    }
}
 
void USDHC_ConfigStrobeDLL(USDHC_Type *base, uint32_t delayTarget, uint32_t updateInterval);
 
static inline void USDHC_SetStrobeDllOverride(USDHC_Type *base, uint32_t delayTaps)
{
    base->STROBE_DLL_CTRL &= (USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_MASK |
                              USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_MASK);
 
    base->STROBE_DLL_CTRL |= USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_MASK |
                             USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL(delayTaps);
}
 
static inline uint32_t USDHC_GetStrobeDLLStatus(USDHC_Type *base)
{
    return base->STROBE_DLL_STATUS;
}
 
#endif
 
void USDHC_SetDataConfig(USDHC_Type *base,
                         usdhc_transfer_direction_t dataDirection,
                         uint32_t blockCount,
                         uint32_t blockSize);
/* @} */
 
void USDHC_TransferCreateHandle(USDHC_Type *base,
                                usdhc_handle_t *handle,
                                const usdhc_transfer_callback_t *callback,
                                void *userData);
 
#if (defined FSL_USDHC_ENABLE_SCATTER_GATHER_TRANSFER) && FSL_USDHC_ENABLE_SCATTER_GATHER_TRANSFER
status_t USDHC_TransferScatterGatherADMANonBlocking(USDHC_Type *base,
                                                    usdhc_handle_t *handle,
                                                    usdhc_adma_config_t *dmaConfig,
                                                    usdhc_scatter_gather_transfer_t *transfer);
#else
status_t USDHC_TransferNonBlocking(USDHC_Type *base,
                                   usdhc_handle_t *handle,
                                   usdhc_adma_config_t *dmaConfig,
                                   usdhc_transfer_t *transfer);
#endif
 
status_t USDHC_TransferBlocking(USDHC_Type *base, usdhc_adma_config_t *dmaConfig, usdhc_transfer_t *transfer);
 
void USDHC_TransferHandleIRQ(USDHC_Type *base, usdhc_handle_t *handle);
 
/* @} */
 
#if defined(__cplusplus)
}
#endif
#endif /* _FSL_USDHC_H_*/