RTEMS 6.1-rc5
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fsl_pxp.h
1/*
2 * Copyright 2017-2022 NXP
3 * All rights reserved.
4 *
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9#ifndef _FSL_PXP_H_
10#define _FSL_PXP_H_
11
12#include "fsl_common.h"
13
14/* Compatibility macro map. */
15#if defined(PXP_AS_CTRL_ALPHA_INVERT_MASK) && (!defined(PXP_AS_CTRL_ALPHA0_INVERT_MASK))
16#define PXP_AS_CTRL_ALPHA0_INVERT_MASK PXP_AS_CTRL_ALPHA_INVERT_MASK
17#endif
18
19#if defined(PXP_AS_CTRL_ALPHA_INVERT_MASK) && (!defined(PXP_AS_CTRL_ALPHA_INVERT_MASK))
20#define PXP_AS_CTRL_ALPHA0_INVERT_MASK PXP_AS_CTRL_ALPHA_INVERT_MASK
21#endif
22
23#if defined(PXP_STAT_IRQ_MASK) && (!defined(PXP_STAT_IRQ0_MASK))
24#define PXP_STAT_IRQ0_MASK PXP_STAT_IRQ_MASK
25#endif
26
27#if defined(PXP_STAT_AXI_READ_ERROR_MASK) && (!defined(PXP_STAT_AXI_READ_ERROR_0_MASK))
28#define PXP_STAT_AXI_READ_ERROR_0_MASK PXP_STAT_AXI_READ_ERROR_MASK
29#endif
30
31#if defined(PXP_STAT_AXI_WRITE_ERROR_MASK) && (!defined(PXP_STAT_AXI_WRITE_ERROR_0_MASK))
32#define PXP_STAT_AXI_WRITE_ERROR_0_MASK PXP_STAT_AXI_WRITE_ERROR_MASK
33#endif
34
40/*******************************************************************************
41 * Definitions
42 ******************************************************************************/
43
44/* PXP global LUT table is 16K. */
45#define PXP_LUT_TABLE_BYTE (16UL * 1024UL)
46/* Intenral memory for LUT, the size is 256 bytes. */
47#define PXP_INTERNAL_RAM_LUT_BYTE (256)
48
51#define FSL_PXP_DRIVER_VERSION (MAKE_VERSION(2, 4, 1))
54/* This macto indicates whether the rotate sub module is shared by process surface and output buffer. */
55#if defined(PXP_CTRL_ROT_POS_MASK)
56#define PXP_SHARE_ROTATE 1
57#else
58#define PXP_SHARE_ROTATE 0
59#endif
60
61/* This macto indicates whether PXP needs mux the process path. */
62#if defined(PXP_DATA_PATH_CTRL0_MUX0_SEL_MASK)
63#define PXP_USE_PATH 1
64#else
65#define PXP_USE_PATH 0
66#endif
67
68#if PXP_USE_PATH
69#define PXP_PATH(mux, sel) (((mux) << 8U) | (sel))
70#define PXP_GET_MUX_FROM_PATH(path) ((path) >> 8U)
71#define PXP_GET_SEL_FROM_PATH(path) ((path)&0x03U)
72#endif /* PXP_USE_PATH */
73
76{
77 kPXP_CompleteInterruptEnable = PXP_CTRL_IRQ_ENABLE_MASK,
78 kPXP_CommandLoadInterruptEnable = PXP_CTRL_NEXT_IRQ_ENABLE_MASK,
80#if !(defined(FSL_FEATURE_PXP_HAS_NO_LUT) && FSL_FEATURE_PXP_HAS_NO_LUT)
82 PXP_CTRL_LUT_DMA_IRQ_ENABLE_MASK,
83#endif
84#if defined(FSL_FEATURE_PXP_V3) && FSL_FEATURE_PXP_V3
85 kPXP_CompressDoneInterruptEnable =
86 PXP_IRQ_MASK_COMPRESS_DONE_IRQ_EN_MASK >> 16U,
87 kPXP_InputFetchCh0InterruptEnable = PXP_IRQ_MASK_FIRST_CH0_PREFETCH_IRQ_EN_MASK
88 << 16U,
89 kPXP_InputFetchCh1InterruptEnable = PXP_IRQ_MASK_FIRST_CH1_PREFETCH_IRQ_EN_MASK
90 << 16U,
91 kPXP_InputStoreCh0InterruptEnable = PXP_IRQ_MASK_FIRST_CH0_STORE_IRQ_EN_MASK
92 << 16U,
93 kPXP_InputStoreCh1InterruptEnable = PXP_IRQ_MASK_FIRST_CH1_STORE_IRQ_EN_MASK
94 << 16U,
95 kPXP_DitherFetchCh0InterruptEnable = PXP_IRQ_MASK_DITHER_CH0_PREFETCH_IRQ_EN_MASK
96 << 16U,
97 kPXP_DitherFetchCh1InterruptEnable = PXP_IRQ_MASK_DITHER_CH1_PREFETCH_IRQ_EN_MASK
98 << 16U,
99 kPXP_DitherStoreCh0InterruptEnable = PXP_IRQ_MASK_DITHER_CH0_STORE_IRQ_EN_MASK
100 << 16U,
101 kPXP_DitherStoreCh1InterruptEnable = PXP_IRQ_MASK_DITHER_CH1_STORE_IRQ_EN_MASK
102 << 16U,
103 kPXP_WfeaStoreCh0InterruptEnable = PXP_IRQ_MASK_WFE_A_CH0_STORE_IRQ_EN_MASK
104 << 16U,
105 kPXP_WfeaStoreCh1InterruptEnable = PXP_IRQ_MASK_WFE_A_CH1_STORE_IRQ_EN_MASK
106 << 16U,
107 kPXP_WfebStoreCh0InterruptEnable = PXP_IRQ_MASK_WFE_B_CH0_STORE_IRQ_EN_MASK
108 << 16U,
109 kPXP_WfebStoreCh1InterruptEnable = PXP_IRQ_MASK_WFE_B_CH1_STORE_IRQ_EN_MASK
110 << 16U,
111 kPXP_InputStoreInterruptEnable = PXP_IRQ_MASK_FIRST_STORE_IRQ_EN_MASK << 16U,
112 kPXP_DitherStoreInterruptEnable = PXP_IRQ_MASK_DITHER_STORE_IRQ_EN_MASK
113 << 16U,
114 kPXP_WfeaStoreInterruptEnable = PXP_IRQ_MASK_WFE_A_STORE_IRQ_EN_MASK << 16U,
115 kPXP_WfebStoreInterruptEnable = PXP_IRQ_MASK_WFE_B_STORE_IRQ_EN_MASK << 16U,
116#endif /* FSL_FEATURE_PXP_V3 */
117};
118
125{
126 kPXP_CompleteFlag = PXP_STAT_IRQ0_MASK,
127 kPXP_Axi0WriteErrorFlag = PXP_STAT_AXI_WRITE_ERROR_0_MASK,
129 kPXP_Axi0ReadErrorFlag = PXP_STAT_AXI_READ_ERROR_0_MASK,
131 kPXP_CommandLoadFlag = PXP_STAT_NEXT_IRQ_MASK,
133#if !(defined(FSL_FEATURE_PXP_HAS_NO_LUT) && FSL_FEATURE_PXP_HAS_NO_LUT)
134 kPXP_LutDmaLoadFlag = PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_MASK,
135#endif
136#if defined(PXP_STAT_AXI_READ_ERROR_1_MASK)
137 kPXP_Axi1WriteErrorFlag = PXP_STAT_AXI_WRITE_ERROR_1_MASK,
139 kPXP_Axi1ReadErrorFlag = PXP_STAT_AXI_READ_ERROR_1_MASK,
141#endif
142#if defined(FSL_FEATURE_PXP_V3) && FSL_FEATURE_PXP_V3
143 kPXP_CompressDoneFlag = PXP_IRQ_COMPRESS_DONE_IRQ_MASK >> 16U,
144 kPXP_InputFetchCh0CompleteFlag = PXP_IRQ_FIRST_CH0_PREFETCH_IRQ_MASK
145 << 16U,
146 kPXP_InputFetchCh1CompleteFlag = PXP_IRQ_FIRST_CH1_PREFETCH_IRQ_MASK
147 << 16U,
148 kPXP_InputStoreCh0CompleteFlag = PXP_IRQ_FIRST_CH0_STORE_IRQ_MASK
149 << 16U,
150 kPXP_InputStoreCh1CompleteFlag = PXP_IRQ_FIRST_CH1_STORE_IRQ_MASK
151 << 16U,
152 kPXP_DitherFetchCh0CompleteFlag = PXP_IRQ_DITHER_CH0_PREFETCH_IRQ_MASK
153 << 16U,
154 kPXP_DitherFetchCh1CompleteFlag = PXP_IRQ_DITHER_CH1_PREFETCH_IRQ_MASK
155 << 16U,
156 kPXP_DitherStoreCh0CompleteFlag = PXP_IRQ_DITHER_CH0_STORE_IRQ_MASK
157 << 16U,
158 kPXP_DitherStoreCh1CompleteFlag = PXP_IRQ_DITHER_CH1_STORE_IRQ_MASK
159 << 16U,
160 kPXP_WfeaStoreCh0CompleteFlag = PXP_IRQ_WFE_A_CH0_STORE_IRQ_MASK
161 << 16U,
162 kPXP_WfeaStoreCh1CompleteFlag = PXP_IRQ_WFE_A_CH1_STORE_IRQ_MASK
163 << 16U,
164 kPXP_WfebStoreCh0CompleteFlag = PXP_IRQ_WFE_B_CH0_STORE_IRQ_MASK
165 << 16U,
166 kPXP_WfebStoreCh1CompleteFlag = PXP_IRQ_WFE_B_CH1_STORE_IRQ_MASK
167 << 16U,
168 kPXP_InputStoreCompleteFlag = PXP_IRQ_FIRST_STORE_IRQ_MASK << 16U,
169 kPXP_DitherStoreCompleteFlag = PXP_IRQ_DITHER_STORE_IRQ_MASK << 16U,
170 kPXP_WfeaStoreCompleteFlag = PXP_IRQ_WFE_A_STORE_IRQ_MASK << 16U,
171 kPXP_WfebStoreCompleteFlag = PXP_IRQ_WFE_B_STORE_IRQ_MASK << 16U,
172#endif /* FSL_FEATURE_PXP_V3 */
173};
174
175#if PXP_USE_PATH
176#if defined(FSL_FEATURE_PXP_V3) && FSL_FEATURE_PXP_V3
177typedef enum _pxp_path
178{
179 kPXP_Mux0SelectProcessSurfaceEngine = PXP_PATH(0U, 0U),
180 kPXP_Mux0SelectInputFetchEngineChannel0 = PXP_PATH(0U, 1U),
181 kPXP_Mux0SelectInputFetchEngineChannel1 = PXP_PATH(0U, 2U),
182 kPXP_Mux0SelectNone = PXP_PATH(0U, 3U),
183 kPXP_Mux1SelectInputFetchEngineChannel0 = PXP_PATH(1U, 0U),
184 kPXP_Mux1SelectRotation1Engine = PXP_PATH(1U, 1U),
185 kPXP_Mux1SelectNone = PXP_PATH(1U, 2U),
186 kPXP_Mux2SelectInputFetchEngineChannel1 = PXP_PATH(2U, 0U),
187 kPXP_Mux2SelectRotation1Engine = PXP_PATH(2U, 1U),
188 kPXP_Mux2SelectNone = PXP_PATH(2U, 2U),
189 kPXP_Mux3SelectCsc1Engine = PXP_PATH(3U, 0U),
190 kPXP_Mux3SelectRotation1Engine = PXP_PATH(3U, 1U),
191 kPXP_Mux3SelectNone = PXP_PATH(3U, 2U),
192 kPXP_Mux5SelectMux1 = PXP_PATH(5U, 0U),
193 kPXP_Mux5SelectAlphaBlending1 = PXP_PATH(5U, 1U),
194 kPXP_Mux5SelectNone = PXP_PATH(5U, 2U),
195 kPXP_Mux6SelectAlphaBlending1 = PXP_PATH(6U, 0U),
196 kPXP_Mux6SelectAlphaBlending0 = PXP_PATH(6U, 1U),
197 kPXP_Mux6SelectNone = PXP_PATH(6U, 2U),
198 kPXP_Mux7SelectMux5 = PXP_PATH(7U, 0U),
199 kPXP_Mux7SelectCsc2Engine = PXP_PATH(7U, 1U),
200 kPXP_Mux7SelectNone = PXP_PATH(7U, 2U),
201 kPXP_Mux8SelectCsc2Engine = PXP_PATH(8U, 0U),
202 kPXP_Mux8SelectAlphaBlending0 = PXP_PATH(8U, 1U),
203 kPXP_Mux8SelectNone = PXP_PATH(8U, 2U),
204 kPXP_Mux9SelectMux7 = PXP_PATH(9U, 0U),
205 kPXP_Mux9SelectMux8 = PXP_PATH(9U, 1U),
206 kPXP_Mux9SelectNone = PXP_PATH(9U, 2U),
207 kPXP_Mux10SelectMux7 = PXP_PATH(10U, 0U),
208 kPXP_Mux10SelectLut = PXP_PATH(10U, 1U),
209 kPXP_Mux10SelectNone = PXP_PATH(10U, 2U),
210 kPXP_Mux11SelectLut = PXP_PATH(11U, 0U),
211 kPXP_Mux11SelectMux8 = PXP_PATH(11U, 1U),
212 kPXP_Mux11SelectNone = PXP_PATH(11U, 2U),
213 kPXP_Mux12SelectMux10 = PXP_PATH(12U, 0U),
214 kPXP_Mux12SelectMux11 = PXP_PATH(12U, 1U),
215 kPXP_Mux12SelectNone = PXP_PATH(12U, 2U),
216 kPXP_Mux13SelectNone = PXP_PATH(13U, 0U),
217 kPXP_Mux13SelectFetchEngineChannel1 = PXP_PATH(13U, 1U),
218 kPXP_Mux14SelectRotation0Engine = PXP_PATH(14U, 0U),
219 kPXP_Mux14SelectMux11 = PXP_PATH(14U, 1U),
220 kPXP_Mux14SelectNone = PXP_PATH(14U, 2U),
221 kPXP_Mux15SelectFetchEngineChannel0 = PXP_PATH(15U, 0U),
222 kPXP_Mux15SelectMux10 = PXP_PATH(15U, 1U),
223 kPXP_Mux15SelectNone = PXP_PATH(15U, 2U),
224 kPXP_Mux16SelectAluA = PXP_PATH(16U, 0U),
225 kPXP_Mux16SelectOutput = PXP_PATH(16U, 1U),
226 kPXP_Mux16SelectAluB = PXP_PATH(16U, 2U),
227 kPXP_Mux16SelectNone = PXP_PATH(16U, 3U),
228 kPXP_Mux17SelectAluA = PXP_PATH(17U, 0U),
229 kPXP_Mux17SelectAluB = PXP_PATH(17U, 1U),
230 kPXP_Mux17SelectNone = PXP_PATH(17U, 2U),
231} pxp_path_t;
232#else
233typedef enum _pxp_path
234{
235 kPXP_Mux0SelectFetchDataArray = PXP_PATH(0U, 0U),
236 kPXP_Mux0SelectAlu = PXP_PATH(0U, 1U),
237 kPXP_Mux0SelectNone = PXP_PATH(0U, 2U),
238 kPXP_Mux1SelectLut = PXP_PATH(1U, 0U),
239 kPXP_Mux1SelectMux0 = PXP_PATH(1U, 1U),
240 kPXP_Mux1SelectNone = PXP_PATH(1U, 2U),
241 kPXP_Mux3SelectRotation1Engine = PXP_PATH(3U, 0U),
242 kPXP_Mux3SelectCsc1Engine = PXP_PATH(3U, 1U),
243 kPXP_Mux3SelectNone = PXP_PATH(3U, 2U),
244 kPXP_Mux8SelectCsc2Engine = PXP_PATH(8U, 0U),
245 kPXP_Mux8SelectAlphaBlending0 = PXP_PATH(8U, 1U),
246 kPXP_Mux8SelectNone = PXP_PATH(8U, 2U),
247 kPXP_Mux9SelectMux0 = PXP_PATH(9U, 0U),
248 kPXP_Mux9SelectMux8 = PXP_PATH(9U, 1U),
249 kPXP_Mux9SelectNone = PXP_PATH(9U, 2U),
250 kPXP_Mux11SelectLut = PXP_PATH(11U, 0U),
251 kPXP_Mux11SelectMux8 = PXP_PATH(11U, 1U),
252 kPXP_Mux11SelectNone = PXP_PATH(11U, 2U),
253 kPXP_Mux12SelectRotation0Engine = PXP_PATH(12U, 0U),
254 kPXP_Mux12SelectMux11 = PXP_PATH(12U, 1U),
255 kPXP_Mux12SelectNone = PXP_PATH(12U, 2U),
256 kPXP_Mux14SelectDitherEngine = PXP_PATH(14U, 0U),
257 kPXP_Mux14SelectMux12 = PXP_PATH(14U, 1U),
258 kPXP_Mux14SelectNone = PXP_PATH(14U, 2U),
259 kPXP_Mux16SelectOutputBuffer = PXP_PATH(16U, 0U),
260 kPXP_Mux16SelectStoreEngine = PXP_PATH(16U, 1U),
261 kPXP_Mux16SelectNone = PXP_PATH(16U, 2U),
262 kPXP_Mux17SelectOutputBuffer = PXP_PATH(17U, 0U),
263 kPXP_Mux17SelectStoreEngine = PXP_PATH(17U, 1U),
264 kPXP_Mux17SelectNone = PXP_PATH(17U, 2U),
265} pxp_path_t;
266#endif /* FSL_FEATURE_PXP_V3 */
267#endif /* PXP_USE_PATH */
268
270typedef enum _pxp_flip_mode
271{
277
280{
284
287{
293
296{
302
305{
324
327{
330 uint32_t buffer0Addr;
331 uint32_t buffer1Addr;
333 uint16_t pitchBytes;
334 uint16_t width;
335 uint16_t height;
337
340{
357
360{
364
367{
369 bool swapByte;
370 uint32_t bufferAddr;
371 uint32_t bufferAddrU;
372 uint32_t bufferAddrV;
373 uint16_t pitchBytes;
375
378{
387
390{
392 uint32_t bufferAddr;
393 uint16_t pitchBytes;
395
399typedef enum _pxp_alpha_mode
400{
409
419typedef enum _pxp_rop_mode
420{
432 kPXP_RopNotXorAs = 0xB
434
439{
440 uint8_t alpha;
446
447#if defined(FSL_FEATURE_PXP_V3) && FSL_FEATURE_PXP_V3
451typedef struct _pxp_as_blend_secondary_config
452{
453 bool invertAlpha;
454 bool ropEnable;
455 pxp_rop_mode_t ropMode;
456} pxp_as_blend_secondary_config_t;
457#endif /* FSL_FEATURE_PXP_V3 */
458
460typedef enum _pxp_block_size
461{
465
467typedef enum _pxp_csc1_mode
468{
472
474typedef enum _pxp_csc2_mode
475{
481
499typedef struct _pxp_csc2_config
500{
502 float A1;
503 float A2;
504 float A3;
505 float B1;
506 float B2;
507 float B3;
508 float C1;
509 float C2;
510 float C3;
511 int16_t D1;
512 int16_t D2;
513 int16_t D3;
515
516#if !(defined(FSL_FEATURE_PXP_HAS_NO_LUT) && FSL_FEATURE_PXP_HAS_NO_LUT)
519{
528
531{
536
539{
543
545typedef struct _pxp_lut_config
546{
549 uint32_t cfaValue;
551#endif /* FSL_FEATURE_PXP_HAS_NO_LUT */
552
554typedef enum _pxp_ram
555{
559#if defined(FSL_FEATURE_PXP_V3) && FSL_FEATURE_PXP_V3
560 kPXP_RamDither0Err0 = 1U,
561 kPXP_RamDither0Err1 = 2U,
562 kPXP_RamAluA = 5U,
563 kPXP_RamAluB = 6U,
564 kPXP_WfeAFetch = 7U,
565 kPXP_WfeBFetch = 8U,
566#endif /* FSL_FEATURE_PXP_V3 */
568
571{
578};
579
582{
587};
588
591{
595};
596
599{
600 uint32_t data_3_0;
601 uint32_t data_7_4;
602 uint32_t data_11_8;
603 uint32_t data_15_12;
605
607typedef struct _pxp_dither_config
608{
609 uint32_t enableDither0 : 1;
610 uint32_t enableDither1 : 1;
611 uint32_t enableDither2 : 1;
612 uint32_t ditherMode0 : 3;
613 uint32_t ditherMode1 : 3;
614 uint32_t ditherMode2 : 3;
615 uint32_t quantBitNum : 3;
616 uint32_t lutMode : 2;
619 uint32_t idxMatrixSize0 : 2;
621 uint32_t idxMatrixSize1 : 2;
623 uint32_t idxMatrixSize2 : 2;
625 uint32_t enableFinalLut : 1;
626 uint32_t : 8;
628
633enum
634{
639};
640
645enum
646{
650};
651
656enum
657{
661
666enum
667{
672};
673
675typedef struct
676{
677 uint32_t enable : 1;
678 uint32_t srcFactorMode : 2;
679 uint32_t dstGlobalAlphaMode : 2;
681 uint32_t dstAlphaMode : 1;
682 uint32_t dstColorMode : 1;
683 uint32_t : 1;
684 uint32_t dstFactorMode : 2;
685 uint32_t srcGlobalAlphaMode : 2;
687 uint32_t srcAlphaMode : 1;
688 uint32_t srcColorMode : 1;
689 uint32_t : 2;
690 uint32_t dstGlobalAlpha : 8;
691 uint32_t srcGlobalAlpha : 8;
693
696{
709 kPXP_PorterDuffMax,
711
714{
715 uint32_t srcPicBaseAddr;
716 uint16_t srcPitchBytes;
717 uint16_t srcOffsetX;
718 uint16_t srcOffsetY;
720 uint16_t destPitchBytes;
721 uint16_t destOffsetX;
722 uint16_t destOffsetY;
723 uint16_t width;
724 uint16_t height;
727
728#if defined(FSL_FEATURE_PXP_V3) && FSL_FEATURE_PXP_V3
729
733typedef enum _pxp_process_engine_name
734{
735 kPXP_PsAsOutEngine = PXP_CTRL_ENABLE_PS_AS_OUT_MASK,
736 kPXP_DitherEngine = PXP_CTRL_ENABLE_DITHER_MASK,
737 kPXP_WfeaEngine = PXP_CTRL_ENABLE_WFE_A_MASK,
738 kPXP_WfebEngine = PXP_CTRL_ENABLE_WFE_B_MASK,
739 kPXP_InputFetchStoreEngine = PXP_CTRL_ENABLE_INPUT_FETCH_STORE_MASK,
740 kPXP_Alpha1Engine = PXP_CTRL_ENABLE_ALPHA_B_MASK,
741 kPXP_Csc2Engine = PXP_CTRL_ENABLE_CSC2_MASK,
742 kPXP_LutEngine = PXP_CTRL_ENABLE_LUT_MASK,
743 kPXP_Rotate0Engine = PXP_CTRL_ENABLE_ROTATE0_MASK,
744 kPXP_Rotate1Engine = PXP_CTRL_ENABLE_ROTATE1_MASK,
745} pxp_process_engine_name_t;
746
747/* Fetch engine configuration. */
754typedef enum _pxp_fetch_engine_name
755{
756 kPXP_FetchInput,
757 kPXP_FetchDither,
758} pxp_fetch_engine_name_t;
759
761typedef enum _pxp_fetch_interface_mode
762{
763 kPXP_FetchModeNormal = 0U,
764 kPXP_FetchModeHandshake = 0x1U,
765 kPXP_FetchModeBypass = 0x2U,
766} pxp_fetch_interface_mode_t;
767
769typedef enum _pxp_scanline_burst
770{
771 kPXP_Scanline8bytes,
772 kPXP_Scanline16bytes,
773 kPXP_Scanline32bytes,
774 kPXP_Scanline64bytes,
775} pxp_scanline_burst_t;
776
778typedef struct _pxp_block_format_config
779{
780 bool
781 enableblock;
784 bool blockSize16;
785 pxp_scanline_burst_t burstLength;
786} pxp_block_config_t;
787
794typedef enum _pxp_activeBits
795{
796 kPXP_Active8Bits = 0x0,
797 kPXP_Active16Bits = 0x1,
798 kPXP_Active32Bits = 0x2,
799 kPXP_Active64Bits = 0x3,
800} pxp_active_bits_t;
801
803typedef enum _pxp_fetch_output_word_order
804{
805 kPXP_FetchOutputChannel1channel0 = 0x0,
806 kPXP_FetchOutputChannel0channel1 = 0x1,
807} pxp_fetch_output_word_order_t;
808
814typedef struct _pxp_fetch_shift_component
815{
816 uint8_t offset;
817 uint8_t width;
818} pxp_fetch_shift_component_t;
819
827typedef struct _pxp_fetch_shift_config
828{
829 bool shiftBypass; /* Bypass the shift */
830 pxp_fetch_shift_component_t component0;
831 pxp_fetch_shift_component_t component1;
832 pxp_fetch_shift_component_t component2;
833 pxp_fetch_shift_component_t component3;
834} pxp_fetch_shift_config_t;
835
837typedef enum _pxp_fetch_pixel_format
838{
839 kPXP_FetchFormatRGB565 = 0x0,
840 kPXP_FetchFormatRGB555 = 0x1,
841 kPXP_FetchFormatARGB1555 = 0x2,
842 kPXP_FetchFormatRGB444 = 0x3,
843 kPXP_FetchFormatARGB4444 = 0x4,
844 kPXP_FetchFormatYUYVorYVYU = 0x5,
845 kPXP_FetchFormatUYVYorVYUY = 0x6,
846 kPXP_FetchFormatYUV422_2P = 0x7,
847} pxp_fetch_pixel_format_t;
848
850typedef struct _pxp_fetch_engine_config
851{
852 bool channelEnable;
853 /* Address configuration */
854 uint32_t inputBaseAddr0;
855 uint32_t inputBaseAddr1;
856 /* Size configuration */
857 uint16_t totalHeight;
858 uint16_t totalWidth;
859 uint16_t pitchBytes;
860 uint16_t
861 ulcX;
862 uint16_t
863 ulcY;
864 uint16_t
865 lrcX;
866 uint16_t
867 lrcY;
868 /* Interface configuration */
869 pxp_fetch_interface_mode_t interface;
870 /* Pixel configuration */
871 pxp_active_bits_t activeBits;
872 pxp_fetch_pixel_format_t pixelFormat;
873 bool expandEnable;
875 /* Fetch format configuration */
876 pxp_flip_mode_t flipMode;
877 pxp_rotate_degree_t rotateDegree;
878 pxp_block_config_t
879 fetchFormat;
880 /* Output configuration. */
881 pxp_fetch_shift_config_t shiftConfig;
882 pxp_fetch_output_word_order_t wordOrder;
883} pxp_fetch_engine_config_t;
884
885/* Store engine configuration. */
886
893typedef enum _pxp_store_engine_name
894{
895 kPXP_StoreInput,
896 kPXP_StoreDither,
897} pxp_store_engine_name_t;
898
900typedef enum _pxp_store_interface_mode
901{
902 kPXP_StoreModeBypass = 0x20U,
903 kPXP_StoreModeNormal = 0x40U,
904 kPXP_StoreModeHandshake = 0x43U,
905 kPXP_StoreModeDual = 0x60U,
907} pxp_store_interface_mode_t;
908
910typedef enum _pxp_store_yuv_mode
911{
912 kPXP_StoreYUVDisable = 0U,
913 kPXP_StoreYUVPlane1 =
914 0x1U,
916 kPXP_StoreYUVPlane2 =
917 0x2U,
919} pxp_store_yuv_mode_t;
920
922typedef struct _pxp_store_shift_config
923{
924 /* Data/Flag shift */
925 bool shiftBypass;
926 uint64_t *pDataShiftMask;
928 uint8_t *pDataShiftWidth;
930 uint8_t *pFlagShiftMask;
932 uint8_t *pFlagShiftWidth;
934} pxp_store_shift_config_t;
935
937typedef struct _pxp_store_engine_config
938{
939 bool channelEnable;
940 /* Address configuration */
941 uint32_t outputBaseAddr0;
943 uint32_t outputBaseAddr1;
945 /* Size configuration */
946 uint16_t totalHeight;
947 uint16_t totalWidth;
948 uint16_t pitchBytes;
949 /* Interface configuration */
950 pxp_store_interface_mode_t interface;
952 /* pxp_store_handshake_array_t arraySize; !< If interfase mode is handshake, need to configure the array size. When
953 block is disabled, the scanline can only be 1. TODO no need now. */
954 /* Pixel configuration */
955 pxp_active_bits_t activeBits;
956 pxp_store_yuv_mode_t yuvMode;
957 /* Fixed data configuration, only apply for channel 0. */
958 bool useFixedData;
960 uint32_t fixedData;
961 /* Data packing */
962 bool packInSelect;
964 /* Data store format */
965 pxp_block_config_t storeFormat;
966 pxp_store_shift_config_t shiftConfig;
967} pxp_store_engine_config_t;
968
969/* Pre-dither CFA engine configuration */
970
972typedef enum _pxp_cfa_input_format
973{
974 kPXP_CfaRGB888,
975 kPXP_CfaRGB444,
976} pxp_cfa_input_format_t;
977
979typedef struct _pxp_cfa_config
980{
981 bool bypass;
982 pxp_cfa_input_format_t pixelInFormat;
983 uint8_t arrayWidth;
984 uint8_t arrayHeight;
985 uint16_t totalHeight;
987 uint16_t totalWidth;
989 uint32_t *cfaValue;
991} pxp_cfa_config_t;
992
993/* Histogram configuration and status */
994
996typedef enum _pxp_histogram_mask_condition
997{
998 kPXP_HistogramMaskEqual = 0x0U,
999 kPXP_HistogramMaskNotequal = 0x1U,
1000 kPXP_HistogramMaskIn = 0x2U,
1001 kPXP_HistogramMaskOut = 0x3U,
1002} pxp_histogram_mask_condition_t;
1003
1005typedef struct _pxp_histogram_config
1006{
1007 bool enable;
1008 uint8_t *pParamValue;
1010 uint8_t lutValueOffset;
1011 uint8_t lutValueWidth;
1013 /* Mask configuration */
1014 bool enableMask;
1015 uint8_t maskValue0;
1016 uint8_t maskValue1;
1017 uint8_t maskOffset;
1018 uint8_t maskWidth;
1019 pxp_histogram_mask_condition_t condition;
1020 /* Size configuration */
1021 uint16_t totalHeight;
1023 uint16_t totalWidth;
1025} pxp_histogram_config_t;
1026
1028typedef struct _pxp_histogram_mask_result
1029{
1030 uint32_t pixelCount;
1031 uint32_t minX;
1032 uint32_t minY;
1033 uint32_t maxX;
1034 uint32_t maxY;
1035 uint64_t lutlist;
1037} pxp_histogram_mask_result_t;
1038
1040enum _pxp_histgram_flags
1041{
1042 kPXP_Histogram2levelMatch = 1 << 0U, /* Bitmap pixels are fully contained within the HIST2 histogram. */
1043 kPXP_Histogram4levelMatch = 1 << 1U, /* Bitmap pixels are fully contained within the HIST4 histogram. */
1044 kPXP_Histogram8levelMatch = 1 << 2U, /* Bitmap pixels are fully contained within the HIST8 histogram. */
1045 kPXP_Histogram16levelMatch = 1 << 3U, /* Bitmap pixels are fully contained within the HIST16 histogram. */
1046 kPXP_Histogram32levelMatch = 1 << 4U, /* Bitmap pixels are fully contained within the HIST32 histogram. */
1047};
1048
1050typedef struct _pxp_wfea_engine_config
1051{
1052 uint32_t y4Addr;
1053 uint32_t y4cAddr;
1054 uint32_t wbAddr;
1055 uint16_t updateWidth;
1056 uint16_t updateHeight;
1057 uint16_t updatePitch;
1058 uint16_t ulcX;
1059 uint16_t ulcY;
1060 uint16_t resX;
1061 uint8_t lutNum;
1062 bool fullUpdateEnable;
1063 bool alphaEnable;
1064 bool detectionOnly;
1065} pxp_wfea_engine_config_t;
1066
1067#endif /* FSL_FEATURE_PXP_V3 */
1068
1069/*******************************************************************************
1070 * API
1071 ******************************************************************************/
1072
1073#if defined(__cplusplus)
1074extern "C" {
1075#endif
1076
1090void PXP_Init(PXP_Type *base);
1091
1099void PXP_Deinit(PXP_Type *base);
1100
1108void PXP_Reset(PXP_Type *base);
1109
1115void PXP_ResetControl(PXP_Type *base);
1116/* @} */
1117
1130static inline void PXP_Start(PXP_Type *base)
1131{
1132 base->CTRL_SET = PXP_CTRL_ENABLE_MASK;
1133}
1134
1141static inline void PXP_EnableLcdHandShake(PXP_Type *base, bool enable)
1142{
1143#if defined(PXP_CTRL_ENABLE_LCD_HANDSHAKE_MASK)
1144 if (enable)
1145 {
1146 base->CTRL_SET = PXP_CTRL_ENABLE_LCD_HANDSHAKE_MASK;
1147 }
1148 else
1149 {
1150 base->CTRL_CLR = PXP_CTRL_ENABLE_LCD_HANDSHAKE_MASK;
1151 }
1152#else
1153 if (enable)
1154 {
1155 base->CTRL_SET = PXP_CTRL_ENABLE_LCD0_HANDSHAKE_MASK;
1156 }
1157 else
1158 {
1159 base->CTRL_CLR = PXP_CTRL_ENABLE_LCD0_HANDSHAKE_MASK;
1160 }
1161#endif
1162}
1163
1164#if (defined(FSL_FEATURE_PXP_HAS_EN_REPEAT) && FSL_FEATURE_PXP_HAS_EN_REPEAT)
1177static inline void PXP_EnableContinousRun(PXP_Type *base, bool enable)
1178{
1179 if (enable)
1180 {
1181 base->CTRL_SET = PXP_CTRL_EN_REPEAT_MASK;
1182 }
1183 else
1184 {
1185 base->CTRL_CLR = PXP_CTRL_EN_REPEAT_MASK;
1186 }
1187}
1188#endif /* FSL_FEATURE_PXP_HAS_EN_REPEAT */
1189
1200static inline void PXP_SetProcessBlockSize(PXP_Type *base, pxp_block_size_t size)
1201{
1202 base->CTRL = (base->CTRL & ~PXP_CTRL_BLOCK_SIZE_MASK) | PXP_CTRL_BLOCK_SIZE(size);
1203}
1204
1205#if PXP_USE_PATH
1212void PXP_SetPath(PXP_Type *base, pxp_path_t path);
1213#endif /* PXP_USE_PATH */
1214
1215#if defined(FSL_FEATURE_PXP_V3) && FSL_FEATURE_PXP_V3
1223static inline void PXP_EnableProcessEngine(PXP_Type *base, uint32_t mask, bool enable)
1224{
1225 mask &= 0xF3F0000UL;
1226
1227 if (enable)
1228 {
1229 base->CTRL_SET = mask;
1230 }
1231 else
1232 {
1233 base->CTRL_CLR = mask;
1234 }
1235}
1236#endif /* FSL_FEATURE_PXP_V3 */
1237
1238/* @} */
1239
1262static inline uint32_t PXP_GetStatusFlags(PXP_Type *base)
1263{
1264#if defined(PXP_STAT_AXI_READ_ERROR_1_MASK)
1265 uint32_t status = base->STAT & (PXP_STAT_NEXT_IRQ_MASK | PXP_STAT_IRQ0_MASK | PXP_STAT_AXI_READ_ERROR_0_MASK |
1266 PXP_STAT_AXI_WRITE_ERROR_0_MASK | PXP_STAT_AXI_READ_ERROR_1_MASK |
1267 PXP_STAT_AXI_WRITE_ERROR_1_MASK);
1268#else
1269 uint32_t status = base->STAT & (PXP_STAT_NEXT_IRQ_MASK | PXP_STAT_IRQ0_MASK | PXP_STAT_AXI_READ_ERROR_0_MASK |
1270 PXP_STAT_AXI_WRITE_ERROR_0_MASK);
1271#endif
1272#if defined(FSL_FEATURE_PXP_V3) && FSL_FEATURE_PXP_V3
1273 status |= (base->IRQ >> 16U | base->IRQ << 16U);
1274#endif /* FSL_FEATURE_PXP_V3 */
1275 return status;
1276}
1277
1286static inline void PXP_ClearStatusFlags(PXP_Type *base, uint32_t statusMask)
1287{
1288 base->STAT_CLR = statusMask;
1289#if defined(FSL_FEATURE_PXP_V3) && FSL_FEATURE_PXP_V3
1290 statusMask &= 0xFFFF8000UL;
1291 base->IRQ_CLR = (statusMask >> 16U | statusMask << 16U);
1292#endif /* FSL_FEATURE_PXP_V3 */
1293}
1294
1304static inline uint8_t PXP_GetAxiErrorId(PXP_Type *base, uint8_t axiIndex)
1305{
1306#if defined(PXP_STAT_AXI_ERROR_ID_1_MASK)
1307 if (0U == axiIndex)
1308 {
1309 return (uint8_t)((base->STAT & PXP_STAT_AXI_ERROR_ID_0_MASK) >> PXP_STAT_AXI_ERROR_ID_0_SHIFT);
1310 }
1311 else
1312 {
1313 return (uint8_t)((base->STAT & PXP_STAT_AXI_ERROR_ID_1_MASK) >> PXP_STAT_AXI_ERROR_ID_1_SHIFT);
1314 }
1315#else
1316 return (uint8_t)((base->STAT & PXP_STAT_AXI_ERROR_ID_MASK) >> PXP_STAT_AXI_ERROR_ID_SHIFT);
1317#endif
1318}
1319
1320/* @} */
1321
1341static inline void PXP_EnableInterrupts(PXP_Type *base, uint32_t mask)
1342{
1343 base->CTRL_SET = (mask & 0xEUL);
1344#if defined(FSL_FEATURE_PXP_V3) && FSL_FEATURE_PXP_V3
1345 mask &= 0xFFFF8000UL;
1346 base->IRQ_MASK_SET = (mask >> 16U | mask << 16U);
1347#endif /* FSL_FEATURE_PXP_V3 */
1348}
1349
1359static inline void PXP_DisableInterrupts(PXP_Type *base, uint32_t mask)
1360{
1361 base->CTRL_CLR = (mask & 0xEUL);
1362#if defined(FSL_FEATURE_PXP_V3) && FSL_FEATURE_PXP_V3
1363 mask &= 0xFFFF8000UL;
1364 base->IRQ_MASK_CLR = (mask >> 16U | mask << 16U);
1365#endif /* FSL_FEATURE_PXP_V3 */
1366}
1367
1368/* @} */
1369
1382
1390
1391#if defined(FSL_FEATURE_PXP_V3) && FSL_FEATURE_PXP_V3
1398void PXP_SetAlphaSurfaceBlendSecondaryConfig(PXP_Type *base, const pxp_as_blend_secondary_config_t *config);
1399
1415void PXP_SetAlphaSurfaceOverlayColorKey(PXP_Type *base, uint8_t num, uint32_t colorKeyLow, uint32_t colorKeyHigh);
1416
1424static inline void PXP_EnableAlphaSurfaceOverlayColorKey(PXP_Type *base, uint32_t num, bool enable)
1425{
1426 switch (num)
1427 {
1428 case 0:
1429 base->AS_CTRL =
1430 (base->AS_CTRL & ~PXP_AS_CTRL_ENABLE_COLORKEY_MASK) | PXP_AS_CTRL_ENABLE_COLORKEY((uint32_t)enable);
1431 break;
1432
1433 case 1:
1434 base->ALPHA_B_CTRL_1 = (base->ALPHA_B_CTRL_1 & ~PXP_ALPHA_B_CTRL_1_OL_CLRKEY_ENABLE_MASK) |
1435 PXP_ALPHA_B_CTRL_1_OL_CLRKEY_ENABLE((uint32_t)enable);
1436 break;
1437
1438 default:
1439 /* Only 2 alpha process engine instances are supported. */
1440 assert(false);
1441 break;
1442 }
1443}
1444#else
1459void PXP_SetAlphaSurfaceOverlayColorKey(PXP_Type *base, uint32_t colorKeyLow, uint32_t colorKeyHigh);
1460
1467static inline void PXP_EnableAlphaSurfaceOverlayColorKey(PXP_Type *base, bool enable)
1468{
1469 if (enable)
1470 {
1471 base->AS_CTRL |= PXP_AS_CTRL_ENABLE_COLORKEY_MASK;
1472 }
1473 else
1474 {
1475 base->AS_CTRL &= ~PXP_AS_CTRL_ENABLE_COLORKEY_MASK;
1476 }
1477}
1478#endif /* FSL_FEATURE_PXP_V3 */
1479
1490 PXP_Type *base, uint16_t upperLeftX, uint16_t upperLeftY, uint16_t lowerRightX, uint16_t lowerRightY);
1491/* @} */
1492
1497#if defined(FSL_FEATURE_PXP_V3) && FSL_FEATURE_PXP_V3
1505static inline void PXP_SetProcessSurfaceBackGroundColor(PXP_Type *base, uint8_t num, uint32_t backGroundColor)
1506{
1507 switch (num)
1508 {
1509 case 0:
1510 base->PS_BACKGROUND_0 = backGroundColor;
1511 break;
1512
1513 case 1:
1514 base->PS_BACKGROUND_1 = backGroundColor;
1515 break;
1516
1517 default:
1518 /* Only 2 alpha process engine instances are supported. */
1519 assert(false);
1520 break;
1521 }
1522}
1523#else
1530static inline void PXP_SetProcessSurfaceBackGroundColor(PXP_Type *base, uint32_t backGroundColor)
1531{
1532#if defined(PXP_PS_BACKGROUND_0_COLOR_MASK)
1533 base->PS_BACKGROUND_0 = backGroundColor;
1534#else
1535 base->PS_BACKGROUND = backGroundColor;
1536#endif
1537}
1538#endif /* FSL_FEATURE_PXP_V3 */
1539
1547
1560 PXP_Type *base, uint16_t inputWidth, uint16_t inputHeight, uint16_t outputWidth, uint16_t outputHeight);
1561
1572 PXP_Type *base, uint16_t upperLeftX, uint16_t upperLeftY, uint16_t lowerRightX, uint16_t lowerRightY);
1573
1574#if defined(FSL_FEATURE_PXP_V3) && FSL_FEATURE_PXP_V3
1586void PXP_SetProcessSurfaceColorKey(PXP_Type *base, uint8_t num, uint32_t colorKeyLow, uint32_t colorKeyHigh);
1587#else
1598void PXP_SetProcessSurfaceColorKey(PXP_Type *base, uint32_t colorKeyLow, uint32_t colorKeyHigh);
1599#endif /* FSL_FEATURE_PXP_V3 */
1600
1612static inline void PXP_SetProcessSurfaceYUVFormat(PXP_Type *base, pxp_ps_yuv_format_t format)
1613{
1615 {
1616 base->CSC1_COEF0 &= ~PXP_CSC1_COEF0_YCBCR_MODE_MASK;
1617 }
1618 else
1619 {
1620 base->CSC1_COEF0 |= PXP_CSC1_COEF0_YCBCR_MODE_MASK;
1621 }
1622}
1623/* @} */
1624
1637
1647static inline void PXP_SetOverwrittenAlphaValue(PXP_Type *base, uint8_t alpha)
1648{
1649 base->OUT_CTRL = (base->OUT_CTRL & ~PXP_OUT_CTRL_ALPHA_MASK) | PXP_OUT_CTRL_ALPHA(alpha);
1650}
1651
1661static inline void PXP_EnableOverWrittenAlpha(PXP_Type *base, bool enable)
1662{
1663 if (enable)
1664 {
1665 base->OUT_CTRL_SET = PXP_OUT_CTRL_ALPHA_OUTPUT_MASK;
1666 }
1667 else
1668 {
1669 base->OUT_CTRL_CLR = PXP_OUT_CTRL_ALPHA_OUTPUT_MASK;
1670 }
1671}
1672
1697static inline void PXP_SetRotateConfig(PXP_Type *base,
1698 pxp_rotate_position_t position,
1699 pxp_rotate_degree_t degree,
1700 pxp_flip_mode_t flipMode)
1701{
1702#if PXP_SHARE_ROTATE
1703 base->CTRL =
1704 (base->CTRL & ~(PXP_CTRL_ROTATE_MASK | PXP_CTRL_ROT_POS_MASK | PXP_CTRL_VFLIP_MASK | PXP_CTRL_HFLIP_MASK)) |
1705 PXP_CTRL_ROTATE(degree) | PXP_CTRL_ROT_POS(position) | ((uint32_t)flipMode << PXP_CTRL_HFLIP_SHIFT);
1706#else
1707 uint32_t ctrl = base->CTRL;
1708
1709 if (kPXP_RotateOutputBuffer == position)
1710 {
1711 ctrl &= ~(PXP_CTRL_HFLIP0_MASK | PXP_CTRL_VFLIP0_MASK | PXP_CTRL_ROTATE0_MASK);
1712 ctrl |= (PXP_CTRL_ROTATE0(degree) | ((uint32_t)flipMode << PXP_CTRL_HFLIP0_SHIFT));
1713 }
1714 else
1715 {
1716 ctrl &= ~(PXP_CTRL_HFLIP1_MASK | PXP_CTRL_VFLIP1_MASK | PXP_CTRL_ROTATE1_MASK);
1717 ctrl |= (PXP_CTRL_ROTATE1(degree) | ((uint32_t)flipMode << PXP_CTRL_HFLIP1_SHIFT));
1718 }
1719
1720 base->CTRL = ctrl;
1721#endif
1722}
1723
1735void PXP_BuildRect(PXP_Type *base,
1736 pxp_output_pixel_format_t outFormat,
1737 uint32_t value,
1738 uint16_t width,
1739 uint16_t height,
1740 uint16_t pitch,
1741 uint32_t outAddr);
1742/* @} */
1743
1793void PXP_SetNextCommand(PXP_Type *base, void *commandAddr);
1794
1801static inline bool PXP_IsNextCommandPending(PXP_Type *base)
1802{
1803 return (bool)(base->NEXT & PXP_NEXT_ENABLED_MASK);
1804}
1805
1811static inline void PXP_CancelNextCommand(PXP_Type *base)
1812{
1813 /* Write PXP_NEXT_ENABLED_MASK to the register NEXT_CLR to canel the command. */
1814 uint32_t regAddr = (uint32_t) & (base->NEXT);
1815 regAddr += 8U;
1816 *(uint32_t *)regAddr = PXP_NEXT_ENABLED_MASK;
1817}
1818
1819/* @} */
1820
1826#if !(defined(FSL_FEATURE_PXP_HAS_NO_CSC2) && FSL_FEATURE_PXP_HAS_NO_CSC2)
1838
1845static inline void PXP_EnableCsc2(PXP_Type *base, bool enable)
1846{
1847 if (enable)
1848 {
1849 base->CSC2_CTRL &= ~PXP_CSC2_CTRL_BYPASS_MASK;
1850 }
1851 else
1852 {
1853 base->CSC2_CTRL |= PXP_CSC2_CTRL_BYPASS_MASK;
1854 }
1855}
1856#endif /* FSL_FEATURE_PXP_HAS_NO_CSC2 */
1857
1868void PXP_SetCsc1Mode(PXP_Type *base, pxp_csc1_mode_t mode);
1869
1876static inline void PXP_EnableCsc1(PXP_Type *base, bool enable)
1877{
1878 if (enable)
1879 {
1880 base->CSC1_COEF0 &= ~PXP_CSC1_COEF0_BYPASS_MASK;
1881 }
1882 else
1883 {
1884 base->CSC1_COEF0 |= PXP_CSC1_COEF0_BYPASS_MASK;
1885 }
1886}
1887/* @} */
1888
1889#if !(defined(FSL_FEATURE_PXP_HAS_NO_LUT) && FSL_FEATURE_PXP_HAS_NO_LUT)
1909
1933 PXP_Type *base, pxp_lut_lookup_mode_t lookupMode, uint32_t bytesNum, uint32_t memAddr, uint16_t lutStartAddr);
1934
1941static inline void PXP_EnableLut(PXP_Type *base, bool enable)
1942{
1943 if (enable)
1944 {
1945 base->LUT_CTRL &= ~PXP_LUT_CTRL_BYPASS_MASK;
1946 }
1947 else
1948 {
1949 base->LUT_CTRL |= PXP_LUT_CTRL_BYPASS_MASK;
1950 }
1951}
1952
1959static inline void PXP_Select8kLutBank(PXP_Type *base, pxp_lut_8k_bank_t bank)
1960{
1961 base->LUT_CTRL = (base->LUT_CTRL & ~PXP_LUT_CTRL_SEL_8KB_MASK) | PXP_LUT_CTRL_SEL_8KB(bank);
1962}
1963/* @} */
1964#endif /* FSL_FEATURE_PXP_HAS_NO_LUT */
1965
1966#if (defined(FSL_FEATURE_PXP_HAS_DITHER) && FSL_FEATURE_PXP_HAS_DITHER)
1981void PXP_SetInternalRamData(PXP_Type *base, pxp_ram_t ram, uint32_t bytesNum, uint8_t *data, uint16_t memStartAddr);
1982
1993void PXP_SetDitherFinalLutData(PXP_Type *base, const pxp_dither_final_lut_data_t *data);
1994
2010static inline void PXP_SetDitherConfig(PXP_Type *base, const pxp_dither_config_t *config)
2011{
2012 typedef union
2013 {
2014 pxp_dither_config_t _dither_config;
2015 uint32_t _u32;
2016 } pxp_reg_convert_t;
2017
2018 pxp_reg_convert_t pid;
2019
2020 pid._dither_config = *config;
2021 base->DITHER_CTRL = pid._u32 & 0x00FFFFFFU;
2022}
2023
2037void PXP_EnableDither(PXP_Type *base, bool enable);
2038
2039/* @} */
2040
2041#endif /* FSL_FEATURE_PXP_HAS_DITHER */
2042
2047#if defined(FSL_FEATURE_PXP_V3) && FSL_FEATURE_PXP_V3
2055void PXP_SetPorterDuffConfig(PXP_Type *base, uint8_t num, const pxp_porter_duff_config_t *config);
2056#endif /* FSL_FEATURE_PXP_V3 */
2057
2058#if !(defined(FSL_FEATURE_PXP_HAS_NO_PORTER_DUFF_CTRL) && FSL_FEATURE_PXP_HAS_NO_PORTER_DUFF_CTRL)
2066#endif /* FSL_FEATURE_PXP_HAS_NO_PORTER_DUFF_CTRL */
2067
2068#if (!(defined(FSL_FEATURE_PXP_HAS_NO_PORTER_DUFF_CTRL) && FSL_FEATURE_PXP_HAS_NO_PORTER_DUFF_CTRL)) || \
2069 (defined(FSL_FEATURE_PXP_V3) && FSL_FEATURE_PXP_V3)
2085
2086/* @} */
2087#endif /* FSL_FEATURE_PXP_V3 || FSL_FEATURE_PXP_HAS_NO_PORTER_DUFF_CTRL */
2088
2089/* @} */
2090
2150
2165status_t PXP_StartMemCopy(PXP_Type *base, uint32_t srcAddr, uint32_t destAddr, uint32_t size);
2166
2184status_t PXP_MemCopy(PXP_Type *base, uint32_t srcAddr, uint32_t destAddr, uint32_t size);
2185
2186/* @} */
2187
2188#if defined(FSL_FEATURE_PXP_V3) && FSL_FEATURE_PXP_V3
2189
2206status_t PXP_SetFetchEngineConfig(PXP_Type *base,
2207 pxp_fetch_engine_name_t name,
2208 uint8_t channel,
2209 const pxp_fetch_engine_config_t *config);
2210
2219static inline void PXP_EnableFetchEngine(PXP_Type *base, pxp_fetch_engine_name_t name, uint8_t channel, bool enable)
2220{
2221 if (enable)
2222 {
2223 if (name == kPXP_FetchInput)
2224 {
2225 switch (channel)
2226 {
2227 case 0:
2228 base->INPUT_FETCH_CTRL_CH0_SET = PXP_INPUT_FETCH_CTRL_CH0_CH_EN_MASK;
2229 break;
2230
2231 case 1:
2232 base->INPUT_FETCH_CTRL_CH1_SET = PXP_INPUT_FETCH_CTRL_CH1_CH_EN_MASK;
2233 break;
2234
2235 default:
2236 /* Only 2 channels are supported per fetch engine. */
2237 assert(false);
2238 break;
2239 }
2240 }
2241 else
2242 {
2243 switch (channel)
2244 {
2245 case 0:
2246 base->DITHER_FETCH_CTRL_CH0_SET = PXP_DITHER_FETCH_CTRL_CH0_CH_EN_MASK;
2247 break;
2248
2249 case 1:
2250 base->DITHER_FETCH_CTRL_CH1_SET = PXP_DITHER_FETCH_CTRL_CH1_CH_EN_MASK;
2251 break;
2252
2253 default:
2254 /* Only 2 channels are supported per fetch engine. */
2255 assert(false);
2256 break;
2257 }
2258 }
2259 }
2260 else
2261 {
2262 if (name == kPXP_FetchInput)
2263 {
2264 switch (channel)
2265 {
2266 case 0:
2267 base->INPUT_FETCH_CTRL_CH0_CLR = PXP_INPUT_FETCH_CTRL_CH0_CH_EN_MASK;
2268 break;
2269
2270 case 1:
2271 base->INPUT_FETCH_CTRL_CH1_CLR = PXP_INPUT_FETCH_CTRL_CH1_CH_EN_MASK;
2272 break;
2273
2274 default:
2275 /* Only 2 channels are supported per fetch engine. */
2276 assert(false);
2277 break;
2278 }
2279 }
2280 else
2281 {
2282 switch (channel)
2283 {
2284 case 0:
2285 base->DITHER_FETCH_CTRL_CH0_CLR = PXP_DITHER_FETCH_CTRL_CH0_CH_EN_MASK;
2286 break;
2287
2288 case 1:
2289 base->DITHER_FETCH_CTRL_CH1_CLR = PXP_DITHER_FETCH_CTRL_CH1_CH_EN_MASK;
2290 break;
2291
2292 default:
2293 /* Only 2 channels are supported per fetch engine. */
2294 assert(false);
2295 break;
2296 }
2297 }
2298 }
2299}
2300/* @} */
2301
2320status_t PXP_SetStoreEngineConfig(PXP_Type *base,
2321 pxp_store_engine_name_t name,
2322 uint8_t channel,
2323 const pxp_store_engine_config_t *config);
2324
2333static inline void PXP_EnableStoreEngine(PXP_Type *base, pxp_store_engine_name_t name, uint8_t channel, bool enable)
2334{
2335 if (enable)
2336 {
2337 if (name == kPXP_StoreInput)
2338 {
2339 switch (channel)
2340 {
2341 case 0:
2342 base->INPUT_STORE_CTRL_CH0_SET = PXP_INPUT_STORE_CTRL_CH0_CH_EN_MASK;
2343 break;
2344
2345 case 1:
2346 base->INPUT_STORE_CTRL_CH1_SET = PXP_INPUT_STORE_CTRL_CH1_CH_EN_MASK;
2347 break;
2348
2349 default:
2350 /* Only 2 channels are supported per fetch engine. */
2351 assert(false);
2352 break;
2353 }
2354 }
2355 else
2356 {
2357 switch (channel)
2358 {
2359 case 0:
2360 base->DITHER_STORE_CTRL_CH0_SET = PXP_DITHER_STORE_CTRL_CH0_CH_EN_MASK;
2361 break;
2362
2363 case 1:
2364 base->DITHER_STORE_CTRL_CH1_SET = PXP_DITHER_STORE_CTRL_CH1_CH_EN_MASK;
2365 break;
2366
2367 default:
2368 /* Only 2 channels are supported per fetch engine. */
2369 assert(false);
2370 break;
2371 }
2372 }
2373 }
2374 else
2375 {
2376 if (name == kPXP_StoreInput)
2377 {
2378 switch (channel)
2379 {
2380 case 0:
2381 base->INPUT_STORE_CTRL_CH0_CLR = PXP_INPUT_STORE_CTRL_CH0_CH_EN_MASK;
2382 break;
2383
2384 case 1:
2385 base->INPUT_STORE_CTRL_CH1_CLR = PXP_INPUT_STORE_CTRL_CH1_CH_EN_MASK;
2386 break;
2387
2388 default:
2389 /* Only 2 channels are supported per fetch engine. */
2390 assert(false);
2391 break;
2392 }
2393 }
2394 else
2395 {
2396 switch (channel)
2397 {
2398 case 0:
2399 base->DITHER_STORE_CTRL_CH0_CLR = PXP_DITHER_STORE_CTRL_CH0_CH_EN_MASK;
2400 break;
2401
2402 case 1:
2403 base->DITHER_STORE_CTRL_CH1_CLR = PXP_DITHER_STORE_CTRL_CH1_CH_EN_MASK;
2404 break;
2405
2406 default:
2407 /* Only 2 channels are supported per fetch engine. */
2408 assert(false);
2409 break;
2410 }
2411 }
2412 }
2413}
2414
2425static inline void PXP_CombineStoreEngineChannel(PXP_Type *base, pxp_store_engine_name_t name, bool combine)
2426{
2427 if (name == kPXP_StoreInput)
2428 {
2429 if (combine)
2430 {
2431 base->INPUT_STORE_CTRL_CH0_SET = PXP_INPUT_STORE_CTRL_CH0_SET_COMBINE_2CHANNEL_MASK;
2432 }
2433 else
2434 {
2435 base->INPUT_STORE_CTRL_CH0_CLR = PXP_INPUT_STORE_CTRL_CH0_SET_COMBINE_2CHANNEL_MASK;
2436 }
2437 }
2438 else
2439 {
2440 if (combine)
2441 {
2442 base->DITHER_STORE_CTRL_CH0_SET = PXP_DITHER_STORE_CTRL_CH0_SET_COMBINE_2CHANNEL_MASK;
2443 }
2444 else
2445 {
2446 base->DITHER_STORE_CTRL_CH0_CLR = PXP_DITHER_STORE_CTRL_CH0_SET_COMBINE_2CHANNEL_MASK;
2447 }
2448 }
2449}
2450/* @} */
2451
2464status_t PXP_SetCfaConfig(PXP_Type *base, const pxp_cfa_config_t *config);
2465
2472static inline void PXP_EnableCfa(PXP_Type *base, bool enable)
2473{
2474 if (enable)
2475 {
2476 base->CFA_CTRL_CLR = PXP_CFA_CTRL_CFA_BYPASS_MASK;
2477 }
2478 else
2479 {
2480 base->CFA_CTRL_SET = PXP_CFA_CTRL_CFA_BYPASS_MASK;
2481 }
2482}
2483/* @} */
2484
2498status_t PXP_SetHistogramConfig(PXP_Type *base, uint8_t num, const pxp_histogram_config_t *config);
2499
2507static inline void PXP_EnableHistogram(PXP_Type *base, uint8_t num, bool enable)
2508{
2509 switch (num)
2510 {
2511 case 0:
2512 base->HIST_A_CTRL =
2513 (base->HIST_A_CTRL & ~PXP_HIST_A_CTRL_ENABLE_MASK) | PXP_HIST_A_CTRL_ENABLE((uint32_t)enable);
2514 break;
2515
2516 case 1:
2517 base->HIST_B_CTRL =
2518 (base->HIST_B_CTRL & ~PXP_HIST_B_CTRL_ENABLE_MASK) | PXP_HIST_B_CTRL_ENABLE((uint32_t)enable);
2519 break;
2520
2521 default:
2522 /* Only 2 instances are supported per fetch engine. */
2523 assert(false);
2524 break;
2525 }
2526}
2527
2535void PXP_GetHistogramMaskResult(PXP_Type *base, uint8_t num, pxp_histogram_mask_result_t *result);
2536
2544static inline uint8_t PXP_GetHistogramMatchResult(PXP_Type *base, uint8_t num)
2545{
2546 uint8_t result = 0U;
2547 switch (num)
2548 {
2549 case 0:
2550 result = (uint8_t)((base->HIST_A_CTRL & PXP_HIST_A_CTRL_STATUS_MASK) >> PXP_HIST_A_CTRL_STATUS_SHIFT);
2551 break;
2552
2553 case 1:
2554 result = (uint8_t)((base->HIST_B_CTRL & PXP_HIST_B_CTRL_STATUS_MASK) >> PXP_HIST_B_CTRL_STATUS_SHIFT);
2555 break;
2556
2557 default:
2558 /* Only 2 histogram instances are supported. */
2559 assert(false);
2560 break;
2561 }
2562
2563 return result;
2564}
2565
2575static inline void PXP_ClearHistogramResult(PXP_Type *base, uint8_t num)
2576{
2577 switch (num)
2578 {
2579 case 0:
2580 base->HIST_A_CTRL |= PXP_HIST_A_CTRL_CLEAR_MASK;
2581 break;
2582
2583 case 1:
2584 base->HIST_B_CTRL |= PXP_HIST_B_CTRL_CLEAR_MASK;
2585 break;
2586
2587 default:
2588 /* Only 2 histogram instances are supported. */
2589 assert(false);
2590 break;
2591 }
2592}
2593
2602static inline void PXP_SetHistogramSize(PXP_Type *base, uint8_t num, uint16_t width, uint16_t height)
2603{
2604 switch (num)
2605 {
2606 case 0:
2607 base->HIST_A_BUF_SIZE = ((uint32_t)height << 16U) | (uint32_t)width;
2608 break;
2609
2610 case 1:
2611 base->HIST_B_BUF_SIZE = ((uint32_t)height << 16U) | (uint32_t)width;
2612 break;
2613
2614 default:
2615 /* Only 2 histogram instances are supported. */
2616 assert(false);
2617 break;
2618 }
2619}
2620/* @} */
2621
2633void PXP_WfeaInit(PXP_Type *base, bool ditherHandshake);
2634
2641static inline void PXP_WfeaEnableDitherHandshake(PXP_Type *base, bool enable)
2642{
2643 if (enable)
2644 {
2645 base->WFA_FETCH_CTRL |= PXP_WFA_FETCH_CTRL_BF1_HSK_MODE_MASK;
2646 }
2647 else
2648 {
2649 base->WFA_FETCH_CTRL &= ~PXP_WFA_FETCH_CTRL_BF1_HSK_MODE_MASK;
2650 }
2651}
2652
2659void PXP_SetWfeaConfig(PXP_Type *base, const pxp_wfea_engine_config_t *config);
2660
2670static inline void PXP_SetLutUsage(PXP_Type *base, uint64_t lutStatus)
2671{
2672 base->WFE_A_STG1_8X1_OUT0_0 |= (uint32_t)lutStatus;
2673 base->WFE_A_STG1_8X1_OUT0_1 |= (uint32_t)(lutStatus >> 32U);
2674}
2675
2685static inline void PXP_ClearLutUsage(PXP_Type *base, uint64_t lutStatus)
2686{
2687 base->WFE_A_STG1_8X1_OUT0_0 &= ~(uint32_t)lutStatus;
2688 base->WFE_A_STG1_8X1_OUT0_1 &= ~(uint32_t)(lutStatus >> 32U);
2689}
2690
2697static inline uint64_t PXP_GetLutUsage(PXP_Type *base)
2698{
2699 return ((uint64_t)base->WFE_A_STG1_8X1_OUT0_0 | (uint64_t)base->WFE_A_STG1_8X1_OUT0_1 << 32U);
2700}
2701
2702/* @} */
2703
2704#endif /* FSL_FEATURE_PXP_V3 */
2705
2706#if defined(__cplusplus)
2707}
2708#endif
2709
2712#endif /* _FSL_PXP_H_ */
#define PXP_AS_CTRL_ENABLE_COLORKEY(x)
Definition: MIMXRT1052.h:39098
#define PXP_CTRL_BLOCK_SIZE(x)
Definition: MIMXRT1052.h:37977
#define PXP_CTRL_ROTATE(x)
Definition: MIMXRT1052.h:37949
int32_t status_t
Type used for all status and error return values.
Definition: fsl_common.h:225
void PXP_SetProcessSurfacePosition(PXP_Type *base, uint16_t upperLeftX, uint16_t upperLeftY, uint16_t lowerRightX, uint16_t lowerRightY)
Set the process surface position in output buffer.
Definition: fsl_pxp.c:538
enum _pxp_interlaced_output_mode pxp_interlaced_output_mode_t
PXP interlaced output mode.
void PXP_Reset(PXP_Type *base)
Reset the PXP.
Definition: fsl_pxp.c:337
void PXP_ResetControl(PXP_Type *base)
Reset the PXP and the control register to initialized state.
Definition: fsl_pxp.c:268
uint32_t srcGlobalAlpha
Definition: fsl_pxp.h:691
void PXP_SetProcessSurfaceScaler(PXP_Type *base, uint16_t inputWidth, uint16_t inputHeight, uint16_t outputWidth, uint16_t outputHeight)
Set the process surface scaler configuration.
Definition: fsl_pxp.c:514
uint32_t enableDither0
Definition: fsl_pxp.h:609
void PXP_SetLutConfig(PXP_Type *base, const pxp_lut_config_t *config)
Set the LUT configuration.
Definition: fsl_pxp.c:854
pxp_alpha_mode_t alphaMode
Definition: fsl_pxp.h:443
_pxp_ps_yuv_format
PXP process surface buffer YUV format.
Definition: fsl_pxp.h:360
uint16_t destOffsetY
Definition: fsl_pxp.h:722
void PXP_SetAlphaSurfaceBlendConfig(PXP_Type *base, const pxp_as_blend_config_t *config)
Set the alpha surface blending configuration.
Definition: fsl_pxp.c:365
void PXP_SetProcessSurfaceColorKey(PXP_Type *base, uint32_t colorKeyLow, uint32_t colorKeyHigh)
Set the process surface color key.
Definition: fsl_pxp.c:588
_pxp_csc1_mode
PXP CSC1 mode.
Definition: fsl_pxp.h:468
void PXP_SetNextCommand(PXP_Type *base, void *commandAddr)
Set the next command.
Definition: fsl_pxp.c:736
void PXP_SetCsc1Mode(PXP_Type *base, pxp_csc1_mode_t mode)
Set the CSC1 mode.
Definition: fsl_pxp.c:804
uint16_t destOffsetX
Definition: fsl_pxp.h:721
_pxp_rop_mode
PXP ROP mode during blending.
Definition: fsl_pxp.h:420
uint16_t width
Definition: fsl_pxp.h:334
uint32_t idxMatrixSize0
Definition: fsl_pxp.h:619
_pxp_lut_lookup_mode
PXP LUT lookup mode.
Definition: fsl_pxp.h:519
uint32_t srcPicBaseAddr
Definition: fsl_pxp.h:715
_pxp_csc2_mode
PXP CSC2 mode.
Definition: fsl_pxp.h:475
uint16_t srcPitchBytes
Definition: fsl_pxp.h:716
uint32_t buffer0Addr
Definition: fsl_pxp.h:330
uint16_t width
Definition: fsl_pxp.h:723
pxp_csc2_mode_t mode
Definition: fsl_pxp.h:501
uint32_t bufferAddrU
Definition: fsl_pxp.h:371
float A3
Definition: fsl_pxp.h:504
uint32_t buffer1Addr
Definition: fsl_pxp.h:331
uint32_t ditherMode0
Definition: fsl_pxp.h:612
_pxp_flags
PXP status flags.
Definition: fsl_pxp.h:125
void PXP_Init(PXP_Type *base)
Initialize the PXP.
Definition: fsl_pxp.c:302
int16_t D1
Definition: fsl_pxp.h:511
void PXP_SetOutputBufferConfig(PXP_Type *base, const pxp_output_buffer_config_t *config)
Set the PXP outpt buffer configuration.
Definition: fsl_pxp.c:601
_pxp_dither_matrix_size
PXP dither matrix size.
Definition: fsl_pxp.h:591
pxp_as_pixel_format_t pixelFormat
Definition: fsl_pxp.h:391
uint32_t dstColorMode
Definition: fsl_pxp.h:682
uint32_t idxMatrixSize2
Definition: fsl_pxp.h:623
enum _pxp_rotate_position pxp_rotate_position_t
PXP rotate mode.
enum _pxp_flip_mode pxp_flip_mode_t
PXP output flip mode.
status_t PXP_LoadLutTable(PXP_Type *base, pxp_lut_lookup_mode_t lookupMode, uint32_t bytesNum, uint32_t memAddr, uint16_t lutStartAddr)
Set the look up table to PXP.
Definition: fsl_pxp.c:888
status_t PXP_StartPictureCopy(PXP_Type *base, const pxp_pic_copy_config_t *config)
Copy picture from one buffer to another buffer.
Definition: fsl_pxp.c:1219
float C3
Definition: fsl_pxp.h:510
_pxp_rotate_degree
PXP rotate degree.
Definition: fsl_pxp.h:287
float A2
Definition: fsl_pxp.h:503
_pxp_as_pixel_format
PXP alpha surface buffer pixel format.
Definition: fsl_pxp.h:378
uint32_t dstAlphaMode
Definition: fsl_pxp.h:681
void PXP_SetPorterDuffConfig(PXP_Type *base, const pxp_porter_duff_config_t *config)
Set the Porter Duff configuration.
Definition: fsl_pxp.c:1046
uint16_t pitchBytes
Definition: fsl_pxp.h:333
enum _pxp_csc2_mode pxp_csc2_mode_t
PXP CSC2 mode.
_pxp_alpha_mode
PXP alpha mode during blending.
Definition: fsl_pxp.h:400
int16_t D2
Definition: fsl_pxp.h:512
_pxp_output_pixel_format
PXP output buffer format.
Definition: fsl_pxp.h:305
float B2
Definition: fsl_pxp.h:506
struct _pxp_lut_config pxp_lut_config_t
PXP LUT configuration.
uint32_t bufferAddrV
Definition: fsl_pxp.h:372
int16_t D3
Definition: fsl_pxp.h:513
uint32_t srcFactorMode
Definition: fsl_pxp.h:678
pxp_rop_mode_t ropMode
Definition: fsl_pxp.h:444
enum _pxp_lut_out_mode pxp_lut_out_mode_t
PXP LUT output mode.
uint32_t bufferAddr
Definition: fsl_pxp.h:392
enum _pxp_output_pixel_format pxp_output_pixel_format_t
PXP output buffer format.
uint32_t enable
Definition: fsl_pxp.h:677
_pxp_interrupt_enable
PXP interrupts to enable.
Definition: fsl_pxp.h:76
struct _pxp_csc2_config pxp_csc2_config_t
PXP CSC2 configuration.
uint32_t enableDither1
Definition: fsl_pxp.h:610
enum _pxp_ram pxp_ram_t
PXP internal memory.
float A1
Definition: fsl_pxp.h:502
uint32_t bufferAddr
Definition: fsl_pxp.h:370
uint16_t pitchBytes
Definition: fsl_pxp.h:393
uint16_t srcOffsetX
Definition: fsl_pxp.h:717
pxp_lut_lookup_mode_t lookupMode
Definition: fsl_pxp.h:547
uint32_t data_15_12
Definition: fsl_pxp.h:603
uint8_t alpha
Definition: fsl_pxp.h:440
enum _pxp_rop_mode pxp_rop_mode_t
PXP ROP mode during blending.
pxp_ps_pixel_format_t pixelFormat
Definition: fsl_pxp.h:368
uint32_t data_3_0
Definition: fsl_pxp.h:600
enum _pxp_as_pixel_format pxp_as_pixel_format_t
PXP alpha surface buffer pixel format.
uint32_t lutMode
Definition: fsl_pxp.h:616
uint32_t quantBitNum
Definition: fsl_pxp.h:615
enum _pxp_porter_duff_blend_mode pxp_porter_duff_blend_mode_t
PXP Porter Duff blend mode. Note: don't change the enum item value.
pxp_output_pixel_format_t pixelFormat
Definition: fsl_pxp.h:328
_pxp_ram
PXP internal memory.
Definition: fsl_pxp.h:555
status_t PXP_StartMemCopy(PXP_Type *base, uint32_t srcAddr, uint32_t destAddr, uint32_t size)
Copy continous memory.
Definition: fsl_pxp.c:1259
_pxp_dither_mode
PXP dither mode.
Definition: fsl_pxp.h:571
enum _pxp_rotate_degree pxp_rotate_degree_t
PXP rotate degree.
uint32_t enableDither2
Definition: fsl_pxp.h:611
_pxp_lut_out_mode
PXP LUT output mode.
Definition: fsl_pxp.h:531
enum _pxp_block_size pxp_block_size_t
PXP process block size.
void PXP_SetProcessSurfaceBufferConfig(PXP_Type *base, const pxp_ps_buffer_config_t *config)
Set the process surface input buffer configuration.
Definition: fsl_pxp.c:490
uint32_t cfaValue
Definition: fsl_pxp.h:549
void PXP_SetAlphaSurfacePosition(PXP_Type *base, uint16_t upperLeftX, uint16_t upperLeftY, uint16_t lowerRightX, uint16_t lowerRightY)
Set the alpha surface position in output buffer.
Definition: fsl_pxp.c:419
enum _pxp_ps_yuv_format pxp_ps_yuv_format_t
PXP process surface buffer YUV format.
struct _pxp_dither_config pxp_dither_config_t
PXP dither configuration.
uint16_t height
Definition: fsl_pxp.h:335
status_t PXP_MemCopy(PXP_Type *base, uint32_t srcAddr, uint32_t destAddr, uint32_t size)
Copy continous memory.
Definition: fsl_pxp.c:1302
void PXP_SetCsc2Config(PXP_Type *base, const pxp_csc2_config_t *config)
Set the CSC2 configuration.
Definition: fsl_pxp.c:759
_pxp_flip_mode
PXP output flip mode.
Definition: fsl_pxp.h:271
uint32_t dstFactorMode
Definition: fsl_pxp.h:684
enum _pxp_alpha_mode pxp_alpha_mode_t
PXP alpha mode during blending.
float C1
Definition: fsl_pxp.h:508
uint32_t enableFinalLut
Definition: fsl_pxp.h:625
pxp_as_pixel_format_t pixelFormat
Definition: fsl_pxp.h:725
uint32_t dstGlobalAlpha
Definition: fsl_pxp.h:690
enum _pxp_csc1_mode pxp_csc1_mode_t
PXP CSC1 mode.
uint32_t srcAlphaMode
Definition: fsl_pxp.h:687
uint32_t data_11_8
Definition: fsl_pxp.h:602
_pxp_dither_lut_mode
PXP dither LUT mode.
Definition: fsl_pxp.h:582
uint32_t ditherMode2
Definition: fsl_pxp.h:614
float B3
Definition: fsl_pxp.h:507
uint32_t idxMatrixSize1
Definition: fsl_pxp.h:621
_pxp_interlaced_output_mode
PXP interlaced output mode.
Definition: fsl_pxp.h:296
struct _pxp_dither_final_lut_data pxp_dither_final_lut_data_t
PXP dither final LUT data.
_pxp_block_size
PXP process block size.
Definition: fsl_pxp.h:461
uint32_t data_7_4
Definition: fsl_pxp.h:601
uint16_t destPitchBytes
Definition: fsl_pxp.h:720
bool invertAlpha
Definition: fsl_pxp.h:442
enum _pxp_lut_8k_bank pxp_lut_8k_bank_t
PXP LUT 8K bank index used when lookup mode is kPXP_LutDirectRGB444.
enum _pxp_ps_pixel_format pxp_ps_pixel_format_t
PXP process surface buffer pixel format.
void PXP_SetAlphaSurfaceBufferConfig(PXP_Type *base, const pxp_as_buffer_config_t *config)
Set the alpha surface input buffer configuration.
Definition: fsl_pxp.c:349
uint32_t dstGlobalAlphaMode
Definition: fsl_pxp.h:679
bool swapByte
Definition: fsl_pxp.h:369
void PXP_SetAlphaSurfaceOverlayColorKey(PXP_Type *base, uint32_t colorKeyLow, uint32_t colorKeyHigh)
Set the alpha surface overlay color key.
Definition: fsl_pxp.c:477
float B1
Definition: fsl_pxp.h:505
uint32_t destPicBaseAddr
Definition: fsl_pxp.h:719
uint32_t srcGlobalAlphaMode
Definition: fsl_pxp.h:685
_pxp_ps_pixel_format
PXP process surface buffer pixel format.
Definition: fsl_pxp.h:340
uint16_t srcOffsetY
Definition: fsl_pxp.h:718
_pxp_porter_duff_blend_mode
PXP Porter Duff blend mode. Note: don't change the enum item value.
Definition: fsl_pxp.h:696
status_t PXP_GetPorterDuffConfig(pxp_porter_duff_blend_mode_t mode, pxp_porter_duff_config_t *config)
Get the Porter Duff configuration by blend mode.
Definition: fsl_pxp.c:1072
struct _pxp_ps_buffer_config pxp_ps_buffer_config_t
PXP process surface buffer configuration.
uint16_t pitchBytes
Definition: fsl_pxp.h:373
uint32_t ditherMode1
Definition: fsl_pxp.h:613
void PXP_Deinit(PXP_Type *base)
De-initialize the PXP.
Definition: fsl_pxp.c:322
_pxp_rotate_position
PXP rotate mode.
Definition: fsl_pxp.h:280
float C2
Definition: fsl_pxp.h:509
struct _pxp_as_blend_config pxp_as_blend_config_t
PXP alpha surface blending configuration.
pxp_interlaced_output_mode_t interlacedMode
Definition: fsl_pxp.h:329
uint32_t srcColorMode
Definition: fsl_pxp.h:688
struct _pxp_as_buffer_config pxp_as_buffer_config_t
PXP alphs surface buffer configuration.
uint16_t height
Definition: fsl_pxp.h:724
_pxp_lut_8k_bank
PXP LUT 8K bank index used when lookup mode is kPXP_LutDirectRGB444.
Definition: fsl_pxp.h:539
struct _pxp_pic_copy_config pxp_pic_copy_config_t
PXP Porter Duff blend mode. Note: don't change the enum item value.
void PXP_BuildRect(PXP_Type *base, pxp_output_pixel_format_t outFormat, uint32_t value, uint16_t width, uint16_t height, uint16_t pitch, uint32_t outAddr)
Build a solid rectangle of given pixel value.
Definition: fsl_pxp.c:635
pxp_lut_out_mode_t outMode
Definition: fsl_pxp.h:548
struct _pxp_output_buffer_config pxp_output_buffer_config_t
PXP output buffer configuration.
enum _pxp_lut_lookup_mode pxp_lut_lookup_mode_t
PXP LUT lookup mode.
@ kPXP_PsYUVFormatYUV
Definition: fsl_pxp.h:361
@ kPXP_PsYUVFormatYCbCr
Definition: fsl_pxp.h:362
@ kPXP_Csc1YCbCr2RGB
Definition: fsl_pxp.h:470
@ kPXP_Csc1YUV2RGB
Definition: fsl_pxp.h:469
@ kPXP_PorterDuffColorWithAlpha
Definition: fsl_pxp.h:671
@ kPXP_PorterDuffColorNoAlpha
Definition: fsl_pxp.h:670
@ kPXP_PorterDuffColorStraight
Definition: fsl_pxp.h:668
@ kPXP_PorterDuffColorInversed
Definition: fsl_pxp.h:669
@ kPXP_RopMergeAsNot
Definition: fsl_pxp.h:426
@ kPXP_RopMaskAsNot
Definition: fsl_pxp.h:423
@ kPXP_RopXorAs
Definition: fsl_pxp.h:431
@ kPXP_RopMergeNotAs
Definition: fsl_pxp.h:425
@ kPXP_RopMergeAs
Definition: fsl_pxp.h:424
@ kPXP_RopNotMergeAs
Definition: fsl_pxp.h:430
@ kPXP_RopNotMaskAs
Definition: fsl_pxp.h:429
@ kPXP_RopNotCopyAs
Definition: fsl_pxp.h:427
@ kPXP_RopNotXorAs
Definition: fsl_pxp.h:432
@ kPXP_RopMaskAs
Definition: fsl_pxp.h:421
@ kPXP_RopMaskNotAs
Definition: fsl_pxp.h:422
@ kPXP_RopNot
Definition: fsl_pxp.h:428
@ kPXP_PorterDuffAlphaStraight
Definition: fsl_pxp.h:658
@ kPXP_PorterDuffAlphaInversed
Definition: fsl_pxp.h:659
@ kPXP_LutDirectRGB454
Definition: fsl_pxp.h:526
@ kPXP_LutDirectY8
Definition: fsl_pxp.h:522
@ kPXP_LutDirectRGB444
Definition: fsl_pxp.h:524
@ kPXP_LutCacheRGB565
Definition: fsl_pxp.h:520
@ kPXP_Csc2YCbCr2RGB
Definition: fsl_pxp.h:477
@ kPXP_Csc2YUV2RGB
Definition: fsl_pxp.h:476
@ kPXP_Csc2RGB2YCbCr
Definition: fsl_pxp.h:479
@ kPXP_Csc2RGB2YUV
Definition: fsl_pxp.h:478
@ kPXP_Axi0ReadErrorFlag
Definition: fsl_pxp.h:129
@ kPXP_CompleteFlag
Definition: fsl_pxp.h:126
@ kPXP_Axi0WriteErrorFlag
Definition: fsl_pxp.h:127
@ kPXP_LutDmaLoadFlag
Definition: fsl_pxp.h:134
@ kPXP_CommandLoadFlag
Definition: fsl_pxp.h:131
@ kPXP_DitherMatrix8
Definition: fsl_pxp.h:593
@ kPXP_DitherMatrix16
Definition: fsl_pxp.h:594
@ kPXP_DitherMatrix4
Definition: fsl_pxp.h:592
@ kPXP_PorterDuffFactorInversed
Definition: fsl_pxp.h:638
@ kPXP_PorterDuffFactorZero
Definition: fsl_pxp.h:636
@ kPXP_PorterDuffFactorStraight
Definition: fsl_pxp.h:637
@ kPXP_PorterDuffFactorOne
Definition: fsl_pxp.h:635
@ kPXP_Rotate270
Definition: fsl_pxp.h:291
@ kPXP_Rotate0
Definition: fsl_pxp.h:288
@ kPXP_Rotate180
Definition: fsl_pxp.h:290
@ kPXP_Rotate90
Definition: fsl_pxp.h:289
@ kPXP_AsPixelFormatARGB4444
Definition: fsl_pxp.h:382
@ kPXP_AsPixelFormatRGB565
Definition: fsl_pxp.h:385
@ kPXP_AsPixelFormatRGB555
Definition: fsl_pxp.h:383
@ kPXP_AsPixelFormatARGB1555
Definition: fsl_pxp.h:381
@ kPXP_AsPixelFormatRGB888
Definition: fsl_pxp.h:380
@ kPXP_AsPixelFormatARGB8888
Definition: fsl_pxp.h:379
@ kPXP_AsPixelFormatRGB444
Definition: fsl_pxp.h:384
@ kPXP_AlphaOverride
Definition: fsl_pxp.h:402
@ kPXP_AlphaMultiply
Definition: fsl_pxp.h:403
@ kPXP_AlphaRop
Definition: fsl_pxp.h:407
@ kPXP_AlphaEmbedded
Definition: fsl_pxp.h:401
@ kPXP_OutputPixelFormatYVU2P420
Definition: fsl_pxp.h:322
@ kPXP_OutputPixelFormatYUV2P422
Definition: fsl_pxp.h:319
@ kPXP_OutputPixelFormatVYUY1P422
Definition: fsl_pxp.h:316
@ kPXP_OutputPixelFormatUYVY1P422
Definition: fsl_pxp.h:315
@ kPXP_OutputPixelFormatYVU2P422
Definition: fsl_pxp.h:321
@ kPXP_OutputPixelFormatY8
Definition: fsl_pxp.h:317
@ kPXP_OutputPixelFormatRGB444
Definition: fsl_pxp.h:312
@ kPXP_OutputPixelFormatRGB888
Definition: fsl_pxp.h:307
@ kPXP_OutputPixelFormatYUV2P420
Definition: fsl_pxp.h:320
@ kPXP_OutputPixelFormatARGB8888
Definition: fsl_pxp.h:306
@ kPXP_OutputPixelFormatRGB565
Definition: fsl_pxp.h:313
@ kPXP_OutputPixelFormatYUV1P444
Definition: fsl_pxp.h:314
@ kPXP_OutputPixelFormatRGB555
Definition: fsl_pxp.h:311
@ kPXP_OutputPixelFormatARGB4444
Definition: fsl_pxp.h:310
@ kPXP_OutputPixelFormatARGB1555
Definition: fsl_pxp.h:309
@ kPXP_OutputPixelFormatY4
Definition: fsl_pxp.h:318
@ kPXP_OutputPixelFormatRGB888P
Definition: fsl_pxp.h:308
@ kPXP_CompleteInterruptEnable
Definition: fsl_pxp.h:77
@ kPXP_CommandLoadInterruptEnable
Definition: fsl_pxp.h:78
@ kPXP_LutDmaLoadInterruptEnable
Definition: fsl_pxp.h:81
@ kPXP_RamDither0Lut
Definition: fsl_pxp.h:556
@ kPXP_RamDither1Lut
Definition: fsl_pxp.h:557
@ kPXP_RamDither2Lut
Definition: fsl_pxp.h:558
@ kPXP_DitherQuantOnly
Definition: fsl_pxp.h:576
@ kPXP_DitherOrdered
Definition: fsl_pxp.h:575
@ kPXP_DitherFloydSteinberg
Definition: fsl_pxp.h:573
@ kPXP_DitherSierra
Definition: fsl_pxp.h:577
@ kPXP_DitherAtkinson
Definition: fsl_pxp.h:574
@ kPXP_DitherPassThrough
Definition: fsl_pxp.h:572
@ kPXP_LutOutY8
Definition: fsl_pxp.h:532
@ kPXP_LutOutRGB888
Definition: fsl_pxp.h:534
@ kPXP_LutOutRGBW4444CFA
Definition: fsl_pxp.h:533
@ kPXP_FlipHorizontal
Definition: fsl_pxp.h:273
@ kPXP_FlipBoth
Definition: fsl_pxp.h:275
@ kPXP_FlipVertical
Definition: fsl_pxp.h:274
@ kPXP_FlipDisable
Definition: fsl_pxp.h:272
@ kPXP_DitherLutOff
Definition: fsl_pxp.h:583
@ kPXP_DitherLutPreDither
Definition: fsl_pxp.h:584
@ kPXP_DitherLutPostDither
Definition: fsl_pxp.h:586
@ kPXP_OutputField0
Definition: fsl_pxp.h:298
@ kPXP_OutputField1
Definition: fsl_pxp.h:299
@ kPXP_OutputProgressive
Definition: fsl_pxp.h:297
@ kPXP_OutputInterlaced
Definition: fsl_pxp.h:300
@ kPXP_BlockSize16
Definition: fsl_pxp.h:463
@ kPXP_BlockSize8
Definition: fsl_pxp.h:462
@ kPXP_PsPixelFormatYUV2P420
Definition: fsl_pxp.h:351
@ kPXP_PsPixelFormatYVU2P422
Definition: fsl_pxp.h:352
@ kPXP_PsPixelFormatYVU420
Definition: fsl_pxp.h:355
@ kPXP_PsPixelFormatVYUY1P422
Definition: fsl_pxp.h:347
@ kPXP_PsPixelFormatRGB888
Definition: fsl_pxp.h:341
@ kPXP_PsPixelFormatUYVY1P422
Definition: fsl_pxp.h:346
@ kPXP_PsPixelFormatYUV1P444
Definition: fsl_pxp.h:345
@ kPXP_PsPixelFormatYVU2P420
Definition: fsl_pxp.h:353
@ kPXP_PsPixelFormatY8
Definition: fsl_pxp.h:348
@ kPXP_PsPixelFormatYVU422
Definition: fsl_pxp.h:354
@ kPXP_PsPixelFormatRGB565
Definition: fsl_pxp.h:344
@ kPXP_PsPixelFormatRGB444
Definition: fsl_pxp.h:343
@ kPXP_PsPixelFormatY4
Definition: fsl_pxp.h:349
@ kPXP_PsPixelFormatYUV2P422
Definition: fsl_pxp.h:350
@ kPXP_PsPixelFormatRGB555
Definition: fsl_pxp.h:342
@ kPXP_PorterDuffDstOut
Definition: fsl_pxp.h:706
@ kPXP_PorterDuffIn
Definition: fsl_pxp.h:700
@ kPXP_PorterDuffDstAtop
Definition: fsl_pxp.h:703
@ kPXP_PorterDuffDstOver
Definition: fsl_pxp.h:704
@ kPXP_PorterDuffClear
Definition: fsl_pxp.h:708
@ kPXP_PorterDuffSrc
Definition: fsl_pxp.h:697
@ kPXP_PorterDuffAtop
Definition: fsl_pxp.h:698
@ kPXP_PorterDuffOut
Definition: fsl_pxp.h:701
@ kPXP_PorterDuffDst
Definition: fsl_pxp.h:702
@ kPXP_PorterDuffDstIn
Definition: fsl_pxp.h:705
@ kPXP_PorterDuffOver
Definition: fsl_pxp.h:699
@ kPXP_PorterDuffXor
Definition: fsl_pxp.h:707
@ kPXP_RotateOutputBuffer
Definition: fsl_pxp.h:281
@ kPXP_RotateProcessSurface
Definition: fsl_pxp.h:282
@ kPXP_Lut8kBank1
Definition: fsl_pxp.h:541
@ kPXP_Lut8kBank0
Definition: fsl_pxp.h:540
@ kPXP_PorterDuffLocalAlpha
Definition: fsl_pxp.h:648
@ kPXP_PorterDuffScaledAlpha
Definition: fsl_pxp.h:649
@ kPXP_PorterDuffGlobalAlpha
Definition: fsl_pxp.h:647
Definition: MIMXRT1052.h:37827
PXP alpha surface blending configuration.
Definition: fsl_pxp.h:439
PXP alphs surface buffer configuration.
Definition: fsl_pxp.h:390
PXP CSC2 configuration.
Definition: fsl_pxp.h:500
PXP dither configuration.
Definition: fsl_pxp.h:608
PXP dither final LUT data.
Definition: fsl_pxp.h:599
PXP LUT configuration.
Definition: fsl_pxp.h:546
PXP output buffer configuration.
Definition: fsl_pxp.h:327
PXP Porter Duff blend mode. Note: don't change the enum item value.
Definition: fsl_pxp.h:714
PXP process surface buffer configuration.
Definition: fsl_pxp.h:367
Definition: deflate.c:114
Definition: mknod-pack_dev.c:254
PXP Porter Duff configuration.
Definition: fsl_pxp.h:676