RTEMS 6.1-rc5
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erc32.h
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1
7/* erc32.h
8 *
9 * This include file contains information pertaining to the ERC32.
10 * The ERC32 is a custom SPARC V7 implementation based on the Cypress
11 * 601/602 chipset. This CPU has a number of on-board peripherals and
12 * was developed by the European Space Agency to target space applications.
13 *
14 * NOTE: Other than where absolutely required, this version currently
15 * supports only the peripherals and bits used by the basic board
16 * support package. This includes at least significant pieces of
17 * the following items:
18 *
19 * + UART Channels A and B
20 * + General Purpose Timer
21 * + Real Time Clock
22 * + Watchdog Timer (so it can be disabled)
23 * + Control Register (so powerdown mode can be enabled)
24 * + Memory Control Register
25 * + Interrupt Control
26 *
27 * COPYRIGHT (c) 1989-1999.
28 * On-Line Applications Research Corporation (OAR).
29 *
30 * The license and distribution terms for this file may be
31 * found in the file LICENSE in this distribution or at
32 * http://www.rtems.org/license/LICENSE.
33 *
34 * Ported to ERC32 implementation of the SPARC by On-Line Applications
35 * Research Corporation (OAR) under contract to the European Space
36 * Agency (ESA).
37 *
38 * ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995.
39 * European Space Agency.
40 */
41
42#ifndef _INCLUDE_ERC32_h
43#define _INCLUDE_ERC32_h
44
45#include <rtems/score/sparc.h>
46
47#ifdef __cplusplus
48extern "C" {
49#endif
50
51/*
52 * Interrupt Sources
53 *
54 * The interrupt source numbers directly map to the trap type and to
55 * the bits used in the Interrupt Clear, Interrupt Force, Interrupt Mask,
56 * and the Interrupt Pending Registers.
57 */
58
59#define ERC32_INTERRUPT_MASKED_ERRORS 1
60#define ERC32_INTERRUPT_EXTERNAL_1 2
61#define ERC32_INTERRUPT_EXTERNAL_2 3
62#define ERC32_INTERRUPT_UART_A_RX_TX 4
63#define ERC32_INTERRUPT_UART_B_RX_TX 5
64#define ERC32_INTERRUPT_CORRECTABLE_MEMORY_ERROR 6
65#define ERC32_INTERRUPT_UART_ERROR 7
66#define ERC32_INTERRUPT_DMA_ACCESS_ERROR 8
67#define ERC32_INTERRUPT_DMA_TIMEOUT 9
68#define ERC32_INTERRUPT_EXTERNAL_3 10
69#define ERC32_INTERRUPT_EXTERNAL_4 11
70#define ERC32_INTERRUPT_GENERAL_PURPOSE_TIMER 12
71#define ERC32_INTERRUPT_REAL_TIME_CLOCK 13
72#define ERC32_INTERRUPT_EXTERNAL_5 14
73#define ERC32_INTERRUPT_WATCHDOG_TIMEOUT 15
74
75#ifndef ASM
76
77/*
78 * Trap Types for on-chip peripherals
79 *
80 * Source: Table 8 - Interrupt Trap Type and Default Priority Assignments
81 *
82 * NOTE: The priority level for each source corresponds to the least
83 * significant nibble of the trap type.
84 */
85
86#define ERC32_TRAP_TYPE( _source ) SPARC_INTERRUPT_SOURCE_TO_TRAP( _source )
87
88#define ERC32_TRAP_SOURCE( _trap ) SPARC_INTERRUPT_TRAP_TO_SOURCE( _trap )
89
90#define ERC32_Is_MEC_Trap( _trap ) SPARC_IS_INTERRUPT_TRAP( _trap )
91
92/*
93 * Structure for ERC32 memory mapped registers.
94 *
95 * Source: Section 3.25.2 - Register Address Map
96 *
97 * NOTE: There is only one of these structures per CPU, its base address
98 * is 0x01f80000, and the variable MEC is placed there by the
99 * linkcmds file.
100 */
101
102typedef struct {
103 volatile uint32_t Control; /* offset 0x00 */
104 volatile uint32_t Software_Reset; /* offset 0x04 */
105 volatile uint32_t Power_Down; /* offset 0x08 */
106 volatile uint32_t Unimplemented_0; /* offset 0x0c */
107 volatile uint32_t Memory_Configuration; /* offset 0x10 */
108 volatile uint32_t IO_Configuration; /* offset 0x14 */
109 volatile uint32_t Wait_State_Configuration; /* offset 0x18 */
110 volatile uint32_t Unimplemented_1; /* offset 0x1c */
111 volatile uint32_t Memory_Access_0; /* offset 0x20 */
112 volatile uint32_t Memory_Access_1; /* offset 0x24 */
113 volatile uint32_t Unimplemented_2[ 7 ]; /* offset 0x28 */
114 volatile uint32_t Interrupt_Shape; /* offset 0x44 */
115 volatile uint32_t Interrupt_Pending; /* offset 0x48 */
116 volatile uint32_t Interrupt_Mask; /* offset 0x4c */
117 volatile uint32_t Interrupt_Clear; /* offset 0x50 */
118 volatile uint32_t Interrupt_Force; /* offset 0x54 */
119 volatile uint32_t Unimplemented_3[ 2 ]; /* offset 0x58 */
120 /* offset 0x60 */
121 volatile uint32_t Watchdog_Program_and_Timeout_Acknowledge;
122 volatile uint32_t Watchdog_Trap_Door_Set; /* offset 0x64 */
123 volatile uint32_t Unimplemented_4[ 6 ]; /* offset 0x68 */
124 volatile uint32_t Real_Time_Clock_Counter; /* offset 0x80 */
125 volatile uint32_t Real_Time_Clock_Scalar; /* offset 0x84 */
126 volatile uint32_t General_Purpose_Timer_Counter; /* offset 0x88 */
127 volatile uint32_t General_Purpose_Timer_Scalar; /* offset 0x8c */
128 volatile uint32_t Unimplemented_5[ 2 ]; /* offset 0x90 */
129 volatile uint32_t Timer_Control; /* offset 0x98 */
130 volatile uint32_t Unimplemented_6; /* offset 0x9c */
131 volatile uint32_t System_Fault_Status; /* offset 0xa0 */
132 volatile uint32_t First_Failing_Address; /* offset 0xa4 */
133 volatile uint32_t First_Failing_Data; /* offset 0xa8 */
134 volatile uint32_t First_Failing_Syndrome_and_Check_Bits;/* offset 0xac */
135 volatile uint32_t Error_and_Reset_Status; /* offset 0xb0 */
136 volatile uint32_t Error_Mask; /* offset 0xb4 */
137 volatile uint32_t Unimplemented_7[ 2 ]; /* offset 0xb8 */
138 volatile uint32_t Debug_Control; /* offset 0xc0 */
139 volatile uint32_t Breakpoint; /* offset 0xc4 */
140 volatile uint32_t Watchpoint; /* offset 0xc8 */
141 volatile uint32_t Unimplemented_8; /* offset 0xcc */
142 volatile uint32_t Test_Control; /* offset 0xd0 */
143 volatile uint32_t Test_Data; /* offset 0xd4 */
144 volatile uint32_t Unimplemented_9[ 2 ]; /* offset 0xd8 */
145 volatile uint32_t UART_Channel_A; /* offset 0xe0 */
146 volatile uint32_t UART_Channel_B; /* offset 0xe4 */
147 volatile uint32_t UART_Status; /* offset 0xe8 */
148} ERC32_Register_Map;
149
150#endif
151
152/*
153 * The following constants are intended to be used ONLY in assembly
154 * language files.
155 *
156 * NOTE: The intended style of usage is to load the address of MEC
157 * into a register and then use these as displacements from
158 * that register.
159 */
160
161#ifdef ASM
162
163#define ERC32_MEC_CONTROL_OFFSET 0x00
164#define ERC32_MEC_SOFTWARE_RESET_OFFSET 0x04
165#define ERC32_MEC_POWER_DOWN_OFFSET 0x08
166#define ERC32_MEC_UNIMPLEMENTED_0_OFFSET 0x0C
167#define ERC32_MEC_MEMORY_CONFIGURATION_OFFSET 0x10
168#define ERC32_MEC_IO_CONFIGURATION_OFFSET 0x14
169#define ERC32_MEC_WAIT_STATE_CONFIGURATION_OFFSET 0x18
170#define ERC32_MEC_UNIMPLEMENTED_1_OFFSET 0x1C
171#define ERC32_MEC_MEMORY_ACCESS_0_OFFSET 0x20
172#define ERC32_MEC_MEMORY_ACCESS_1_OFFSET 0x24
173#define ERC32_MEC_UNIMPLEMENTED_2_OFFSET 0x28
174#define ERC32_MEC_INTERRUPT_SHAPE_OFFSET 0x44
175#define ERC32_MEC_INTERRUPT_PENDING_OFFSET 0x48
176#define ERC32_MEC_INTERRUPT_MASK_OFFSET 0x4C
177#define ERC32_MEC_INTERRUPT_CLEAR_OFFSET 0x50
178#define ERC32_MEC_INTERRUPT_FORCE_OFFSET 0x54
179#define ERC32_MEC_UNIMPLEMENTED_3_OFFSET 0x58
180#define ERC32_MEC_WATCHDOG_PROGRAM_AND_TIMEOUT_ACKNOWLEDGE_OFFSET 0x60
181#define ERC32_MEC_WATCHDOG_TRAP_DOOR_SET_OFFSET 0x64
182#define ERC32_MEC_UNIMPLEMENTED_4_OFFSET 0x6C
183#define ERC32_MEC_REAL_TIME_CLOCK_COUNTER_OFFSET 0x80
184#define ERC32_MEC_REAL_TIME_CLOCK_SCALAR_OFFSET 0x84
185#define ERC32_MEC_GENERAL_PURPOSE_TIMER_COUNTER_OFFSET 0x88
186#define ERC32_MEC_GENERAL_PURPOSE_TIMER_SCALAR_OFFSET 0x8C
187#define ERC32_MEC_UNIMPLEMENTED_5_OFFSET 0x90
188#define ERC32_MEC_TIMER_CONTROL_OFFSET 0x98
189#define ERC32_MEC_UNIMPLEMENTED_6_OFFSET 0x9C
190#define ERC32_MEC_SYSTEM_FAULT_STATUS_OFFSET 0xA0
191#define ERC32_MEC_FIRST_FAILING_ADDRESS_OFFSET 0xA4
192#define ERC32_MEC_FIRST_FAILING_DATA_OFFSET 0xA8
193#define ERC32_MEC_FIRST_FAILING_SYNDROME_AND_CHECK_BITS_OFFSET 0xAC
194#define ERC32_MEC_ERROR_AND_RESET_STATUS_OFFSET 0xB0
195#define ERC32_MEC_ERROR_MASK_OFFSET 0xB4
196#define ERC32_MEC_UNIMPLEMENTED_7_OFFSET 0xB8
197#define ERC32_MEC_DEBUG_CONTROL_OFFSET 0xC0
198#define ERC32_MEC_BREAKPOINT_OFFSET 0xC4
199#define ERC32_MEC_WATCHPOINT_OFFSET 0xC8
200#define ERC32_MEC_UNIMPLEMENTED_8_OFFSET 0xCC
201#define ERC32_MEC_TEST_CONTROL_OFFSET 0xD0
202#define ERC32_MEC_TEST_DATA_OFFSET 0xD4
203#define ERC32_MEC_UNIMPLEMENTED_9_OFFSET 0xD8
204#define ERC32_MEC_UART_CHANNEL_A_OFFSET 0xE0
205#define ERC32_MEC_UART_CHANNEL_B_OFFSET 0xE4
206#define ERC32_MEC_UART_STATUS_OFFSET 0xE8
207
208#endif
209
210/*
211 * The following defines the bits in the Configuration Register.
212 */
213
214#define ERC32_CONFIGURATION_POWER_DOWN_MASK 0x00000001
215#define ERC32_CONFIGURATION_POWER_DOWN_ALLOWED 0x00000001
216#define ERC32_CONFIGURATION_POWER_DOWN_DISABLED 0x00000000
217
218#define ERC32_CONFIGURATION_SOFTWARE_RESET_MASK 0x00000002
219#define ERC32_CONFIGURATION_SOFTWARE_RESET_ALLOWED 0x00000002
220#define ERC32_CONFIGURATION_SOFTWARE_RESET_DISABLED 0x00000000
221
222#define ERC32_CONFIGURATION_BUS_TIMEOUT_MASK 0x00000004
223#define ERC32_CONFIGURATION_BUS_TIMEOUT_ENABLED 0x00000004
224#define ERC32_CONFIGURATION_BUS_TIMEOUT_DISABLED 0x00000000
225
226#define ERC32_CONFIGURATION_ACCESS_PROTECTION_MASK 0x00000008
227#define ERC32_CONFIGURATION_ACCESS_PROTECTION_ENABLED 0x00000008
228#define ERC32_CONFIGURATION_ACCESS_PROTECTION_DISABLED 0x00000000
229
230/*
231 * The following defines the bits in the Memory Configuration Register.
232 */
233
234#define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_MASK 0x00001C00
235#define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_256K ( 0 << 10 )
236#define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_512K ( 1 << 10 )
237#define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_1MB ( 2 << 10 )
238#define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_2MB ( 3 << 10 )
239#define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_4MB ( 4 << 10 )
240#define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_8MB ( 5 << 10 )
241#define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_16MB ( 6 << 10 )
242#define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_32MB ( 7 << 10 )
243
244#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_MASK 0x001C0000
245#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_128K ( 0 << 18 )
246#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_256K ( 1 << 18 )
247#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_512K ( 2 << 18 )
248#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_1M ( 3 << 18 )
249#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_2M ( 4 << 18 )
250#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_4M ( 5 << 18 )
251#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_8M ( 6 << 18 )
252#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_16M ( 7 << 18 )
253
254/*
255 * The following defines the bits in the Timer Control Register.
256 */
257
258#define ERC32_MEC_TIMER_CONTROL_GCR 0x00000001 /* 1 = reload at 0 */
259 /* 0 = stop at 0 */
260#define ERC32_MEC_TIMER_CONTROL_GCL 0x00000002 /* 1 = load and start */
261 /* 0 = no function */
262#define ERC32_MEC_TIMER_CONTROL_GSE 0x00000004 /* 1 = enable counting */
263 /* 0 = hold scalar and counter */
264#define ERC32_MEC_TIMER_CONTROL_GSL 0x00000008 /* 1 = load scalar and start*/
265 /* 0 = no function */
266
267#define ERC32_MEC_TIMER_CONTROL_RTCCR 0x00000100 /* 1 = reload at 0 */
268 /* 0 = stop at 0 */
269#define ERC32_MEC_TIMER_CONTROL_RTCCL 0x00000200 /* 1 = load and start */
270 /* 0 = no function */
271#define ERC32_MEC_TIMER_CONTROL_RTCSE 0x00000400 /* 1 = enable counting */
272 /* 0 = hold scalar and counter */
273#define ERC32_MEC_TIMER_CONTROL_RTCSL 0x00000800 /* 1 = load scalar and start*/
274 /* 0 = no function */
275
276/*
277 * The following defines the bits in the UART Control Registers.
278 *
279 */
280
281#define ERC32_MEC_UART_CONTROL_RTD 0x000000FF /* RX/TX data */
282
283/*
284 * The following defines the bits in the MEC UART Control Registers.
285 */
286
287#define ERC32_MEC_UART_STATUS_DR 0x00000001 /* Data Ready */
288#define ERC32_MEC_UART_STATUS_TSE 0x00000002 /* TX Send Register Empty */
289#define ERC32_MEC_UART_STATUS_THE 0x00000004 /* TX Hold Register Empty */
290#define ERC32_MEC_UART_STATUS_FE 0x00000010 /* RX Framing Error */
291#define ERC32_MEC_UART_STATUS_PE 0x00000020 /* RX Parity Error */
292#define ERC32_MEC_UART_STATUS_OE 0x00000040 /* RX Overrun Error */
293#define ERC32_MEC_UART_STATUS_CU 0x00000080 /* Clear Errors */
294#define ERC32_MEC_UART_STATUS_TXE 0x00000006 /* TX Empty */
295#define ERC32_MEC_UART_STATUS_CLRA 0x00000080 /* Clear UART A */
296#define ERC32_MEC_UART_STATUS_CLRB 0x00800000 /* Clear UART B */
297#define ERC32_MEC_UART_STATUS_ERRA 0x00000070 /* Error in UART A */
298#define ERC32_MEC_UART_STATUS_ERRB 0x00700000 /* Error in UART B */
299
300#define ERC32_MEC_UART_STATUS_DRA (ERC32_MEC_UART_STATUS_DR << 0)
301#define ERC32_MEC_UART_STATUS_TSEA (ERC32_MEC_UART_STATUS_TSE << 0)
302#define ERC32_MEC_UART_STATUS_THEA (ERC32_MEC_UART_STATUS_THE << 0)
303#define ERC32_MEC_UART_STATUS_FEA (ERC32_MEC_UART_STATUS_FE << 0)
304#define ERC32_MEC_UART_STATUS_PEA (ERC32_MEC_UART_STATUS_PE << 0)
305#define ERC32_MEC_UART_STATUS_OEA (ERC32_MEC_UART_STATUS_OE << 0)
306#define ERC32_MEC_UART_STATUS_CUA (ERC32_MEC_UART_STATUS_CU << 0)
307#define ERC32_MEC_UART_STATUS_TXEA (ERC32_MEC_UART_STATUS_TXE << 0)
308
309#define ERC32_MEC_UART_STATUS_DRB (ERC32_MEC_UART_STATUS_DR << 16)
310#define ERC32_MEC_UART_STATUS_TSEB (ERC32_MEC_UART_STATUS_TSE << 16)
311#define ERC32_MEC_UART_STATUS_THEB (ERC32_MEC_UART_STATUS_THE << 16)
312#define ERC32_MEC_UART_STATUS_FEB (ERC32_MEC_UART_STATUS_FE << 16)
313#define ERC32_MEC_UART_STATUS_PEB (ERC32_MEC_UART_STATUS_PE << 16)
314#define ERC32_MEC_UART_STATUS_OEB (ERC32_MEC_UART_STATUS_OE << 16)
315#define ERC32_MEC_UART_STATUS_CUB (ERC32_MEC_UART_STATUS_CU << 16)
316#define ERC32_MEC_UART_STATUS_TXEB (ERC32_MEC_UART_STATUS_TXE << 16)
317
318#ifndef ASM
319
320/*
321 * This is used to manipulate the on-chip registers.
322 *
323 * The following symbol must be defined in the linkcmds file and point
324 * to the correct location.
325 */
326
327extern ERC32_Register_Map ERC32_MEC;
328
329/*
330 * Macros to manipulate the Interrupt Clear, Interrupt Force, Interrupt Mask,
331 * and the Interrupt Pending Registers.
332 *
333 * NOTE: For operations which are not atomic, this code disables interrupts
334 * to guarantee there are no intervening accesses to the same register.
335 * The operations which read the register, modify the value and then
336 * store the result back are vulnerable.
337 */
338
339#define ERC32_Clear_interrupt( _source ) \
340 do { \
341 ERC32_MEC.Interrupt_Clear = (1 << (_source)); \
342 } while (0)
343
344#define ERC32_Force_interrupt( _source ) \
345 do { \
346 uint32_t _level; \
347 \
348 _level = sparc_disable_interrupts(); \
349 ERC32_MEC.Test_Control = ERC32_MEC.Test_Control | 0x80000; \
350 ERC32_MEC.Interrupt_Force |= (1 << (_source)); \
351 sparc_enable_interrupts( _level ); \
352 } while (0)
353
354#define ERC32_Is_interrupt_pending( _source ) \
355 (ERC32_MEC.Interrupt_Pending & (1 << (_source)))
356
357#define ERC32_Is_interrupt_masked( _source ) \
358 (ERC32_MEC.Interrupt_Mask & (1 << (_source)))
359
360#define ERC32_Mask_interrupt( _source ) \
361 do { \
362 uint32_t _level; \
363 \
364 _level = sparc_disable_interrupts(); \
365 ERC32_MEC.Interrupt_Mask |= (1 << (_source)); \
366 sparc_enable_interrupts( _level ); \
367 } while (0)
368
369#define ERC32_Unmask_interrupt( _source ) \
370 do { \
371 uint32_t _level; \
372 \
373 _level = sparc_disable_interrupts(); \
374 ERC32_MEC.Interrupt_Mask &= ~(1 << (_source)); \
375 sparc_enable_interrupts( _level ); \
376 } while (0)
377
378#define ERC32_Disable_interrupt( _source, _previous ) \
379 do { \
380 uint32_t _level; \
381 uint32_t _mask = 1 << (_source); \
382 \
383 _level = sparc_disable_interrupts(); \
384 (_previous) = ERC32_MEC.Interrupt_Mask; \
385 ERC32_MEC.Interrupt_Mask = _previous | _mask; \
386 sparc_enable_interrupts( _level ); \
387 (_previous) &= _mask; \
388 } while (0)
389
390#define ERC32_Restore_interrupt( _source, _previous ) \
391 do { \
392 uint32_t _level; \
393 uint32_t _mask = 1 << (_source); \
394 \
395 _level = sparc_disable_interrupts(); \
396 ERC32_MEC.Interrupt_Mask = \
397 (ERC32_MEC.Interrupt_Mask & ~_mask) | (_previous); \
398 sparc_enable_interrupts( _level ); \
399 } while (0)
400
401/* Make all SPARC BSPs have common macros for interrupt handling on local CPU */
402#define BSP_Clear_interrupt(_source) ERC32_Clear_interrupt(_source)
403#define BSP_Force_interrupt(_source) ERC32_Force_interrupt(_source)
404#define BSP_Clear_forced_interrupt( _source ) \
405 do { \
406 uint32_t _level; \
407 \
408 _level = sparc_disable_interrupts(); \
409 ERC32_MEC.Interrupt_Force &= ~(1 << (_source)); \
410 sparc_enable_interrupts( _level ); \
411 } while (0)
412#define BSP_Is_interrupt_pending(_source) ERC32_Is_interrupt_pending(_source)
413#define BSP_Is_interrupt_forced(_source) \
414 (ERC32_MEC.Interrupt_Force & (1 << (_source)))
415#define BSP_Is_interrupt_masked(_source) ERC32_Is_interrupt_masked(_source)
416#define BSP_Unmask_interrupt(_source) ERC32_Unmask_interrupt(_source)
417#define BSP_Mask_interrupt(_source) ERC32_Mask_interrupt(_source)
418#define BSP_Disable_interrupt(_source, _previous) \
419 ERC32_Disable_interrupt(_source, _prev)
420#define BSP_Restore_interrupt(_source, _previous) \
421 ERC32_Restore_interrupt(_source, _previous)
422
423/* Make all SPARC BSPs have common macros for interrupt handling on any CPU */
424#define BSP_Cpu_Is_interrupt_masked(_source, _cpu) \
425 BSP_Is_interrupt_masked(_source)
426#define BSP_Cpu_Unmask_interrupt(_source, _cpu) \
427 BSP_Unmask_interrupt(_source)
428#define BSP_Cpu_Mask_interrupt(_source, _cpu) \
429 BSP_Mask_interrupt(_source)
430#define BSP_Cpu_Disable_interrupt(_source, _previous, _cpu) \
431 BSP_Disable_interrupt(_source, _prev)
432#define BSP_Cpu_Restore_interrupt(_source, _previous, _cpu) \
433 BSP_Cpu_Restore_interrupt(_source, _previous)
434
435/*
436 * The following macros attempt to hide the fact that the General Purpose
437 * Timer and Real Time Clock Timer share the Timer Control Register. Because
438 * the Timer Control Register is write only, we must mirror it in software
439 * and insure that writes to one timer do not alter the current settings
440 * and status of the other timer.
441 *
442 * This code promotes the view that the two timers are completely independent.
443 * By exclusively using the routines below to access the Timer Control
444 * Register, the application can view the system as having a General Purpose
445 * Timer Control Register and a Real Time Clock Timer Control Register
446 * rather than the single shared value.
447 *
448 * Each logical timer control register is organized as follows:
449 *
450 * D0 - Counter Reload
451 * 1 = reload counter at zero and restart
452 * 0 = stop counter at zero
453 *
454 * D1 - Counter Load
455 * 1 = load counter with preset value and restart
456 * 0 = no function
457 *
458 * D2 - Enable
459 * 1 = enable counting
460 * 0 = hold scaler and counter
461 *
462 * D3 - Scaler Load
463 * 1 = load scalar with preset value and restart
464 * 0 = no function
465 *
466 * To insure the management of the mirror is atomic, we disable interrupts
467 * around updates.
468 */
469
470#define ERC32_MEC_TIMER_COUNTER_RELOAD_AT_ZERO 0x00000001
471#define ERC32_MEC_TIMER_COUNTER_STOP_AT_ZERO 0x00000000
472
473#define ERC32_MEC_TIMER_COUNTER_LOAD_COUNTER 0x00000002
474
475#define ERC32_MEC_TIMER_COUNTER_ENABLE_COUNTING 0x00000004
476#define ERC32_MEC_TIMER_COUNTER_DISABLE_COUNTING 0x00000000
477
478#define ERC32_MEC_TIMER_COUNTER_LOAD_SCALER 0x00000008
479
480#define ERC32_MEC_TIMER_COUNTER_RELOAD_MASK 0x00000001
481#define ERC32_MEC_TIMER_COUNTER_ENABLE_MASK 0x00000004
482
483#define ERC32_MEC_TIMER_COUNTER_DEFINED_MASK 0x0000000F
484#define ERC32_MEC_TIMER_COUNTER_CURRENT_MODE_MASK 0x00000005
485
486extern uint32_t _ERC32_MEC_Timer_Control_Mirror;
487
488/*
489 * This macros manipulate the General Purpose Timer portion of the
490 * Timer Control register and promote the view that there are actually
491 * two independent Timer Control Registers.
492 */
493
494#define ERC32_MEC_Set_General_Purpose_Timer_Control( _value ) \
495 do { \
496 uint32_t _level; \
497 uint32_t _control; \
498 uint32_t __value; \
499 \
500 __value = ((_value) & 0x0f); \
501 _level = sparc_disable_interrupts(); \
502 _control = _ERC32_MEC_Timer_Control_Mirror; \
503 _control &= ERC32_MEC_TIMER_COUNTER_DEFINED_MASK << 8; \
504 _ERC32_MEC_Timer_Control_Mirror = _control | _value; \
505 _control &= (ERC32_MEC_TIMER_COUNTER_CURRENT_MODE_MASK << 8); \
506 _control |= __value; \
507 /* printf( "GPT 0x%x 0x%x 0x%x\n", _value, __value, _control ); */ \
508 ERC32_MEC.Timer_Control = _control; \
509 sparc_enable_interrupts( _level ); \
510 } while ( 0 )
511
512#define ERC32_MEC_Get_General_Purpose_Timer_Control( _value ) \
513 do { \
514 (_value) = _ERC32_MEC_Timer_Control_Mirror & 0xf; \
515 } while ( 0 )
516
517/*
518 * This macros manipulate the Real Timer Clock Timer portion of the
519 * Timer Control register and promote the view that there are actually
520 * two independent Timer Control Registers.
521 */
522
523#define ERC32_MEC_Set_Real_Time_Clock_Timer_Control( _value ) \
524 do { \
525 uint32_t _level; \
526 uint32_t _control; \
527 uint32_t __value; \
528 \
529 __value = ((_value) & 0x0f) << 8; \
530 _level = sparc_disable_interrupts(); \
531 _control = _ERC32_MEC_Timer_Control_Mirror; \
532 _control &= ERC32_MEC_TIMER_COUNTER_DEFINED_MASK; \
533 _ERC32_MEC_Timer_Control_Mirror = _control | __value; \
534 _control &= ERC32_MEC_TIMER_COUNTER_CURRENT_MODE_MASK; \
535 _control |= __value; \
536 /* printf( "RTC 0x%x 0x%x 0x%x\n", _value, __value, _control ); */ \
537 ERC32_MEC.Timer_Control = _control; \
538 sparc_enable_interrupts( _level ); \
539 } while ( 0 )
540
541#define ERC32_MEC_Get_Real_Time_Clock_Timer_Control( _value ) \
542 do { \
543 (_value) = (_ERC32_MEC_Timer_Control_Mirror >> 8) & 0xf; \
544 } while ( 0 )
545
546#endif /* !ASM */
547
548#ifdef __cplusplus
549}
550#endif
551
552#endif /* !_INCLUDE_ERC32_h */
sparc.h
This header file provides information required to build RTEMS for a particular member of the SPARC fa...
ERC32_Register_Map
Definition: erc32.h:102
Timer_Control
Definition: timerdata.h:61
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