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#define | US_CR 0x00 /* Control Register */ |
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#define | US_MR 0x04 /* Mode Register */ |
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#define | US_IER 0x08 /* Interrupt Enable Register */ |
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#define | US_IDR 0x0C /* Interrupt Disable Register */ |
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#define | US_IMR 0x10 /* Interrupt Mask Register */ |
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#define | US_SR 0x14 /* Channel Status Register */ |
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#define | US_RHR 0x18 /* Receiver Holding Register */ |
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#define | US_THR 0x1C /* Transmitter Holding Register */ |
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#define | US_BRGR 0x20 /* Baud Rate Generator Register */ |
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#define | US_RTOR 0x24 /* Receiver Time-out Register */ |
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#define | US_TTGR 0x28 /* Transmitter Timeguard Register */ |
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#define | US_C1R 0x40 /* Chip ID1 Register - FI DI Ratio Register */ |
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#define | US_C2R 0x44 /* Chip ID2 Register - Number of Erros Register */ |
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#define | US_FNTR 0x48 /* Force NTRST Register */ |
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#define | US_IF 0x4C /* IrDA Filter Register */ |
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#define | US_CR_RSTRX BIT2 /* 1 = Reset and disable receiver */ |
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#define | US_CR_RSTTX BIT3 /* 1 = Reset and disable transmitter */ |
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#define | US_CR_RXEN BIT4 /* 1 = Receiver enable */ |
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#define | US_CR_RXDIS BIT5 /* 1 = Receiver disable */ |
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#define | US_CR_TXEN BIT6 /* 1 = Transmitter enable */ |
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#define | US_CR_TXDIS BIT7 /* 1 = Transmitter disable */ |
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#define | US_CR_RSTSTA BIT8 /* 1 = Reset PARE, FRAME and OVRE in DBGU_SR. */ |
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#define | US_CR_STTBRK BIT9 /* 1 = Start transmission of a Break */ |
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#define | US_CR_STPBRK BIT10 /* 1 = Stop transmission of a Break */ |
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#define | US_CR_STTTO BIT11 /* 1 = Start Time-out */ |
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#define | US_CR_SENDA BIT12 /* 1 = Send Address - MDROP mode only */ |
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#define | US_CR_RSTIT BIT13 /* 1 = Reset Iteration */ |
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#define | US_CR_RSTNACK BIT14 /* 1 = Reset Non Acknowledge */ |
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#define | US_CR_RETTO BIT15 /* 1 = Restart Time-out */ |
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#define | US_CR_DTREN BIT16 /* 1 = Data Terminal Ready Enable - AT91RM9200 only */ |
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#define | US_CR_DTRDIS BIT17 /* 1 = Data Terminal Ready Disable - AT91RM9200 only */ |
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#define | US_CR_RTSEN BIT18 /* 1 = Request To Send Enable */ |
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#define | US_CR_RTSDIS BIT19 /* 1 = Request To Send Disable */ |
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#define | US_MR_USMODE (0xF << 0) /* Mode of the USART */ |
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#define | US_MR_USMODE_NORMAL 0 |
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#define | US_MR_USMODE_RS485 1 |
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#define | US_MR_USMODE_HWHS 2 |
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#define | US_MR_USMODE_MODEM 3 |
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#define | US_MR_USMODE_ISO7816_T0 4 |
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#define | US_MR_USMODE_ISO7816_T1 6 |
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#define | US_MR_USMODE_IRDA 8 |
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#define | US_MR_USCLKS (3 << 4) /* Clock Selection */ |
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#define | US_MR_USCLKS_MCK (0 << 4) |
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#define | US_MR_USCLKS_MCK_DIV8 (1 << 4) |
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#define | US_MR_USCLKS_SCK (3 << 4) |
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#define | US_MR_CHRL (3 << 6) /* Character Length */ |
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#define | US_MR_CHRL_5 (0 << 6) |
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#define | US_MR_CHRL_6 (1 << 6) |
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#define | US_MR_CHRL_7 (2 << 6) |
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#define | US_MR_CHRL_8 (3 << 6) |
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#define | US_MR_SYNC (1 << 8) /* Synchronous Mode Select */ |
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#define | US_MR_PAR (7 << 9) /* Parity Type */ |
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#define | US_MR_PAR_EVEN (0 << 9) /* Even Parity */ |
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#define | US_MR_PAR_ODD (1 << 9) /* Odd Parity */ |
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#define | US_MR_PAR_SPACE (2 << 9) /* Parity forced to 0 (Space) */ |
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#define | US_MR_PAR_MARK (3 << 9) /* Parity forced to 1 (Mark) */ |
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#define | US_MR_PAR_NONE (4 << 9) /* No Parity */ |
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#define | US_MR_PAR_MDROP (6 << 9) /* Multi-drop mode */ |
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#define | US_MR_NBSTOP (3 << 12) /* Number of Stop Bits */ |
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#define | US_MR_NBSTOP_1 (0 << 12) |
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#define | US_MR_NBSTOP_1_5 (1 << 12) |
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#define | US_MR_NBSTOP_2 (2 << 12) |
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#define | US_MR_CHMODE (3 << 14) /* Channel Mode */ |
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#define | US_MR_CHMODE_NORM (0 << 14) /* Normal Mode */ |
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#define | US_MR_CHMODE_AUTO (1 << 14) /* Auto Echo: RXD drives TXD */ |
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#define | US_MR_CHMODE_LOC (2 << 14) /* Local Loopback: TXD drives RXD */ |
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#define | US_MR_CHMODE_REM (3 << 14) /* Remote Loopback: RXD pin connected to TXD pin. */ |
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#define | US_MR_MSBF (1 << 16) /* Bit Order */ |
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#define | US_MR_MODE9 (1 << 17) /* 9-bit Character Length */ |
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#define | US_MR_CLKO (1 << 18) /* Clock Output Select */ |
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#define | US_MR_OVER (1 << 19) /* Oversampling Mode */ |
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#define | US_MR_INACK (1 << 20) /* Inhibit Non Acknowledge */ |
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#define | US_MR_DSNACK (1 << 21) /* Disable Successive NACK */ |
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#define | US_MR_MAX_ITER (7 << 24) /* Max Iterations */ |
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#define | US_MR_FILTER (1 << 28) /* Infrared Receive Line Filter */ |
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#define | US_IER_RXRDY BIT0 /* RXRDY Interrupt */ |
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#define | US_IER_TXRDY BIT1 /* TXRDY Interrupt */ |
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#define | US_IER_RXBRK BIT2 /* End of Receive Transfer Interrupt */ |
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#define | US_IER_ENDRX BIT3 /* End of Receiver Transfer */ |
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#define | US_IER_OVRE BIT5 /* Overrun Interrupt */ |
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#define | US_IER_FRAME BIT6 /* Framing Error Interrupt */ |
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#define | US_IER_PARE BIT7 /* Parity Error */ |
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#define | US_IER_TIMEOUT BIT8 /* Receiver Time-out */ |
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#define | US_IER_TXEMPTY BIT9 /* Transmitter Empty */ |
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#define | US_IER_ITERATION BIT10 /* Max number of Repetitions Reached */ |
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#define | US_IER_TXBUFE BIT11 /* Transmission Buffer Empty */ |
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#define | US_IER_RXBUFF BIT12 /* Reception Buffer Full */ |
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#define | US_IER_NACK BIT13 /* Non Acknowledge */ |
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#define | US_IER_RIIC BIT16 /* Ring Indicator Input Change [AT91RM9200 only] */ |
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#define | US_IER_DSRIC BIT17 /* Data Set Ready Input Change [AT91RM9200 only] */ |
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#define | US_IER_DCDIC BIT18 /* Data Carrier Detect Input Change [AT91RM9200 only] */ |
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#define | US_IER_CTSIC BIT19 /* Clear to Send Input Change */ |
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#define | US_IER_ALL 0xC0001AFB /* all assigned bits */ |
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#define | US_FNTR_NTRST BIT0 /* 1 = Force NTRST low in JTAG */ |
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Atmel AT91RM9200_USART Register definitions.
1.9.6