RTEMS 6.1-rc5
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at91rm9200_mem.h
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1
9/*
10 * AT91RM9200 Memory Controller definitions
11 *
12 * Copyright (c) 2002 by Cogent Computer Systems
13 * Written by Mike Kelly <mike@cogcomp.com>
14 *
15 * The license and distribution terms for this file may be
16 * found in the file LICENSE in this distribution or at
17 * http://www.rtems.org/license/LICENSE.
18 */
19#ifndef AT91RM9200_MEM_H
20#define AT91RM9200_MEM_H
21
22/**********************************************************************
23 * External Bus Interface Unit
24 **********************************************************************/
25#define EBI_CSA 0x00 /* Chip Select Assignment Register */
26#define EBI_CFGR 0x04 /* Configuration Register */
27
28/* Bit Defines */
29/* EBI_CSA - Chip Select Assignment Register */
30#define EBI_CSA_CS4_CF BIT4 /* 1 = CS4-6 are assigned to Compact Flash, 0 = Chip Selects */
31#define EBI_CSA_CS3_SMM BIT3 /* 1 = CS3 is assigned to SmartMedia, 0 = Chip Select */
32#define EBI_CSA_CS1_SDRAM BIT1 /* 1 = CS1 is assigned to SDRAM, 0 = Chip Select */
33#define EBI_CSA_CS0_BF BIT0 /* 1 = CS0 is assigned to Burst Flash, 0 = Chip Select */
34
35/* EBI_CFGR - Configuration Register */
36#define EBI_CFGR_DBPU BIT0 /* 1 = Disable D0-15 pullups */
37
38/***************************************************************************
39 * Static Memory Interface Unit
40 ***************************************************************************/
41#define SMC_CSR0 0x00 /* Chip Select Register 0 */
42#define SMC_CSR1 0x04 /* Chip Select Register 1 */
43#define SMC_CSR2 0x08 /* Chip Select Register 2 */
44#define SMC_CSR3 0x0C /* Chip Select Register 3 */
45#define SMC_CSR4 0x10 /* Chip Select Register 4 */
46#define SMC_CSR5 0x14 /* Chip Select Register 5 */
47#define SMC_CSR6 0x18 /* Chip Select Register 6 */
48#define SMC_CSR7 0x1C /* Chip Select Register 7 */
49
50/* Bit Defines */
51/* SMC_CSR0 -7 - Chip Selects 0 - 7 Register */
52#define SMC_CSR_RWHOLD(_x_) ((_x_ & 0x3) << 28) /* Hold CS after R/W strobes */
53#define SMC_CSR_RWSETUP(_x_) ((_x_ & 0x3) << 24) /* Setup CS before R/W strobes */
54#define SMC_CSR_ACSS_0 (0 << 16) /* Setup/Hold Address 0 clocks before/after CS */
55#define SMC_CSR_ACSS_1 (1 << 16) /* Setup/Hold Address 1 clock before/after CS */
56#define SMC_CSR_ACSS_2 (2 << 16) /* Setup/Hold Address 2 clocks before/after CS */
57#define SMC_CSR_ACSS_3 (3 << 16) /* Setup/Hold Address 3 clocks before/after CS */
58#define SMC_CSR_DRP_NORMAL 0 /* 0 = normal read protocol */
59#define SMC_CSR_DRP_EARLY BIT15 /* 1 = early read protocol */
60#define SMC_CSR_DBW_16 (1 << 13) /* CS DataBus Width = 16-Bits */
61#define SMC_CSR_DBW_8 (2 << 13) /* CS DataBus Width = 8 Bits */
62#define SMC_CSR_BAT_16_1 0 /* Single 16-Bit device (when DBW is 16) */
63#define SMC_CSR_BAT_16_2 BIT12 /* Dual 8-Bit devices (when DBW is 16) */
64#define SMC_CSR_TDF(_x_) ((_x_ & 0xf) << 8) /* Intercycle Data Float Time */
65#define SMC_CSR_WSEN BIT7 /* 1 = wait states are enabled */
66#define SMC_CSR_NWS(_x_) ((_x_ & 0x7f) << 0) /* Wait States + 1 */
67
68/* ***************************************************************************** */
69/* SDRAM Memory Interface Unit */
70/* ***************************************************************************** */
71#define SDRC_MR 0x00 /* Mode Register */
72#define SDRC_TR 0x04 /* Refresh Timer Register */
73#define SDRC_CR 0x08 /* Configuration Register */
74#define SDRC_SRR 0x0C /* Self Refresh Register */
75#define SDRC_LPR 0x10 /* Low Power Register */
76#define SDRC_IER 0x14 /* Interrupt Enable Register */
77#define SDRC_IDR 0x18 /* Interrupt Disable Register */
78#define SDRC_IMR 0x1C /* Interrupt Mask Register */
79#define SDRC_ISR 0x20 /* Interrupt Status Register */
80
81/* Bit Defines */
82/* SDRC_MR - Mode Register */
83#define SDRC_MR_DBW_16 BIT4 /* 1 = SDRAM is 16-bits wide, 0 = 32-bits */
84#define SDRC_MR_NORM (0 << 0) /* Normal Mode - All accesses to SDRAM are decoded normally */
85#define SDRC_MR_NOP (1 << 0) /* NOP Command is sent to SDRAM */
86#define SDRC_MR_PRE (2 << 0) /* Precharge All Command is sent to SDRAM */
87#define SDRC_MR_MRS (3 << 0) /* Mode Register Set Command is sent to SDRAM */
88#define SDRC_MR_REF (4 << 0) /* Refresh Command is sent to SDRAM */
89
90/* SDRC_TR - Refresh Timer Register */
91#define SDRC_TR_COUNT(_x_) ((_x_ & 0xfff) << 0)
92
93/* SDRC_CR - Configuration Register */
94#define SDRC_CR_TXSR(_x_) ((_x_ & 0xf) << 27) /* CKE to ACT Time */
95#define SDRC_CR_TRAS(_x_) ((_x_ & 0xf) << 23) /* ACT to PRE Time */
96#define SDRC_CR_TRCD(_x_) ((_x_ & 0xf) << 19) /* RAS to CAS Time */
97#define SDRC_CR_TRP(_x_) ((_x_ & 0xf) << 15) /* PRE to ACT Time */
98#define SDRC_CR_TRC(_x_) ((_x_ & 0xf) << 11) /* REF to ACT Time */
99#define SDRC_CR_TWR(_x_) ((_x_ & 0xf) << 7) /* Write Recovery Time */
100#define SDRC_CR_CAS_2 (2 << 5) /* Cas Delay = 2, this is the only supported value */
101#define SDRC_CR_NB_2 0 /* 2 Banks per device */
102#define SDRC_CR_NB_4 BIT4 /* 4 Banks per device */
103#define SDRC_CR_NR_11 (0 << 2) /* Number of rows = 11 */
104#define SDRC_CR_NR_12 (1 << 2) /* Number of rows = 12 */
105#define SDRC_CR_NR_13 (2 << 2) /* Number of rows = 13 */
106#define SDRC_CR_NC_8 (0 << 0) /* Number of columns = 8 */
107#define SDRC_CR_NC_9 (1 << 0) /* Number of columns = 9 */
108#define SDRC_CR_NC_10 (2 << 0) /* Number of columns = 10 */
109#define SDRC_CR_NC_11 (3 << 0) /* Number of columns = 11 */
110
111/* SDRC_SRR - Self Refresh Register */
112#define SDRC_SRR_SRCB BIT0 /* 1 = Enter Self Refresh */
113
114/* SDRC_LPR - Low Power Register */
115#define SDRC_LPR_LPCB BIT0 /* 1 = De-assert CKE between accesses */
116
117/* SDRC_IER - Interrupt Enable Register */
118/* SDRC_IDR - Interrupt Disable Register */
119/* SDRC_ISR - Interrupt Mask Register */
120/* SDRC_IMR - Interrupt Mask Register */
121#define SDRC_INT_RES BIT0 /* Refresh Error Status */
122
123#endif
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