RTEMS 6.1-rc5
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at91rm9200_emac.h
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1
9/*
10 * Atmel AT91RM9200 EMAC Register definitions
11 *
12 * Copyright (c) 2003 by Cogent Computer Systems
13 * Written by Mike Kelly <mike@cogcomp.com>
14 *
15 * The license and distribution terms for this file may be
16 * found in the file LICENSE in this distribution or at
17 * http://www.rtems.org/license/LICENSE.
18 */
19#ifndef __AT91RM9200_EMAC_H__
20#define __AT91RM9200_EMAC_H__
21
22#include <bits.h>
23
24/*Register offsets */
25#define EMAC_CTL 0x00 /* Network Control Register */
26#define EMAC_CFG 0x04 /* Network Configuration Register */
27#define EMAC_SR 0x08 /* Network Status Register */
28#define EMAC_TAR 0x0C /* Transmit Address Register */
29#define EMAC_TCR 0x10 /* Transmit Control Register */
30#define EMAC_TSR 0x14 /* Transmit Status Register */
31#define EMAC_RBQP 0x18 /* Receive Buffer Queue Pointer */
32#define EMAC_RSR 0x20 /* Receive Status Register */
33#define EMAC_ISR 0x24 /* Interrupt Enable Register */
34#define EMAC_IER 0x28 /* Interrupt Enable Register */
35#define EMAC_IDR 0x2C /* Interrupt Disable Register */
36#define EMAC_IMR 0x30 /* Interrupt Mask Register */
37#define EMAC_MAN 0x34 /* PHY Maintenance Register */
38#define EMAC_FRA 0x40 /* Frames Transmitted OK Register */
39#define EMAC_SCOL 0x44 /* Single Collision Frame Register */
40#define EMAC_MCOL 0x48 /* Multiple Collision Frame Register */
41#define EMAC_OK 0x4C /* Frames Received OK Register */
42#define EMAC_SEQE 0x50 /* Frame Check Sequence Error Register */
43#define EMAC_ALE 0x54 /* Alignment Error Register */
44#define EMAC_DTE 0x58 /* Deferred Transmission Frame Register */
45#define EMAC_LCOL 0x5C /* Late Collision Register */
46#define EMAC_ECOL 0x60 /* Excessive Collision Register */
47#define EMAC_CSE 0x64 /* Carrier Sense Error Register */
48#define EMAC_TUE 0x68 /* Transmit Underrun Error Register */
49#define EMAC_CDE 0x6C /* Code Error Register */
50#define EMAC_ELR 0x70 /* Excessive Length Error Register */
51#define EMAC_RJB 0x74 /* Receive Jabber Register */
52#define EMAC_USF 0x78 /* Undersize Frame Register */
53#define EMAC_SQEE 0x7C /* SQE Test Error Register */
54#define EMAC_DRFC 0x80 /* Discarded RX Frame Register */
55#define EMAC_HSH 0x90 /* Hash Address High[63:32] */
56#define EMAC_HSL 0x94 /* Hash Address Low[31:0] */
57#define EMAC_SA1L 0x98 /* Specific Addr 1 Low, First 4 bytes */
58#define EMAC_SA1H 0x9C /* Specific Addr 1 High, Last 2 bytes */
59#define EMAC_SA2L 0xA0 /* Specific Addr 2 Low, First 4 bytes */
60#define EMAC_SA2H 0xA4 /* Specific Addr 2 High, Last 2 bytes */
61#define EMAC_SA3L 0xA8 /* Specific Addr 3 Low, First 4 bytes */
62#define EMAC_SA3H 0xAC /* Specific Addr 3 High, Last 2 bytes */
63#define EMAC_SA4L 0xB0 /* Specific Addr 4 Low, First 4 bytes */
64#define EMAC_SA4H 0xB4 /* Specific Addr 4 High, Last 2 bytesr */
65
66/* Control Register, EMAC_CTL, Offset 0x0 */
67#define EMAC_CTL_LB BIT0 /* 1 = Set Loopback output signal */
68#define EMAC_CTL_LBL BIT1 /* 1 = Loopback local. */
69#define EMAC_CTL_RE BIT2 /* 1 = Receive enable. */
70#define EMAC_CTL_TE BIT3 /* 1 = Transmit enable. */
71#define EMAC_CTL_MPE BIT4 /* 1 = Management port enable. */
72#define EMAC_CTL_CSR BIT5 /* Write 1 to clear stats registers. */
73#define EMAC_CTL_ISR BIT6 /* Write to increment stats registers */
74#define EMAC_CTL_WES BIT7 /* 1 = Enable writing to stats regs */
75#define EMAC_CTL_BP BIT8 /* 1 = Force collision on all RX frames */
76
77/* Configuration Register, EMAC_CFG, Offset 0x4 */
78#define EMAC_CFG_SPD BIT0 /* 1 = 10/100 Speed (not functional?) */
79#define EMAC_CFG_FD BIT1 /* 1 = Full duplex. */
80#define EMAC_CFG_BR BIT2 /* write 0 */
81#define EMAC_CFG_CAF BIT4 /* 1 = accept all frames */
82#define EMAC_CFG_NBC BIT5 /* 1 = disable reception of bcast frms */
83#define EMAC_CFG_MTI BIT6 /* 1 = Multicast hash enable */
84#define EMAC_CFG_UNI BIT7 /* 1 = Unicast hash enable. */
85#define EMAC_CFG_BIG BIT8 /* 1 = enable reception 1522 byte frms */
86#define EMAC_CFG_EAE BIT9 /* write 0 */
87#define EMAC_CFG_CLK_8 (0 << 10) /* MII Clock = HCLK divided by 8 */
88#define EMAC_CFG_CLK_16 (1 << 10) /* MII Clock = HCLK divided by 16 */
89#define EMAC_CFG_CLK_32 (2 << 10) /* MII Clock = HCLK divided by 32 */
90#define EMAC_CFG_CLK_64 (3 << 10) /* MII Clock = HCLK divided by 64 */
91#define EMAC_CFG_CLK_MASK (3 << 10) /* MII Clock mask */
92#define EMAC_CFG_RTY BIT12 /* Retry Test Mode - Must be 0 */
93#define EMAC_CFG_RMII BIT13 /* Reduced MII Mode Enable */
94
95/* Status Register, EMAC_SR, Offset 0x8 */
96#define EMAC_LINK BIT0 /* Link pin */
97#define EMAC_MDIO BIT1 /* Real Time state of MDIO pin */
98#define EMAC_IDLE BIT2 /* 0 = PHY Logic is idle */
99
100/* Transmit Control Register, EMAC_TCR, Offset 0x10 */
101#define EMAC_TCR_LEN(_x_) ((_x_ & 0x7FF) << 0) /* Tx frame len minus CRC */
102#define EMAC_TCR_NCRC BIT15 /* Do'nt append CRC on Tx */
103
104/* Transmit Status Register, EMAC_TSR, Offset 0x14 */
105#define EMAC_TSR_OVR BIT0 /* 1 = Transmit buffer overrun */
106#define EMAC_TSR_COL BIT1 /* 1 = Collision occured */
107#define EMAC_TSR_RLE BIT2 /* 1 = Retry lmimt exceeded */
108#define EMAC_TSR_TXIDLE BIT3 /* 1 = Transmitter is idle */
109#define EMAC_TSR_BNQ BIT4 /* 1 = Transmit buffer not queued */
110#define EMAC_TSR_COMP BIT5 /* 1 = Transmit complete */
111#define EMAC_TSR_UND BIT6 /* 1 = Transmit underrun */
112
113/* Receive Status Register, EMAC_RSR, Offset 0x20 */
114#define EMAC_RSR_BNA BIT0 /* 1 = Buffer not available */
115#define EMAC_RSR_REC BIT1 /* 1 = Frame received */
116#define EMAC_RSR_OVR BIT2 /* 1 = Receive overrun */
117
118/*
119 * Interrupt Status Register, EMAC_ISR, Offsen 0x24
120 * Interrupt Enable Register, EMAC_IER, Offset 0x28
121 * Interrupt Disable Register, EMAC_IDR, Offset 0x2c
122 * Interrupt Mask Register, EMAC_IMR, Offset 0x30
123 */
124#define EMAC_INT_DONE BIT0 /* Phy management done */
125#define EMAC_INT_RCOM BIT1 /* Receive complete */
126#define EMAC_INT_RBNA BIT2 /* Receive buffer not available */
127#define EMAC_INT_TOVR BIT3 /* Transmit buffer overrun */
128#define EMAC_INT_TUND BIT4 /* Transmit buffer underrun */
129#define EMAC_INT_RTRY BIT5 /* Transmit Retry limt */
130#define EMAC_INT_TBRE BIT6 /* Transmit buffer register empty */
131#define EMAC_INT_TCOM BIT7 /* Transmit complete */
132#define EMAC_INT_TIDLE BIT8 /* Transmit idle */
133#define EMAC_INT_LINK BIT9 /* Link pin changed value */
134#define EMAC_INT_ROVR BIT10 /* Receive overrun */
135#define EMAC_INT_ABT BIT11 /* Abort on DMA transfer */
136
137/* PHY Maintenance Register, EMAC_MAN, Offset 0x34 */
138#define EMAC_MAN_DATA(_x_) ((_x_ & 0xFFFF) << 0)/* PHY data register */
139#define EMAC_MAN_CODE (0x2 << 16) /* IEEE Code */
140#define EMAC_MAN_REGA(_x_) ((_x_ & 0x1F) << 18) /* PHY register address */
141#define EMAC_MAN_PHYA(_x_) ((_x_ & 0x1F) << 23) /* PHY address */
142#define EMAC_MAN_WRITE (0x1 << 28) /* Transfer is a write */
143#define EMAC_MAN_READ (0x2 << 28) /* Transfer is a read */
144#define EMAC_MAN_HIGH BIT30 /* Must be set */
145#define EMAC_MAN_LOW BIT31
146
147/*
148 * Bit assignments for Receive Buffer Descriptor
149 * Address - Word 0
150 */
151#define RXBUF_ADD_BASE_MASK 0xfffffffc /* Base addr of the rx buf */
152#define RXBUF_ADD_WRAP BIT1 /* set indicates last buf */
153#define RXBUF_ADD_OWNED BIT0 /* 1 = SW owns the pointer */
154
155/* Status - Word 1 */
156#define RXBUF_STAT_BCAST BIT31 /* Global bcast addr detected */
157#define RXBUF_STAT_MULTI BIT30 /* Multicast hash match */
158#define RXBUF_STAT_UNI BIT29 /* Unicast hash match */
159#define RXBUF_STAT_EXT BIT28 /* External address (optional) */
160#define RXBUF_STAT_UNK BIT27 /* Unknown source address */
161#define RXBUF_STAT_LOC1 BIT26 /* Local address 1 match */
162#define RXBUF_STAT_LOC2 BIT25 /* Local address 2 match */
163#define RXBUF_STAT_LOC3 BIT24 /* Local address 3 match */
164#define RXBUF_STAT_LOC4 BIT23 /* Local address 4 match */
165#define RXBUF_STAT_LEN_MASK 0x7ff /* Len of frame including FCS */
166
167#endif /* __AT91RM9200_EMAC_H__ */
168
bits.h
Contains Defined Bits.
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