37#ifndef LIBBSP_ARM_SHARED_ARM_GIC_H
38#define LIBBSP_ARM_SHARED_ARM_GIC_H
59#define GIC_ID_TO_ONE_BIT_REG_INDEX(id) ((id) >> 5)
60#define GIC_ID_TO_ONE_BIT_REG_BIT(id) (1U << ((id) & 0x1fU))
62#define GIC_ID_TO_TWO_BITS_REG_INDEX(id) ((id) >> 4)
63#define GIC_ID_TO_TWO_BITS_REG_OFFSET(id) (((id) & 0xfU) << 1)
65static inline bool gic_id_is_enabled(
volatile gic_dist *dist, uint32_t
id)
67 uint32_t i = GIC_ID_TO_ONE_BIT_REG_INDEX(
id);
68 uint32_t bit = GIC_ID_TO_ONE_BIT_REG_BIT(
id);
70 return (dist->icdiser[i] & bit) != 0;
73static inline void gic_id_enable(
volatile gic_dist *dist, uint32_t
id)
75 uint32_t i = GIC_ID_TO_ONE_BIT_REG_INDEX(
id);
76 uint32_t bit = GIC_ID_TO_ONE_BIT_REG_BIT(
id);
78 dist->icdiser[i] = bit;
81static inline void gic_id_disable(
volatile gic_dist *dist, uint32_t
id)
83 uint32_t i = GIC_ID_TO_ONE_BIT_REG_INDEX(
id);
84 uint32_t bit = GIC_ID_TO_ONE_BIT_REG_BIT(
id);
86 dist->icdicer[i] = bit;
89static inline bool gic_id_is_pending(
volatile gic_dist *dist, uint32_t
id)
91 uint32_t i = GIC_ID_TO_ONE_BIT_REG_INDEX(
id);
92 uint32_t bit = GIC_ID_TO_ONE_BIT_REG_BIT(
id);
94 return (dist->icdispr[i] & bit) != 0;
97static inline void gic_id_set_pending(
volatile gic_dist *dist, uint32_t
id)
99 uint32_t i = GIC_ID_TO_ONE_BIT_REG_INDEX(
id);
100 uint32_t bit = GIC_ID_TO_ONE_BIT_REG_BIT(
id);
102 dist->icdispr[i] = bit;
105static inline void gic_id_clear_pending(
volatile gic_dist *dist, uint32_t
id)
107 uint32_t i = GIC_ID_TO_ONE_BIT_REG_INDEX(
id);
108 uint32_t bit = GIC_ID_TO_ONE_BIT_REG_BIT(
id);
110 dist->icdicpr[i] = bit;
113static inline bool gic_id_is_active(
volatile gic_dist *dist, uint32_t
id)
115 uint32_t i = GIC_ID_TO_ONE_BIT_REG_INDEX(
id);
116 uint32_t bit = GIC_ID_TO_ONE_BIT_REG_BIT(
id);
118 return (dist->icdabr[i] & bit) != 0;
126static inline gic_group gic_id_get_group(
131 uint32_t i = GIC_ID_TO_ONE_BIT_REG_INDEX(
id);
132 uint32_t bit = GIC_ID_TO_ONE_BIT_REG_BIT(
id);
134 return (dist->icdigr[i] & bit) != 0 ? GIC_GROUP_1 : GIC_GROUP_0;
137static inline void gic_id_set_group(
143 uint32_t i = GIC_ID_TO_ONE_BIT_REG_INDEX(
id);
144 uint32_t bit = GIC_ID_TO_ONE_BIT_REG_BIT(
id);
145 uint32_t icdigr = dist->icdigr[i];
149 if (group == GIC_GROUP_1) {
153 dist->icdigr[i] = icdigr;
156static inline void gic_id_set_priority(
162 dist->icdipr[id] = priority;
165static inline uint8_t gic_id_get_priority(
volatile gic_dist *dist, uint32_t
id)
167 return dist->icdipr[id];
170static inline void gic_id_set_targets(
176 dist->icdiptr[id] = targets;
179static inline uint8_t gic_id_get_targets(
volatile gic_dist *dist, uint32_t
id)
181 return dist->icdiptr[id];
189static inline gic_trigger_mode gic_id_get_trigger_mode(
194 uint32_t i = GIC_ID_TO_TWO_BITS_REG_INDEX(
id);
195 uint32_t o = GIC_ID_TO_TWO_BITS_REG_OFFSET(
id) + 1;
196 uint32_t bit = 1U << o;
198 return (dist->icdicfr[i] & bit) != 0 ?
199 GIC_EDGE_TRIGGERED : GIC_LEVEL_SENSITIVE;
202static inline void gic_id_set_trigger_mode(
205 gic_trigger_mode mode
208 uint32_t i = GIC_ID_TO_TWO_BITS_REG_INDEX(
id);
209 uint32_t o = GIC_ID_TO_TWO_BITS_REG_OFFSET(
id) + 1;
210 uint32_t bit = mode << o;
211 uint32_t mask = 1U << o;
212 uint32_t icdicfr = dist->icdicfr[i];
217 dist->icdicfr[i] = icdicfr;
225static inline gic_handling_model gic_id_get_handling_model(
230 uint32_t i = GIC_ID_TO_TWO_BITS_REG_INDEX(
id);
231 uint32_t o = GIC_ID_TO_TWO_BITS_REG_OFFSET(
id);
232 uint32_t bit = 1U << o;
234 return (dist->icdicfr[i] & bit) != 0 ? GIC_1_TO_N : GIC_N_TO_N;
237static inline void gic_id_set_handling_model(
240 gic_handling_model model
243 uint32_t i = GIC_ID_TO_TWO_BITS_REG_INDEX(
id);
244 uint32_t o = GIC_ID_TO_TWO_BITS_REG_OFFSET(
id);
245 uint32_t bit = model << o;
246 uint32_t mask = 1U << o;
247 uint32_t icdicfr = dist->icdicfr[i];
252 dist->icdicfr[i] = icdicfr;
This header file provides interfaces of the ARM Generic Interrupt Controller (GIC) memory-mapped regi...
Definition: arm-gic-regs.h:108