alt_clock_manager.h

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/******************************************************************************
*
* Copyright 2013 Altera Corporation. All Rights Reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*
******************************************************************************/
 
#ifndef __ALT_CLK_MGR_H__
#define __ALT_CLK_MGR_H__
 
#include "hwlib.h"
#include "alt_clock_group.h"
 
#ifdef __cplusplus
extern "C"
{
#endif  /* __cplusplus */
 
/******************************************************************************/
typedef uint32_t    alt_freq_t;
 
/******************************************************************************/
typedef enum ALT_CLK_e
{
    /* Clock Input Pins */
    ALT_CLK_IN_PIN_OSC1,
    ALT_CLK_IN_PIN_OSC2,
    /* FPGA Clock Sources External to HPS */
    ALT_CLK_F2H_PERIPH_REF,
                                        /*<! Alternate clock source from FPGA
                                         * for HPS Peripheral PLL. */
 
    ALT_CLK_F2H_SDRAM_REF,
                                        /*<! Alternate clock source from FPGA
                                         * for HPS SDRAM PLL. */
 
 
    /* Other Clock Sources External to HPS */
    ALT_CLK_IN_PIN_JTAG,
    ALT_CLK_IN_PIN_ULPI0,
    ALT_CLK_IN_PIN_ULPI1,
    ALT_CLK_IN_PIN_EMAC0_RX,
    ALT_CLK_IN_PIN_EMAC1_RX,
    /* PLLs */
    ALT_CLK_MAIN_PLL,
    ALT_CLK_PERIPHERAL_PLL,
    ALT_CLK_SDRAM_PLL,
    /* OSC1 Clock Group - The OSC1 clock group contains those clocks which are derived
     * directly from the osc_clk_1_HPS pin */
    ALT_CLK_OSC1,
    /* Main Clock Group - The following clocks are derived from the Main PLL. */
    ALT_CLK_MAIN_PLL_C0,
    ALT_CLK_MAIN_PLL_C1,
    ALT_CLK_MAIN_PLL_C2,
    ALT_CLK_MAIN_PLL_C3,
    ALT_CLK_MAIN_PLL_C4,
    ALT_CLK_MAIN_PLL_C5,
    ALT_CLK_MPU,
    ALT_CLK_MPU_L2_RAM,
    ALT_CLK_MPU_PERIPH,
    ALT_CLK_L3_MAIN,
    ALT_CLK_L3_MP,
    ALT_CLK_L3_SP,
    ALT_CLK_L4_MAIN,
    ALT_CLK_L4_MP,
    ALT_CLK_L4_SP,
    ALT_CLK_DBG_BASE,
    ALT_CLK_DBG_AT,
    ALT_CLK_DBG_TRACE,
    ALT_CLK_DBG_TIMER,
    ALT_CLK_DBG,
    ALT_CLK_MAIN_QSPI,
    ALT_CLK_MAIN_NAND_SDMMC,
    ALT_CLK_CFG,
    ALT_CLK_H2F_USER0,
    /* Peripherals Clock Group - The following clocks are derived from the Peripheral PLL */
    ALT_CLK_PERIPHERAL_PLL_C0,
    ALT_CLK_PERIPHERAL_PLL_C1,
    ALT_CLK_PERIPHERAL_PLL_C2,
    ALT_CLK_PERIPHERAL_PLL_C3,
    ALT_CLK_PERIPHERAL_PLL_C4,
    ALT_CLK_PERIPHERAL_PLL_C5,
    ALT_CLK_USB_MP,
    ALT_CLK_SPI_M,
    ALT_CLK_QSPI,
    ALT_CLK_NAND_X,
    ALT_CLK_NAND,
    ALT_CLK_SDMMC,
    ALT_CLK_EMAC0,
    ALT_CLK_EMAC1,
    ALT_CLK_CAN0,
    ALT_CLK_CAN1,
    ALT_CLK_GPIO_DB,
    ALT_CLK_H2F_USER1,
    /* SDRAM Clock Group - The following clocks are derived from the SDRAM PLL */
    ALT_CLK_SDRAM_PLL_C0,
    ALT_CLK_SDRAM_PLL_C1,
    ALT_CLK_SDRAM_PLL_C2,
    ALT_CLK_SDRAM_PLL_C3,
    ALT_CLK_SDRAM_PLL_C4,
    ALT_CLK_SDRAM_PLL_C5,
    ALT_CLK_DDR_DQS,
    ALT_CLK_DDR_2X_DQS,
    ALT_CLK_DDR_DQ,
    ALT_CLK_H2F_USER2,
    /* Clock Output Pins */
    ALT_CLK_OUT_PIN_EMAC0_TX,
    ALT_CLK_OUT_PIN_EMAC1_TX,
    ALT_CLK_OUT_PIN_SDMMC,
    ALT_CLK_OUT_PIN_I2C0_SCL,
    ALT_CLK_OUT_PIN_I2C1_SCL,
    ALT_CLK_OUT_PIN_I2C2_SCL,
    ALT_CLK_OUT_PIN_I2C3_SCL,
    ALT_CLK_OUT_PIN_SPIM0,
    ALT_CLK_OUT_PIN_SPIM1,
    ALT_CLK_OUT_PIN_QSPI,
    ALT_CLK_UNKNOWN
} ALT_CLK_t;
 
/******************************************************************************/
/******************************************************************************/
typedef enum ALT_CLK_PLL_LOCK_STATUS_e
{
    ALT_MAIN_PLL_LOCK_ACHV    = 0x00000001, 
    ALT_PERIPH_PLL_LOCK_ACHV  = 0x00000002, 
    ALT_SDR_PLL_LOCK_ACHV     = 0x00000004, 
    ALT_MAIN_PLL_LOCK_LOST    = 0x00000008, 
    ALT_PERIPH_PLL_LOCK_LOST  = 0x00000010, 
    ALT_SDR_PLL_LOCK_LOST     = 0x00000020  
} ALT_CLK_PLL_LOCK_STATUS_t;
 
/******************************************************************************/
ALT_STATUS_CODE alt_clk_lock_status_clear(ALT_CLK_PLL_LOCK_STATUS_t lock_stat_mask);
 
/******************************************************************************/
uint32_t alt_clk_lock_status_get(void);
 
/******************************************************************************/
ALT_STATUS_CODE alt_clk_pll_is_locked(ALT_CLK_t pll);
 
/******************************************************************************/
/******************************************************************************/
typedef enum ALT_CLK_SAFE_DOMAIN_e
{
    ALT_CLK_DOMAIN_NORMAL,
    ALT_CLK_DOMAIN_DEBUG
} ALT_CLK_SAFE_DOMAIN_t;
 
/******************************************************************************/
ALT_STATUS_CODE alt_clk_safe_mode_clear(void);
 
/******************************************************************************/
bool alt_clk_is_in_safe_mode(ALT_CLK_SAFE_DOMAIN_t clk_domain);
 
/******************************************************************************/
/******************************************************************************/
ALT_STATUS_CODE alt_clk_pll_bypass_disable(ALT_CLK_t pll);
 
/******************************************************************************/
ALT_STATUS_CODE alt_clk_pll_bypass_enable(ALT_CLK_t pll,
                                          bool use_input_mux);
 
/******************************************************************************/
ALT_STATUS_CODE alt_clk_pll_is_bypassed(ALT_CLK_t pll);
 
/******************************************************************************/
/******************************************************************************/
ALT_STATUS_CODE alt_clk_clock_disable(ALT_CLK_t clk);
 
/******************************************************************************/
ALT_STATUS_CODE alt_clk_clock_enable(ALT_CLK_t clk);
 
/******************************************************************************/
ALT_STATUS_CODE alt_clk_is_enabled(ALT_CLK_t clk);
 
/******************************************************************************/
/******************************************************************************/
ALT_CLK_t alt_clk_source_get(ALT_CLK_t clk);
 
/******************************************************************************/
ALT_STATUS_CODE alt_clk_source_set(ALT_CLK_t clk,
                                   ALT_CLK_t ref_clk);
 
/******************************************************************************/
/******************************************************************************/
ALT_STATUS_CODE alt_clk_ext_clk_freq_set(ALT_CLK_t clk,
                                         alt_freq_t freq);
 
/******************************************************************************/
alt_freq_t alt_clk_ext_clk_freq_get(ALT_CLK_t clk);
 
/******************************************************************************/
typedef struct ALT_CLK_PLL_CFG_s
{
    ALT_CLK_t           ref_clk;        
    uint32_t            mult;           
    uint32_t            div;            
    uint32_t            cntrs[6];       
    uint32_t            pshift[6];      
} ALT_CLK_PLL_CFG_t;
 
/******************************************************************************/
ALT_STATUS_CODE alt_clk_pll_cfg_get(ALT_CLK_t pll,
                                    ALT_CLK_PLL_CFG_t* pll_cfg);
 
/******************************************************************************/
ALT_STATUS_CODE alt_clk_pll_cfg_set(ALT_CLK_t pll,
                                    const ALT_CLK_PLL_CFG_t* pll_cfg);
 
/******************************************************************************/
ALT_STATUS_CODE alt_clk_pll_vco_cfg_get(ALT_CLK_t pll,
                                        uint32_t* mult,
                                        uint32_t* div);
 
/******************************************************************************/
ALT_STATUS_CODE alt_clk_pll_vco_cfg_set(ALT_CLK_t pll,
                                        uint32_t mult,
                                        uint32_t div);
 
/******************************************************************************/
ALT_STATUS_CODE alt_clk_pll_vco_freq_get(ALT_CLK_t pll,
                                         alt_freq_t* freq);
 
/******************************************************************************/
uint32_t alt_clk_pll_guard_band_get(ALT_CLK_t pll);
 
/******************************************************************************/
ALT_STATUS_CODE alt_clk_pll_guard_band_set(ALT_CLK_t pll,
                                           uint32_t guard_band);
 
/******************************************************************************/
ALT_STATUS_CODE alt_clk_divider_get(ALT_CLK_t clk,
                                    uint32_t* div);
 
/******************************************************************************/
ALT_STATUS_CODE alt_clk_divider_set(ALT_CLK_t clk,
                                    uint32_t div);
 
/******************************************************************************/
ALT_STATUS_CODE alt_clk_freq_get(ALT_CLK_t clk,
                                 alt_freq_t* freq);
 
/******************************************************************************/
/******************************************************************************/
ALT_STATUS_CODE alt_clk_irq_disable(ALT_CLK_PLL_LOCK_STATUS_t lock_stat_mask);
 
/******************************************************************************/
ALT_STATUS_CODE alt_clk_irq_enable(ALT_CLK_PLL_LOCK_STATUS_t lock_stat_mask);
 
/******************************************************************************/
/******************************************************************************/
ALT_STATUS_CODE alt_clk_group_cfg_raw_get(ALT_CLK_GRP_t clk_group,
                                          ALT_CLK_GROUP_RAW_CFG_t* clk_group_raw_cfg);
 
/******************************************************************************/
ALT_STATUS_CODE alt_clk_group_cfg_raw_set(const ALT_CLK_GROUP_RAW_CFG_t* clk_group_raw_cfg);
 
ALT_STATUS_CODE alt_clk_clkmgr_init(void);
 
#ifdef __cplusplus
}
 
#endif  /* __cplusplus */
#endif  /* __ALT_CLK_MGR_H__ */