RTEMS 6.1-rc5
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aarch32-pmsa.h
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1/* SPDX-License-Identifier: BSD-2-Clause */
2
12/*
13 * Copyright (C) 2020 embedded brains GmbH & Co. KG
14 *
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions
17 * are met:
18 * 1. Redistributions of source code must retain the above copyright
19 * notice, this list of conditions and the following disclaimer.
20 * 2. Redistributions in binary form must reproduce the above copyright
21 * notice, this list of conditions and the following disclaimer in the
22 * documentation and/or other materials provided with the distribution.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
28 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
35 */
36
37#ifndef _RTEMS_SCORE_AARCH32_PMSA_H
38#define _RTEMS_SCORE_AARCH32_PMSA_H
39
41
42#ifdef __cplusplus
43extern "C" {
44#endif
45
57#define AARCH32_PMSA_MIN_REGION_ALIGN 64
58
59#define AARCH32_PMSA_ATTR_EN 0x1U
60
61#define AARCH32_PMSA_ATTR_IDX_SHIFT 1
62#define AARCH32_PMSA_ATTR_IDX_MASK 0xeU
63#define AARCH32_PMSA_ATTR_IDX( _idx ) \
64 ( ( _idx ) << AARCH32_PMSA_ATTR_IDX_SHIFT )
65
66#define AARCH32_PMSA_ATTR_XN 0x40U
67
68#define AARCH32_PMSA_ATTR_AP_SHIFT 7
69#define AARCH32_PMSA_ATTR_AP_MASK 0x18U
70#define AARCH32_PMSA_ATTR_AP( _ap ) \
71 ( ( _ap ) << AARCH32_PMSA_ATTR_AP_SHIFT )
72#define AARCH32_PMSA_ATTR_AP_EL1_RW_EL0_NO 0x0U
73#define AARCH32_PMSA_ATTR_AP_EL1_RW_EL0_RW 0x1U
74#define AARCH32_PMSA_ATTR_AP_EL1_RO_EL0_NO 0x2U
75#define AARCH32_PMSA_ATTR_AP_EL1_RO_EL0_RO 0x3U
76
77#define AARCH32_PMSA_ATTR_SH_SHIFT 9
78#define AARCH32_PMSA_ATTR_SH_MASK 0x600U
79#define AARCH32_PMSA_ATTR_SH( _sh ) \
80 ( ( _sh ) << AARCH32_PMSA_ATTR_SH_SHIFT )
81#define AARCH32_PMSA_ATTR_SH_NO 0x0U
82#define AARCH32_PMSA_ATTR_SH_RES 0x1U
83#define AARCH32_PMSA_ATTR_SH_OUTER 0x2U
84#define AARCH32_PMSA_ATTR_SH_INNER 0x3U
85
86#define AARCH32_PMSA_MEM_DEVICE_NG_NR_NE 0x00U
87#define AARCH32_PMSA_MEM_DEVICE_NG_NR_E 0x04U
88#define AARCH32_PMSA_MEM_DEVICE_NG_R_E 0x08U
89#define AARCH32_PMSA_MEM_DEVICE_G_R_E 0x0cU
90
91#define AARCH32_PMSA_MEM_OUTER_WTT 0x00U
92#define AARCH32_PMSA_MEM_OUTER_NC 0x40U
93#define AARCH32_PMSA_MEM_OUTER_WBT 0x40U
94#define AARCH32_PMSA_MEM_OUTER_WTNT 0x80U
95#define AARCH32_PMSA_MEM_OUTER_WBNT 0xc0U
96
97#define AARCH32_PMSA_MEM_OUTER_RA 0x20U
98#define AARCH32_PMSA_MEM_OUTER_WA 0x10U
99
100#define AARCH32_PMSA_MEM_INNER_WTT 0x00U
101#define AARCH32_PMSA_MEM_INNER_NC 0x04U
102#define AARCH32_PMSA_MEM_INNER_WBT 0x04U
103#define AARCH32_PMSA_MEM_INNER_WTNT 0x08U
104#define AARCH32_PMSA_MEM_INNER_WBNT 0x0cU
105
106#define AARCH32_PMSA_MEM_INNER_RA 0x02U
107#define AARCH32_PMSA_MEM_INNER_WA 0x01U
108
109#define AARCH32_PMSA_MEM_ATTR( _ma0, _ma1, _ma2, _ma3 ) \
110 ( ( _ma0 ) | ( ( _ma1 ) << 8 ) | ( ( _ma2 ) << 16 ) | ( ( _ma3 ) << 24 ) )
111
112#define AARCH32_PMSA_MEM_ATTR_DEFAULT_CACHED \
113 ( AARCH32_PMSA_MEM_OUTER_WBNT | \
114 AARCH32_PMSA_MEM_OUTER_RA | \
115 AARCH32_PMSA_MEM_OUTER_WA | \
116 AARCH32_PMSA_MEM_INNER_WBNT | \
117 AARCH32_PMSA_MEM_INNER_RA | \
118 AARCH32_PMSA_MEM_INNER_WA )
119
120#define AARCH32_PMSA_MEM_ATTR_DEFAULT_UNCACHED \
121 ( AARCH32_PMSA_MEM_OUTER_NC | \
122 AARCH32_PMSA_MEM_INNER_NC )
123
124#define AARCH32_PMSA_MEM_ATTR_DEFAULT_DEVICE \
125 AARCH32_PMSA_MEM_DEVICE_NG_NR_NE
126
127#define AARCH32_PMSA_CODE_CACHED \
128 ( AARCH32_PMSA_ATTR_EN | \
129 AARCH32_PMSA_ATTR_AP( AARCH32_PMSA_ATTR_AP_EL1_RO_EL0_NO ) | \
130 AARCH32_PMSA_ATTR_SH( AARCH32_PMSA_ATTR_SH_NO ) | \
131 AARCH32_PMSA_ATTR_IDX( 0U ) )
132
133#define AARCH32_PMSA_CODE_UNCACHED \
134 ( AARCH32_PMSA_ATTR_EN | \
135 AARCH32_PMSA_ATTR_AP( AARCH32_PMSA_ATTR_AP_EL1_RO_EL0_NO ) | \
136 AARCH32_PMSA_ATTR_SH( AARCH32_PMSA_ATTR_SH_NO ) | \
137 AARCH32_PMSA_ATTR_IDX( 1U ) )
138
139#define AARCH32_PMSA_DATA_READ_ONLY_CACHED \
140 ( AARCH32_PMSA_ATTR_EN | \
141 AARCH32_PMSA_ATTR_XN | \
142 AARCH32_PMSA_ATTR_AP( AARCH32_PMSA_ATTR_AP_EL1_RO_EL0_NO ) | \
143 AARCH32_PMSA_ATTR_SH( AARCH32_PMSA_ATTR_SH_NO ) | \
144 AARCH32_PMSA_ATTR_IDX( 0U ) )
145
146#define AARCH32_PMSA_DATA_READ_ONLY_UNCACHED \
147 ( AARCH32_PMSA_ATTR_EN | \
148 AARCH32_PMSA_ATTR_XN | \
149 AARCH32_PMSA_ATTR_AP( AARCH32_PMSA_ATTR_AP_EL1_RO_EL0_NO ) | \
150 AARCH32_PMSA_ATTR_SH( AARCH32_PMSA_ATTR_SH_NO ) | \
151 AARCH32_PMSA_ATTR_IDX( 1U ) )
152
153#define AARCH32_PMSA_DATA_READ_WRITE_CACHED \
154 ( AARCH32_PMSA_ATTR_EN | \
155 AARCH32_PMSA_ATTR_XN | \
156 AARCH32_PMSA_ATTR_AP( AARCH32_PMSA_ATTR_AP_EL1_RW_EL0_NO ) | \
157 AARCH32_PMSA_ATTR_SH( AARCH32_PMSA_ATTR_SH_NO ) | \
158 AARCH32_PMSA_ATTR_IDX( 0U ) )
159
160#define AARCH32_PMSA_DATA_READ_WRITE_UNCACHED \
161 ( AARCH32_PMSA_ATTR_EN | \
162 AARCH32_PMSA_ATTR_XN | \
163 AARCH32_PMSA_ATTR_AP( AARCH32_PMSA_ATTR_AP_EL1_RW_EL0_NO ) | \
164 AARCH32_PMSA_ATTR_SH( AARCH32_PMSA_ATTR_SH_NO ) | \
165 AARCH32_PMSA_ATTR_IDX( 1U ) )
166
167#define AARCH32_PMSA_DATA_READ_WRITE_SHARED \
168 ( AARCH32_PMSA_ATTR_EN | \
169 AARCH32_PMSA_ATTR_XN | \
170 AARCH32_PMSA_ATTR_AP( AARCH32_PMSA_ATTR_AP_EL1_RW_EL0_NO ) | \
171 AARCH32_PMSA_ATTR_SH( AARCH32_PMSA_ATTR_SH_OUTER ) | \
172 AARCH32_PMSA_ATTR_IDX( 1U ) )
173
174#define AARCH32_PMSA_DEVICE \
175 ( AARCH32_PMSA_ATTR_EN | \
176 AARCH32_PMSA_ATTR_XN | \
177 AARCH32_PMSA_ATTR_AP( AARCH32_PMSA_ATTR_AP_EL1_RW_EL0_NO ) | \
178 AARCH32_PMSA_ATTR_SH( AARCH32_PMSA_ATTR_SH_NO ) | \
179 AARCH32_PMSA_ATTR_IDX( 2U ) )
180
181/*
182 * The Cortex-R52 processor is not coherent and the inner shareability domain
183 * consists of an individual Cortex-R52 core. Thus for an SMP configuration,
184 * the read-write data must be configured as Non-cachable and Shareable. The
185 * outer shareability domain is external to the Cortex-R52 processor.
186 */
187#if defined(RTEMS_SMP)
188#define AARCH32_PMSA_DATA_READ_WRITE_DEFAULT \
189 AARCH32_PMSA_DATA_READ_WRITE_SHARED
190#else
191#define AARCH32_PMSA_DATA_READ_WRITE_DEFAULT \
192 AARCH32_PMSA_DATA_READ_WRITE_CACHED
193#endif
194
202#define AARCH32_PMSA_DEFAULT_SECTIONS \
203 { \
204 .begin = (uint32_t) bsp_section_fast_text_begin, \
205 .end = (uint32_t) bsp_section_fast_text_end, \
206 .attributes = AARCH32_PMSA_CODE_CACHED \
207 }, { \
208 .begin = (uint32_t) bsp_section_fast_data_begin, \
209 .end = (uint32_t) bsp_section_fast_data_end, \
210 .attributes = AARCH32_PMSA_DATA_READ_WRITE_DEFAULT \
211 }, { \
212 .begin = (uint32_t) bsp_section_start_begin, \
213 .end = (uint32_t) bsp_section_start_end, \
214 .attributes = AARCH32_PMSA_CODE_CACHED \
215 }, { \
216 .begin = (uint32_t) bsp_section_vector_begin, \
217 .end = (uint32_t) bsp_section_vector_end, \
218 .attributes = AARCH32_PMSA_CODE_CACHED \
219 }, { \
220 .begin = (uint32_t) bsp_section_text_begin, \
221 .end = (uint32_t) bsp_section_text_end, \
222 .attributes = AARCH32_PMSA_CODE_CACHED \
223 }, { \
224 .begin = (uint32_t) bsp_section_rodata_begin, \
225 .end = (uint32_t) bsp_section_rodata_end, \
226 .attributes = AARCH32_PMSA_DATA_READ_ONLY_CACHED \
227 }, { \
228 .begin = (uint32_t) bsp_section_data_begin, \
229 .end = (uint32_t) bsp_section_data_end, \
230 .attributes = AARCH32_PMSA_DATA_READ_WRITE_DEFAULT \
231 }, { \
232 .begin = (uint32_t) bsp_section_bss_begin, \
233 .end = (uint32_t) bsp_section_bss_end, \
234 .attributes = AARCH32_PMSA_DATA_READ_WRITE_DEFAULT \
235 }, { \
236 .begin = (uint32_t) bsp_section_rtemsstack_begin, \
237 .end = (uint32_t) bsp_section_rtemsstack_end, \
238 .attributes = AARCH32_PMSA_DATA_READ_WRITE_DEFAULT \
239 }, { \
240 .begin = (uint32_t) bsp_section_work_begin, \
241 .end = (uint32_t) bsp_section_work_end, \
242 .attributes = AARCH32_PMSA_DATA_READ_WRITE_DEFAULT \
243 }, { \
244 .begin = (uint32_t) bsp_section_stack_begin, \
245 .end = (uint32_t) bsp_section_stack_end, \
246 .attributes = AARCH32_PMSA_DATA_READ_WRITE_DEFAULT \
247 }, { \
248 .begin = (uint32_t) bsp_section_nocache_begin, \
249 .end = (uint32_t) bsp_section_nocache_end, \
250 .attributes = AARCH32_PMSA_DATA_READ_WRITE_UNCACHED \
251 }, { \
252 .begin = (uint32_t) bsp_section_nocachenoload_begin, \
253 .end = (uint32_t) bsp_section_nocachenoload_end, \
254 .attributes = AARCH32_PMSA_DATA_READ_WRITE_UNCACHED \
255 }
256
263typedef struct {
267 uint32_t begin;
268
272 uint32_t end;
273
277 uint32_t attributes;
279
286typedef struct {
292 uint32_t base;
293
299 uint32_t limit;
300
304 uint32_t attributes;
306
326 uint32_t memory_attributes_0,
327 uint32_t memory_attributes_1,
328 const AArch32_PMSA_Section *sections,
329 size_t section_count
330);
331
351 const AArch32_PMSA_Section *sections,
352 size_t section_count,
353 AArch32_PMSA_Region *regions,
354 size_t region_max
355);
356
366
371extern const size_t _AArch32_PMSA_Section_count;
372
381
384#ifdef __cplusplus
385}
386#endif
387
388#endif /* _RTEMS_SCORE_AARCH32_PMSA_H */
This header file provides basic definitions used by the API and the implementation.
const size_t _AArch32_PMSA_Section_count
This constant provides the count of elements in _AArch32_PMSA_Sections.
Definition: pmsa-sections.c:55
void _AArch32_PMSA_Initialize(uint32_t memory_attributes_0, uint32_t memory_attributes_1, const AArch32_PMSA_Section *sections, size_t section_count)
Initializes the Memory Protection Unit (MPU).
const AArch32_PMSA_Section _AArch32_PMSA_Sections[]
This array provides section definitions to initialize the memory protection unit (MPU).
Definition: pmsa-sections.c:46
size_t _AArch32_PMSA_Map_sections_to_regions(const AArch32_PMSA_Section *sections, size_t section_count, AArch32_PMSA_Region *regions, size_t region_max)
Maps the section definitions to region definitions.
void _AArch32_PMSA_Initialize_default(void)
Initializes the Memory Protection Unit (MPU) using the section definitions with default memory attrib...
The region definition is used to configure the Memory Protection Unit (MPU).
Definition: aarch32-pmsa.h:286
uint32_t base
This member defines the base address of the region.
Definition: aarch32-pmsa.h:292
uint32_t attributes
This member defines the attributes of the region.
Definition: aarch32-pmsa.h:304
uint32_t limit
This member defines the limit address of the region.
Definition: aarch32-pmsa.h:299
The section definition is used to initialize the Memory Protection Unit (MPU).
Definition: aarch32-pmsa.h:263
uint32_t begin
This member defines the begin address of the section.
Definition: aarch32-pmsa.h:267
uint32_t attributes
This member defines the attributes of the section.
Definition: aarch32-pmsa.h:277
uint32_t end
This member defines the end address of the section.
Definition: aarch32-pmsa.h:272