RTEMS 6.1-rc4
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zynq-uart-regs.h
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1
9/*
10 * SPDX-License-Identifier: BSD-2-Clause
11 *
12 * Copyright (C) 2013 embedded brains GmbH & Co. KG
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions
16 * are met:
17 * 1. Redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer.
19 * 2. Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in the
21 * documentation and/or other materials provided with the distribution.
22 *
23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
33 * POSSIBILITY OF SUCH DAMAGE.
34 */
35
46#ifndef LIBBSP_ARM_XILINX_ZYNQ_UART_REGS_H
47#define LIBBSP_ARM_XILINX_ZYNQ_UART_REGS_H
48
49#include <bsp/utility.h>
50
51#define ZYNQ_UART_DEFAULT_BAUD 115200
52
53#define ZYNQ_UART_FIFO_DEPTH 64
54
55typedef struct zynq_uart {
56 uint32_t control;
57#define ZYNQ_UART_CONTROL_STPBRK BSP_BIT32(8)
58#define ZYNQ_UART_CONTROL_STTBRK BSP_BIT32(7)
59#define ZYNQ_UART_CONTROL_RSTTO BSP_BIT32(6)
60#define ZYNQ_UART_CONTROL_TXDIS BSP_BIT32(5)
61#define ZYNQ_UART_CONTROL_TXEN BSP_BIT32(4)
62#define ZYNQ_UART_CONTROL_RXDIS BSP_BIT32(3)
63#define ZYNQ_UART_CONTROL_RXEN BSP_BIT32(2)
64#define ZYNQ_UART_CONTROL_TXRES BSP_BIT32(1)
65#define ZYNQ_UART_CONTROL_RXRES BSP_BIT32(0)
66 uint32_t mode;
67#define ZYNQ_UART_MODE_CHMODE(val) BSP_FLD32(val, 8, 9)
68#define ZYNQ_UART_MODE_CHMODE_GET(reg) BSP_FLD32GET(reg, 8, 9)
69#define ZYNQ_UART_MODE_CHMODE_SET(reg, val) BSP_FLD32SET(reg, val, 8, 9)
70#define ZYNQ_UART_MODE_CHMODE_NORMAL 0x00U
71#define ZYNQ_UART_MODE_CHMODE_AUTO_ECHO 0x01U
72#define ZYNQ_UART_MODE_CHMODE_LOCAL_LOOPBACK 0x02U
73#define ZYNQ_UART_MODE_CHMODE_REMOTE_LOOPBACK 0x03U
74#define ZYNQ_UART_MODE_NBSTOP(val) BSP_FLD32(val, 6, 7)
75#define ZYNQ_UART_MODE_NBSTOP_GET(reg) BSP_FLD32GET(reg, 6, 7)
76#define ZYNQ_UART_MODE_NBSTOP_SET(reg, val) BSP_FLD32SET(reg, val, 6, 7)
77#define ZYNQ_UART_MODE_NBSTOP_STOP_1 0x00U
78#define ZYNQ_UART_MODE_NBSTOP_STOP_1_5 0x01U
79#define ZYNQ_UART_MODE_NBSTOP_STOP_2 0x02U
80#define ZYNQ_UART_MODE_PAR(val) BSP_FLD32(val, 3, 5)
81#define ZYNQ_UART_MODE_PAR_GET(reg) BSP_FLD32GET(reg, 3, 5)
82#define ZYNQ_UART_MODE_PAR_SET(reg, val) BSP_FLD32SET(reg, val, 3, 5)
83#define ZYNQ_UART_MODE_PAR_EVEN 0x00U
84#define ZYNQ_UART_MODE_PAR_ODD 0x01U
85#define ZYNQ_UART_MODE_PAR_SPACE 0x02U
86#define ZYNQ_UART_MODE_PAR_MARK 0x03U
87#define ZYNQ_UART_MODE_PAR_NONE 0x04U
88#define ZYNQ_UART_MODE_CHRL(val) BSP_FLD32(val, 1, 2)
89#define ZYNQ_UART_MODE_CHRL_GET(reg) BSP_FLD32GET(reg, 1, 2)
90#define ZYNQ_UART_MODE_CHRL_SET(reg, val) BSP_FLD32SET(reg, val, 1, 2)
91#define ZYNQ_UART_MODE_CHRL_8 0x00U
92#define ZYNQ_UART_MODE_CHRL_7 0x02U
93#define ZYNQ_UART_MODE_CHRL_6 0x03U
94#define ZYNQ_UART_MODE_CLKS BSP_BIT32(0)
95 uint32_t irq_en;
96 uint32_t irq_dis;
97 uint32_t irq_mask;
98 uint32_t irq_sts;
99#define ZYNQ_UART_TOVR BSP_BIT32(12)
100#define ZYNQ_UART_TNFUL BSP_BIT32(11)
101#define ZYNQ_UART_TTRIG BSP_BIT32(10)
102#define ZYNQ_UART_DMSI BSP_BIT32(9)
103#define ZYNQ_UART_TIMEOUT BSP_BIT32(8)
104#define ZYNQ_UART_PARE BSP_BIT32(7)
105#define ZYNQ_UART_FRAME BSP_BIT32(6)
106#define ZYNQ_UART_ROVR BSP_BIT32(5)
107#define ZYNQ_UART_TFUL BSP_BIT32(4)
108#define ZYNQ_UART_TEMPTY BSP_BIT32(3)
109#define ZYNQ_UART_RFUL BSP_BIT32(2)
110#define ZYNQ_UART_REMPTY BSP_BIT32(1)
111#define ZYNQ_UART_RTRIG BSP_BIT32(0)
112 uint32_t baud_rate_gen;
113#define ZYNQ_UART_BAUD_RATE_GEN_CD(val) BSP_FLD32(val, 0, 15)
114#define ZYNQ_UART_BAUD_RATE_GEN_CD_GET(reg) BSP_FLD32GET(reg, 0, 15)
115#define ZYNQ_UART_BAUD_RATE_GEN_CD_SET(reg, val) BSP_FLD32SET(reg, val, 0, 15)
116 uint32_t rx_timeout;
117#define ZYNQ_UART_RX_TIMEOUT_RTO(val) BSP_FLD32(val, 0, 7)
118#define ZYNQ_UART_RX_TIMEOUT_RTO_GET(reg) BSP_FLD32GET(reg, 0, 7)
119#define ZYNQ_UART_RX_TIMEOUT_RTO_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7)
120 uint32_t rx_fifo_trg_lvl;
121#define ZYNQ_UART_RX_FIFO_TRG_LVL_RTRIG(val) BSP_FLD32(val, 0, 5)
122#define ZYNQ_UART_RX_FIFO_TRG_LVL_RTRIG_GET(reg) BSP_FLD32GET(reg, 0, 5)
123#define ZYNQ_UART_RX_FIFO_TRG_LVL_RTRIG_SET(reg, val) BSP_FLD32SET(reg, val, 0, 5)
124 uint32_t modem_ctrl;
125#define ZYNQ_UART_MODEM_CTRL_FCM BSP_BIT32(5)
126#define ZYNQ_UART_MODEM_CTRL_RTS BSP_BIT32(1)
127#define ZYNQ_UART_MODEM_CTRL_DTR BSP_BIT32(0)
128 uint32_t modem_sts;
129#define ZYNQ_UART_MODEM_STS_FCMS BSP_BIT32(8)
130#define ZYNQ_UART_MODEM_STS_DCD BSP_BIT32(7)
131#define ZYNQ_UART_MODEM_STS_RI BSP_BIT32(6)
132#define ZYNQ_UART_MODEM_STS_DSR BSP_BIT32(5)
133#define ZYNQ_UART_MODEM_STS_CTS BSP_BIT32(4)
134#define ZYNQ_UART_MODEM_STS_DDCD BSP_BIT32(3)
135#define ZYNQ_UART_MODEM_STS_TERI BSP_BIT32(2)
136#define ZYNQ_UART_MODEM_STS_DDSR BSP_BIT32(1)
137#define ZYNQ_UART_MODEM_STS_DCTS BSP_BIT32(0)
138 uint32_t channel_sts;
139#define ZYNQ_UART_CHANNEL_STS_TNFUL BSP_BIT32(14)
140#define ZYNQ_UART_CHANNEL_STS_TTRIG BSP_BIT32(13)
141#define ZYNQ_UART_CHANNEL_STS_FDELT BSP_BIT32(12)
142#define ZYNQ_UART_CHANNEL_STS_TACTIVE BSP_BIT32(11)
143#define ZYNQ_UART_CHANNEL_STS_RACTIVE BSP_BIT32(10)
144#define ZYNQ_UART_CHANNEL_STS_TFUL BSP_BIT32(4)
145#define ZYNQ_UART_CHANNEL_STS_TEMPTY BSP_BIT32(3)
146#define ZYNQ_UART_CHANNEL_STS_RFUL BSP_BIT32(2)
147#define ZYNQ_UART_CHANNEL_STS_REMPTY BSP_BIT32(1)
148#define ZYNQ_UART_CHANNEL_STS_RTRIG BSP_BIT32(0)
149 uint32_t tx_rx_fifo;
150#define ZYNQ_UART_TX_RX_FIFO_FIFO(val) BSP_FLD32(val, 0, 7)
151#define ZYNQ_UART_TX_RX_FIFO_FIFO_GET(reg) BSP_FLD32GET(reg, 0, 7)
152#define ZYNQ_UART_TX_RX_FIFO_FIFO_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7)
153 uint32_t baud_rate_div;
154#define ZYNQ_UART_BAUD_RATE_DIV_BDIV(val) BSP_FLD32(val, 0, 7)
155#define ZYNQ_UART_BAUD_RATE_DIV_BDIV_GET(reg) BSP_FLD32GET(reg, 0, 7)
156#define ZYNQ_UART_BAUD_RATE_DIV_BDIV_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7)
157 uint32_t flow_delay;
158#define ZYNQ_UART_FLOW_DELAY_FDEL(val) BSP_FLD32(val, 0, 5)
159#define ZYNQ_UART_FLOW_DELAY_FDEL_GET(reg) BSP_FLD32GET(reg, 0, 5)
160#define ZYNQ_UART_FLOW_DELAY_FDEL_SET(reg, val) BSP_FLD32SET(reg, val, 0, 5)
161 uint32_t reserved_3c[2];
162 uint32_t tx_fifo_trg_lvl;
163#define ZYNQ_UART_TX_FIFO_TRG_LVL_TTRIG(val) BSP_FLD32(val, 0, 5)
164#define ZYNQ_UART_TX_FIFO_TRG_LVL_TTRIG_GET(reg) BSP_FLD32GET(reg, 0, 5)
165#define ZYNQ_UART_TX_FIFO_TRG_LVL_TTRIG_SET(reg, val) BSP_FLD32SET(reg, val, 0, 5)
166} zynq_uart;
167
168void zynq_uart_initialize(volatile zynq_uart *regs);
169
170int zynq_uart_read_char_polled(volatile zynq_uart *regs);
171
172void zynq_uart_write_char_polled(volatile zynq_uart *regs, char c);
173
177void zynq_uart_reset_tx_flush(volatile zynq_uart *regs);
178
182uint32_t zynq_uart_input_clock(void);
183
204 uint32_t desired_baud,
205 uint32_t mode_clks,
206 uint32_t *cd_ptr,
207 uint32_t *bdiv_ptr
208);
209
212#endif /* LIBBSP_ARM_XILINX_ZYNQ_UART_REGS_H */
void zynq_uart_reset_tx_flush(volatile zynq_uart *regs)
Definition: zynq-uart-polled.c:160
uint32_t zynq_uart_input_clock(void)
Returns the Zynq UART input clock frequency in Hz.
Definition: zynq-uart-input-clock.c:41
uint32_t zynq_uart_calculate_baud(uint32_t desired_baud, uint32_t mode_clks, uint32_t *cd_ptr, uint32_t *bdiv_ptr)
Calculates the clock and baud divisor of the best approximation of the desired baud.
Definition: zynq-uart-polled.c:60
This header file provides utility macros for BSPs.
Definition: intercom.c:87
Definition: zynq-uart-regs.h:55