RTEMS 6.1-rc4
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zynq-devcfg-regs.h
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1/* SPDX-License-Identifier: BSD-2-Clause */
2
9/*
10 * Copyright (c) 2016
11 * NSF Center for High-Performance Reconfigurable Computing (CHREC),
12 * University of Florida. All rights reserved.
13 * Copyright (c) 2017
14 * NSF Center for High-Performance Reconfigurable Computing (CHREC),
15 * University of Pittsburgh. All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met:
20 * 1. Redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer.
22 * 2. Redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
27 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
29 * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER
30 * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
31 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
32 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
33 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
34 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
35 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
36 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 *
38 * The views and conclusions contained in the software and documentation
39 * are those of the authors and should not be interpreted as representing
40 * official policies, either expressed or implied, of CHREC.
41 *
42 * Author: Patrick Gauvin <gauvin@hcs.ufl.edu>
43 */
44
51#ifndef LIBBSP_ARM_XILINX_ZYNQ_DEVCFG_REGS_H
52#define LIBBSP_ARM_XILINX_ZYNQ_DEVCFG_REGS_H
53
54#include <stdint.h>
55#include <bsp/utility.h>
56
57#ifdef __cplusplus
58extern "C" {
59#endif /* __cplusplus */
60
61/* Zynq-7000 series devcfg address */
62#define ZYNQ_DEVCFG_BASE_ADDR 0xF8007000UL
63/* For use with the PCAP DMA */
64#define ZYNQ_DEVCFG_BITSTREAM_ADDR 0xFFFFFFFFUL
65#define ZYNQ_DEVCFG_INTERRUPT_VECTOR 40
66
67typedef struct {
68 uint32_t ctrl;
69#define ZYNQ_DEVCFG_CTRL_FORCE_RST( val ) BSP_FLD32( val, 31, 31 )
70#define ZYNQ_DEVCFG_CTRL_FORCE_RST_GET( reg ) BSP_FLD32GET( reg, 31, 31 )
71#define ZYNQ_DEVCFG_CTRL_PCFG_PROG_B_GET( reg ) BSP_FLD32GET( reg, 30, 30 )
72#define ZYNQ_DEVCFG_CTRL_PCFG_PROG_B( val ) BSP_FLD32( val, 30, 30 )
73#define ZYNQ_DEVCFG_CTRL_PCFG_POR_CNT_4K_GET( reg ) BSP_FLD32GET( reg, 29, 29 )
74#define ZYNQ_DEVCFG_CTRL_PCFG_POR_CNT_4K( val ) BSP_FLD32( val, 29, 29 )
75#define ZYNQ_DEVCFG_CTRL_PCAP_PR( val ) BSP_FLD32( val, 27, 27 )
76#define ZYNQ_DEVCFG_CTRL_PCAP_PR_GET( reg ) BSP_FLD32GET( reg, 27, 27 )
77#define ZYNQ_DEVCFG_CTRL_PCAP_PR_ICAP ( 0 )
78#define ZYNQ_DEVCFG_CTRL_PCAP_PR_PCAP ( 1 )
79#define ZYNQ_DEVCFG_CTRL_PCAP_MODE( val ) BSP_FLD32( val, 26, 26 )
80#define ZYNQ_DEVCFG_CTRL_PCAP_MODE_GET( reg ) BSP_FLD32GET( reg, 26, 26 )
81#define ZYNQ_DEVCFG_CTRL_QUARTER_PCAP_RATE_EN( val ) BSP_FLD32( val, 25, 25 )
82#define ZYNQ_DEVCFG_CTRL_QUARTER_PCAP_RATE_EN_GET( reg ) \
83 BSP_FLD32GET( reg, 25, 25 )
84#define ZYNQ_DEVCFG_CTRL_MULTIBOOT_EN( val ) BSP_FLD32( val, 24, 24 )
85#define ZYNQ_DEVCFG_CTRL_MULTIBOOT_EN_GET( reg ) BSP_FLD32GET( reg, 24, 24 )
86#define ZYNQ_DEVCFG_CTRL_JTAG_CHAIN_DIS( val ) BSP_FLD32( val, 23, 23 )
87#define ZYNQ_DEVCFG_CTRL_JTAG_CHAIN_DIS_GET( reg ) BSP_FLD32GET( reg, 23, 23 )
88#define ZYNQ_DEVCFG_CTRL_PCFG_AES_FUSE( val ) BSP_FLD32( val, 12, 12 )
89#define ZYNQ_DEVCFG_CTRL_PCFG_AES_FUSE_GET( reg ) BSP_FLD32GET( reg, 12, 12 )
90#define ZYNQ_DEVCFG_CTRL_PCFG_AES_FUSE_BBRAM ( 0 )
91#define ZYNQ_DEVCFG_CTRL_PCFG_AES_FUSE_EFUSE ( 1 )
92#define ZYNQ_DEVCFG_CTRL_PCFG_AES_EN( val ) BSP_FLD32( val, 9, 11 )
93#define ZYNQ_DEVCFG_CTRL_PCFG_AES_EN_GET( reg ) BSP_FLD32GET( reg, 9, 11 )
94#define ZYNQ_DEVCFG_CTRL_PCFG_AES_EN_ENABLE ( 0x3 )
95#define ZYNQ_DEVCFG_CTRL_PCFG_AES_EN_DISABLE ( 0x0 )
96#define ZYNQ_DEVCFG_CTRL_PCFG_AES_EN_LOCKDOWN ( 0x1 )
97#define ZYNQ_DEVCFG_CTRL_PCFG_SEU_EN( val ) BSP_FLD32( val, 8, 8 )
98#define ZYNQ_DEVCFG_CTRL_PCFG_SEU_EN_GET( reg ) BSP_FLD32GET( reg, 8, 8 )
99#define ZYNQ_DEVCFG_CTRL_PCFG_SEC_EN_GET( reg ) BSP_FLD32GET( reg, 7, 7 )
100#define ZYNQ_DEVCFG_CTRL_PCFG_SPNIDEN( val ) BSP_FLD32( val, 6, 6 )
101#define ZYNQ_DEVCFG_CTRL_PCFG_SPNIDEN_GET( reg ) BSP_FLD32GET( reg, 6, 6 )
102#define ZYNQ_DEVCFG_CTRL_PCFG_SPIDEN( val ) BSP_FLD32( val, 5, 5 )
103#define ZYNQ_DEVCFG_CTRL_PCFG_SPIDEN_GET( reg ) BSP_FLD32GET( reg, 5, 5 )
104#define ZYNQ_DEVCFG_CTRL_PCFG_NIDEN( val ) BSP_FLD32( val, 4, 4 )
105#define ZYNQ_DEVCFG_CTRL_PCFG_NIDEN_GET( reg ) BSP_FLD32GET( reg, 4, 4 )
106#define ZYNQ_DEVCFG_CTRL_PCFG_DBGEN( val ) BSP_FLD32( val, 3, 3 )
107#define ZYNQ_DEVCFG_CTRL_PCFG_DBGEN_GET( reg ) BSP_FLD32GET( reg, 3, 3 )
108#define ZYNQ_DEVCFG_CTRL_PCFG_DAP_EN( val ) BSP_FLD32( val, 0, 2 )
109#define ZYNQ_DEVCFG_CTRL_PCFG_DAP_EN_GET( reg ) BSP_FLD32GET( reg, 0, 2 )
110#define ZYNQ_DEVCFG_CTRL_PCFG_DAP_EN_ENABLE ( 0x3 )
111#define ZYNQ_DEVCFG_CTRL_PCFG_DAP_EN_BYPASS ( 0x0 )
112#define ZYNQ_DEVCFG_CTRL_RESERVED_BITS ( 0x6000 )
113 uint32_t lock;
114 uint32_t cfg;
115 /* int_sts and int_mask directly overlap, so they share the ZYNQ_DEVCFG_INT_*
116 * macros */
117 uint32_t int_sts;
118 uint32_t int_mask;
119#define ZYNQ_DEVCFG_INT_PSS_CFG_RESET_B_INT BSP_BIT32( 27 )
120#define ZYNQ_DEVCFG_INT_PSS_CFG_RESET_B_INT_GET( reg ) \
121 BSP_FLD32GET( reg, 27, 27 )
122#define ZYNQ_DEVCFG_INT_AXI_WERR_INT_GET( reg ) BSP_FLD32GET( reg, 22, 22 )
123#define ZYNQ_DEVCFG_INT_AXI_RTO_INT_GET( reg ) BSP_FLD32GET( reg, 21, 21 )
124#define ZYNQ_DEVCFG_INT_AXI_RERR_INT_GET( reg ) BSP_FLD32GET( reg, 20, 20 )
125#define ZYNQ_DEVCFG_INT_RX_FIFO_OV_INT_GET( reg ) \
126 BSP_FLD32GET( reg, 18, 18 )
127#define ZYNQ_DEVCFG_INT_DMA_CMD_ERR_INT_GET( reg ) \
128 BSP_FLD32GET( reg, 15, 15 )
129#define ZYNQ_DEVCFG_INT_DMA_Q_OV_INT_GET( reg ) BSP_FLD32GET( reg, 14, 14 )
130#define ZYNQ_DEVCFG_INT_DMA_DONE_INT BSP_BIT32( 13 )
131#define ZYNQ_DEVCFG_INT_DMA_DONE_INT_GET( reg ) BSP_FLD32GET( reg, 13, 13 )
132#define ZYNQ_DEVCFG_INT_D_P_DONE_INT BSP_BIT32( 12 )
133#define ZYNQ_DEVCFG_INT_D_P_DONE_INT_GET( reg ) BSP_FLD32GET( reg, 12, 12 )
134#define ZYNQ_DEVCFG_INT_P2D_LEN_ERR_INT_GET( reg ) \
135 BSP_FLD32GET( reg, 11, 11 )
136#define ZYNQ_DEVCFG_INT_PCFG_HMAC_ERR_INT_GET( reg ) \
137 BSP_FLD32GET( reg, 6, 6 )
138#define ZYNQ_DEVCFG_INT_PCFG_SEU_ERR_INT_GET( reg ) \
139 BSP_FLD32GET( reg, 5, 5 )
140#define ZYNQ_DEVCFG_INT_PCFG_POR_B_INT_GET( reg ) BSP_FLD32GET( reg, 4, 4 )
141#define ZYNQ_DEVCFG_INT_PCFG_CFG_RST_INT_GET( reg ) \
142 BSP_FLD32GET( reg, 3, 3 )
143#define ZYNQ_DEVCFG_INT_PCFG_DONE_INT BSP_BIT32( 2 )
144#define ZYNQ_DEVCFG_INT_PCFG_DONE_INT_GET( reg ) BSP_FLD32GET( reg, 2, 2 )
145#define ZYNQ_DEVCFG_INT_PCFG_INIT_PE_INT BSP_BIT32( 1 )
146#define ZYNQ_DEVCFG_INT_PCFG_INIT_PE_INT_GET( reg ) \
147 BSP_FLD32GET( reg, 1, 1 )
148#define ZYNQ_DEVCFG_INT_PCFG_INIT_NE_INT BSP_BIT32( 0 )
149#define ZYNQ_DEVCFG_INT_PCFG_INIT_NE_INT_GET( reg ) \
150 BSP_FLD32GET( reg, 0, 0 )
151#define ZYNQ_DEVCFG_INT_ALL ( 0xf8f7f87f )
152 uint32_t status;
153#define ZYNQ_DEVCFG_STATUS_DMA_CMD_Q_F( val ) BSP_FLD32( val, 31, 31 )
154#define ZYNQ_DEVCFG_STATUS_DMA_CMD_Q_F_GET( reg ) BSP_FLD32GET( reg, 31, 31 )
155#define ZYNQ_DEVCFG_STATUS_PCFG_INIT_GET( reg ) BSP_FLD32GET( reg, 4, 4 )
156 uint32_t dma_src_addr;
157#define ZYNQ_DEVCFG_DMA_SRC_ADDR_DMA_DONE_INT_WAIT_PCAP ( 0x1 )
158 uint32_t dma_dst_addr;
159#define ZYNQ_DEVCFG_DMA_DST_ADDR_DMA_DONE_INT_WAIT_PCAP ( 0x1 )
160 uint32_t dma_src_len;
161#define ZYNQ_DEVCFG_DMA_SRC_LEN_LEN( val ) BSP_FLD32( val, 0, 26 )
162 uint32_t dma_dest_len; /* (sic) */
163#define ZYNQ_DEVCFG_DMA_DEST_LEN_LEN( val ) BSP_FLD32( val, 0, 26 )
164 uint32_t reserved0;
165 uint32_t multiboot_addr;
166 uint32_t reserved1;
167 uint32_t unlock;
168 uint32_t reserved2[18];
169 uint32_t mctrl;
170#define ZYNQ_DEVCFG_MCTRL_PS_VERSION_GET( reg ) BSP_FLD32GET( reg, 28, 31 )
171#define ZYNQ_DEVCFG_MCTRL_PS_VERSION_1_0 0x0
172#define ZYNQ_DEVCFG_MCTRL_PS_VERSION_2_0 0x1
173#define ZYNQ_DEVCFG_MCTRL_PS_VERSION_3_0 0x2
174#define ZYNQ_DEVCFG_MCTRL_PS_VERSION_3_1 0x3
175#define ZYNQ_DEVCFG_MCTRL_PCFG_POR_B_GET( reg ) BSP_FLD32GET( reg, 8, 8 )
176#define ZYNQ_DEVCFG_MCTRL_INT_PCAP_LPBK_GET( reg ) BSP_FLD32GET( reg, 4, 4 )
177#define ZYNQ_DEVCFG_MCTRL_INT_PCAP_LPBK( val ) BSP_FLD32( val, 4, 4 )
178#define ZYNQ_DEVCFG_MCTRL_RESERVED_SET_BITS ( 0x800000 )
179#define ZYNQ_DEVCFG_MCTRL_RESERVED_UNSET_BITS ( 0x3 )
180#define ZYNQ_DEVCFG_MCTRL_SET( reg, val ) ( ( ( reg ) & \
181 ~ZYNQ_DEVCFG_MCTRL_RESERVED_UNSET_BITS ) | \
182 ZYNQ_DEVCFG_MCTRL_RESERVED_SET_BITS | ( val ) )
183 uint32_t reserved3[32];
184 uint32_t xadcif_cfg;
185 uint32_t xadcif_int_sts;
186 uint32_t xadcif_int_mask;
187 uint32_t xadcif_msts;
188 uint32_t xadcif_cmdfifo;
189 uint32_t xadcif_rdfifo;
190 uint32_t xadcif_mctrl;
191} zynq_devcfg_regs;
192
193#ifdef __cplusplus
194}
195#endif /* __cplusplus */
196
197#endif /* LIBBSP_ARM_XILINX_ZYNQ_DEVCFG_REGS_H */
utility.h
This header file provides utility macros for BSPs.
zynq_devcfg_regs
Definition: zynq-devcfg-regs.h:67
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