RTEMS 6.1-rc4
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xilinx-axi-i2c.h
1/* SPDX-License-Identifier: BSD-2-Clause */
2
3/*
4 * Copyright (c) 2016-2017 Chris Johns <chrisj@rtems.org> All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
26 */
27
28/*
29 * Xilinx AXI IIC Interface v2.0. See PG090.pdf.
30 *
31 * Note, only master support is provided and no dynamic mode by design.
32 *
33 * The clock set up is to be handled by the IP integrator. There are too many
34 * factors handling this in software.
35 */
36
37
38#ifndef XILINX_AXI_I2C_H
39#define XILINX_AXI_I2C_H
40
41#include <dev/i2c/i2c.h>
42
43/*
44 * The PL integrator controls the timing. This interface allows software to
45 * override those settings. It pays to check the timing with ChipScope.
46 *
47 * If you set the AXI bus frequency you can use the clock speed ioctl call to
48 * change the speed dymanically. The ioctl call overrides the defaults passed
49 * in.
50 *
51 * Set the valid mask to the values that are to be set.
52 */
53#define XILINX_AIX_I2C_AXI_CLOCK (1 << 0)
54#define XILINX_AIX_I2C_TSUSTA (1 << 1)
55#define XILINX_AIX_I2C_TSUSTO (1 << 2)
56#define XILINX_AIX_I2C_THDSTA (1 << 3)
57#define XILINX_AIX_I2C_TSUDAT (1 << 4)
58#define XILINX_AIX_I2C_TBUF (1 << 5)
59#define XILINX_AIX_I2C_THIGH (1 << 6)
60#define XILINX_AIX_I2C_TLOW (1 << 7)
61#define XILINX_AIX_I2C_THDDAT (1 << 8)
62#define XILINX_AIX_I2C_ALL_REGS (XILINX_AIX_I2C_TSUSTA | \
63 XILINX_AIX_I2C_TSUSTO | \
64 XILINX_AIX_I2C_THDSTA | \
65 XILINX_AIX_I2C_TSUDAT | \
66 XILINX_AIX_I2C_TBUF | \
67 XILINX_AIX_I2C_THIGH | \
68 XILINX_AIX_I2C_TLOW | \
69 XILINX_AIX_I2C_THDDAT)
70typedef struct
71{
72 uint32_t valid_mask;
73 uint32_t AXI_CLOCK;
74 uint32_t SCL_INERTIAL_DELAY;
75 uint32_t TSUSTA;
76 uint32_t TSUSTO;
77 uint32_t THDSTA;
78 uint32_t TSUDAT;
79 uint32_t TBUF;
80 uint32_t THIGH;
81 uint32_t TLOW;
82 uint32_t THDDAT;
84
85/*
86 * Register the driver.
87 *
88 * The driver can multipex a number of I2C buses (in master mode only) using
89 * the GPO port. The PL designer can use the output pins to select a bus. This
90 * is useful if connecting a number of slave devices that have limit selectable
91 * addresses.
92 *
93 * @param bus_path The driver's device path.
94 * @param register_base AXI base address.
95 * @param irq AXI FPGA interrupt.
96 * @param gpio_address Bits 12:15 of a slave address it written to the GPO.
97 * @param timing Override the default timing. NULL means no changes.
98 */
99int i2c_bus_register_xilinx_aix_i2c(const char* bus_path,
100 uintptr_t register_base,
102 bool ten_gpio,
103 const xilinx_aix_i2c_timing* timing);
104
105#endif
Inter-Integrated Circuit (I2C) Driver API.
ISR_Vector_number rtems_vector_number
This integer type represents interrupt vector numbers.
Definition: intr.h:102
Definition: xilinx-axi-i2c.h:71