RTEMS 6.1-rc4
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stm32h7xx_ll_mdma.h
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1
19/* Define to prevent recursive inclusion -------------------------------------*/
20#ifndef STM32H7xx_LL_MDMA_H
21#define STM32H7xx_LL_MDMA_H
22
23#ifdef __cplusplus
24extern "C" {
25#endif
26
27/* Includes ------------------------------------------------------------------*/
28#include "stm32h7xx.h"
29
34#if defined (MDMA)
35
41/* Private types -------------------------------------------------------------*/
42/* Private variables ---------------------------------------------------------*/
47/* Array used to get the MDMA channel register offset versus channel index LL_MDMA_CHANNEL_x */
48static const uint32_t LL_MDMA_CH_OFFSET_TAB[] =
49{
50 (uint32_t)(MDMA_Channel0_BASE - MDMA_BASE),
51 (uint32_t)(MDMA_Channel1_BASE - MDMA_BASE),
52 (uint32_t)(MDMA_Channel2_BASE - MDMA_BASE),
53 (uint32_t)(MDMA_Channel3_BASE - MDMA_BASE),
54 (uint32_t)(MDMA_Channel4_BASE - MDMA_BASE),
55 (uint32_t)(MDMA_Channel5_BASE - MDMA_BASE),
56 (uint32_t)(MDMA_Channel6_BASE - MDMA_BASE),
57 (uint32_t)(MDMA_Channel7_BASE - MDMA_BASE),
58 (uint32_t)(MDMA_Channel8_BASE - MDMA_BASE),
59 (uint32_t)(MDMA_Channel9_BASE - MDMA_BASE),
60 (uint32_t)(MDMA_Channel10_BASE - MDMA_BASE),
61 (uint32_t)(MDMA_Channel11_BASE - MDMA_BASE),
62 (uint32_t)(MDMA_Channel12_BASE - MDMA_BASE),
63 (uint32_t)(MDMA_Channel13_BASE - MDMA_BASE),
64 (uint32_t)(MDMA_Channel14_BASE - MDMA_BASE),
65 (uint32_t)(MDMA_Channel15_BASE - MDMA_BASE)
66};
67
72/* Private constants ---------------------------------------------------------*/
82/* Private macros ------------------------------------------------------------*/
83/* Exported types ------------------------------------------------------------*/
84#if defined(USE_FULL_LL_DRIVER) || defined(__rtems__)
89typedef struct
90{
91 uint32_t SrcAddress;
95 uint32_t DstAddress;
99 uint32_t RequestMode;
103 uint32_t TriggerMode;
107 uint32_t HWTrigger;
111 uint32_t BlockDataLength;
115 uint32_t BlockRepeatCount;
119 uint32_t BlockRepeatDestAddrUpdateMode;
123 uint32_t BlockRepeatSrcAddrUpdateMode;
127 uint32_t BlockRepeatDestAddrUpdateVal;
131 uint32_t BlockRepeatSrcAddrUpdateVal;
135 uint32_t LinkAddress;
139 uint32_t WordEndianess;
143 uint32_t HalfWordEndianess;
147 uint32_t ByteEndianess;
151 uint32_t Priority;
155 uint32_t BufferableWriteMode;
161 uint32_t PaddingAlignment;
165 uint32_t PackMode;
170 uint32_t BufferTransferLength;
174 uint32_t DestBurst;
178 uint32_t SrctBurst;
182 uint32_t DestIncSize;
186 uint32_t SrcIncSize;
190 uint32_t DestDataSize;
194 uint32_t SrcDataSize;
198 uint32_t DestIncMode;
202 uint32_t SrcIncMode;
207 uint32_t DestBus;
211 uint32_t SrcBus;
215 uint32_t MaskAddress;
220 uint32_t MaskData;
225} LL_MDMA_InitTypeDef;
226
234typedef struct
235{
236 __IO uint32_t CTCR;
237 __IO uint32_t CBNDTR;
238 __IO uint32_t CSAR;
239 __IO uint32_t CDAR;
240 __IO uint32_t CBRUR;
241 __IO uint32_t CLAR;
242 __IO uint32_t CTBR;
243 __IO uint32_t Reserved;
244 __IO uint32_t CMAR;
245 __IO uint32_t CMDR;
247}LL_MDMA_LinkNodeTypeDef;
248
252#endif /*USE_FULL_LL_DRIVER*/
253/* Exported constants --------------------------------------------------------*/
263#define LL_MDMA_CHANNEL_0 0x00000000U
264#define LL_MDMA_CHANNEL_1 0x00000001U
265#define LL_MDMA_CHANNEL_2 0x00000002U
266#define LL_MDMA_CHANNEL_3 0x00000003U
267#define LL_MDMA_CHANNEL_4 0x00000004U
268#define LL_MDMA_CHANNEL_5 0x00000005U
269#define LL_MDMA_CHANNEL_6 0x00000006U
270#define LL_MDMA_CHANNEL_7 0x00000007U
271#define LL_MDMA_CHANNEL_8 0x00000008U
272#define LL_MDMA_CHANNEL_9 0x00000009U
273#define LL_MDMA_CHANNEL_10 0x0000000AU
274#define LL_MDMA_CHANNEL_11 0x0000000BU
275#define LL_MDMA_CHANNEL_12 0x0000000CU
276#define LL_MDMA_CHANNEL_13 0x0000000DU
277#define LL_MDMA_CHANNEL_14 0x0000000EU
278#define LL_MDMA_CHANNEL_15 0x0000000FU
279#define LL_MDMA_CHANNEL_ALL 0xFFFF0000U
288#define LL_MDMA_WORD_ENDIANNESS_PRESERVE 0x00000000U
289#define LL_MDMA_WORD_ENDIANNESS_EXCHANGE MDMA_CCR_WEX
299#define LL_MDMA_HALFWORD_ENDIANNESS_PRESERVE 0x00000000U
300#define LL_MDMA_HALFWORD_ENDIANNESS_EXCHANGE MDMA_CCR_HEX
310#define LL_MDMA_BYTE_ENDIANNESS_PRESERVE 0x00000000U
311#define LL_MDMA_BYTE_ENDIANNESS_EXCHANGE MDMA_CCR_BEX
321#define LL_MDMA_PRIORITY_LOW 0x00000000U
322#define LL_MDMA_PRIORITY_MEDIUM MDMA_CCR_PL_0
323#define LL_MDMA_PRIORITY_HIGH MDMA_CCR_PL_1
324#define LL_MDMA_PRIORITY_VERYHIGH MDMA_CCR_PL
333#define LL_MDMA_BUFF_WRITE_DISABLE 0x00000000U
334#define LL_MDMA_BUFF_WRITE_ENABLE MDMA_CTCR_BWM
343#define LL_MDMA_REQUEST_MODE_HW 0x00000000U
344#define LL_MDMA_REQUEST_MODE_SW MDMA_CTCR_SWRM
353#define LL_MDMA_BUFFER_TRANSFER 0x00000000U
354#define LL_MDMA_BLOCK_TRANSFER MDMA_CTCR_TRGM_0
355#define LL_MDMA_REPEAT_BLOCK_TRANSFER MDMA_CTCR_TRGM_1
356#define LL_MDMA_FULL_TRANSFER MDMA_CTCR_TRGM
365#define LL_MDMA_DATAALIGN_RIGHT 0x00000000U
366#define LL_MDMA_DATAALIGN_RIGHT_SIGNED MDMA_CTCR_PAM_0
368#define LL_MDMA_DATAALIGN_LEFT MDMA_CTCR_PAM_1
377#define LL_MDMA_PACK_DISABLE 0x00000000U
378#define LL_MDMA_PACK_ENABLE MDMA_CTCR_PKE
387#define LL_MDMA_DEST_BURST_SINGLE 0x00000000U
388#define LL_MDMA_DEST_BURST_2BEATS MDMA_CTCR_DBURST_0
389#define LL_MDMA_DEST_BURST_4BEATS MDMA_CTCR_DBURST_1
390#define LL_MDMA_DEST_BURST_8BEATS (MDMA_CTCR_DBURST_0 | MDMA_CTCR_DBURST_1)
391#define LL_MDMA_DEST_BURST_16BEATS MDMA_CTCR_DBURST_2
392#define LL_MDMA_DEST_BURST_32BEATS (MDMA_CTCR_DBURST_0 | MDMA_CTCR_DBURST_2)
393#define LL_MDMA_DEST_BURST_64BEATS (MDMA_CTCR_DBURST_1 | MDMA_CTCR_DBURST_2)
394#define LL_MDMA_DEST_BURST_128BEATS (MDMA_CTCR_DBURST)
403#define LL_MDMA_SRC_BURST_SINGLE 0x00000000U
404#define LL_MDMA_SRC_BURST_2BEATS MDMA_CTCR_SBURST_0
405#define LL_MDMA_SRC_BURST_4BEATS MDMA_CTCR_SBURST_1
406#define LL_MDMA_SRC_BURST_8BEATS (MDMA_CTCR_SBURST_0 | MDMA_CTCR_SBURST_1)
407#define LL_MDMA_SRC_BURST_16BEATS MDMA_CTCR_SBURST_2
408#define LL_MDMA_SRC_BURST_32BEATS (MDMA_CTCR_SBURST_0 | MDMA_CTCR_SBURST_2)
409#define LL_MDMA_SRC_BURST_64BEATS (MDMA_CTCR_SBURST_1 | MDMA_CTCR_SBURST_2)
410#define LL_MDMA_SRC_BURST_128BEATS MDMA_CTCR_SBURST
419#define LL_MDMA_DEST_INC_OFFSET_BYTE 0x00000000U
420#define LL_MDMA_DEST_INC_OFFSET_HALFWORD MDMA_CTCR_DINCOS_0
421#define LL_MDMA_DEST_INC_OFFSET_WORD MDMA_CTCR_DINCOS_1
422#define LL_MDMA_DEST_INC_OFFSET_DOUBLEWORD MDMA_CTCR_DINCOS
431#define LL_MDMA_SRC_INC_OFFSET_BYTE 0x00000000U
432#define LL_MDMA_SRC_INC_OFFSET_HALFWORD MDMA_CTCR_SINCOS_0
433#define LL_MDMA_SRC_INC_OFFSET_WORD MDMA_CTCR_SINCOS_1
434#define LL_MDMA_SRC_INC_OFFSET_DOUBLEWORD MDMA_CTCR_SINCOS
443#define LL_MDMA_DEST_DATA_SIZE_BYTE 0x00000000U
444#define LL_MDMA_DEST_DATA_SIZE_HALFWORD MDMA_CTCR_DSIZE_0
445#define LL_MDMA_DEST_DATA_SIZE_WORD MDMA_CTCR_DSIZE_1
446#define LL_MDMA_DEST_DATA_SIZE_DOUBLEWORD MDMA_CTCR_DSIZE
455#define LL_MDMA_SRC_DATA_SIZE_BYTE 0x00000000U
456#define LL_MDMA_SRC_DATA_SIZE_HALFWORD MDMA_CTCR_SSIZE_0
457#define LL_MDMA_SRC_DATA_SIZE_WORD MDMA_CTCR_SSIZE_1
458#define LL_MDMA_SRC_DATA_SIZE_DOUBLEWORD MDMA_CTCR_SSIZE
467#define LL_MDMA_DEST_FIXED 0x00000000U
468#define LL_MDMA_DEST_INCREMENT MDMA_CTCR_DINC_1
469#define LL_MDMA_DEST_DECREMENT MDMA_CTCR_DINC
478#define LL_MDMA_SRC_FIXED 0x00000000U
479#define LL_MDMA_SRC_INCREMENT MDMA_CTCR_SINC_1
480#define LL_MDMA_SRC_DECREMENT MDMA_CTCR_SINC
489#define LL_MDMA_BLK_RPT_DEST_ADDR_INCREMENT 0x00000000U
490#define LL_MDMA_BLK_RPT_DEST_ADDR_DECREMENT MDMA_CBNDTR_BRDUM
499#define LL_MDMA_BLK_RPT_SRC_ADDR_INCREMENT 0x00000000U
500#define LL_MDMA_BLK_RPT_SRC_ADDR_DECREMENT MDMA_CBNDTR_BRSUM
509#define LL_MDMA_DEST_BUS_SYSTEM_AXI 0x00000000U
510#define LL_MDMA_DEST_BUS_AHB_TCM MDMA_CTBR_DBUS
519#define LL_MDMA_SRC_BUS_SYSTEM_AXI 0x00000000U
520#define LL_MDMA_SRC_BUS_AHB_TCM MDMA_CTBR_SBUS
529#define LL_MDMA_REQ_DMA1_STREAM0_TC 0x00000000U
530#define LL_MDMA_REQ_DMA1_STREAM1_TC 0x00000001U
531#define LL_MDMA_REQ_DMA1_STREAM2_TC 0x00000002U
532#define LL_MDMA_REQ_DMA1_STREAM3_TC 0x00000003U
533#define LL_MDMA_REQ_DMA1_STREAM4_TC 0x00000004U
534#define LL_MDMA_REQ_DMA1_STREAM5_TC 0x00000005U
535#define LL_MDMA_REQ_DMA1_STREAM6_TC 0x00000006U
536#define LL_MDMA_REQ_DMA1_STREAM7_TC 0x00000007U
537#define LL_MDMA_REQ_DMA2_STREAM0_TC 0x00000008U
538#define LL_MDMA_REQ_DMA2_STREAM1_TC 0x00000009U
539#define LL_MDMA_REQ_DMA2_STREAM2_TC 0x0000000AU
540#define LL_MDMA_REQ_DMA2_STREAM3_TC 0x0000000BU
541#define LL_MDMA_REQ_DMA2_STREAM4_TC 0x0000000CU
542#define LL_MDMA_REQ_DMA2_STREAM5_TC 0x0000000DU
543#define LL_MDMA_REQ_DMA2_STREAM6_TC 0x0000000EU
544#define LL_MDMA_REQ_DMA2_STREAM7_TC 0x0000000FU
545#if defined (LTDC)
546#define LL_MDMA_REQ_LTDC_LINE_IT 0x00000010U
547#endif /* LTDC */
548#if defined (JPEG)
549#define LL_MDMA_REQ_JPEG_INFIFO_TH 0x00000011U
550#define LL_MDMA_REQ_JPEG_INFIFO_NF 0x00000012U
551#define LL_MDMA_REQ_JPEG_OUTFIFO_TH 0x00000013U
552#define LL_MDMA_REQ_JPEG_OUTFIFO_NE 0x00000014U
553#define LL_MDMA_REQ_JPEG_END_CONVERSION 0x00000015U
554#endif /* JPEG */
555#if defined (QUADSPI)
556#define LL_MDMA_REQ_QUADSPI_FIFO_TH 0x00000016U
557#define LL_MDMA_REQ_QUADSPI_TC 0x00000017U
558#endif /* QUADSPI */
559#if defined (OCTOSPI1)
560#define LL_MDMA_REQ_OCTOSPI1_FIFO_TH 0x00000016U
561#define LL_MDMA_REQ_OCTOSPI1_TC 0x00000017U
562#endif /* OCTOSPI1 */
563#define LL_MDMA_REQ_DMA2D_CLUT_TC 0x00000018U
564#define LL_MDMA_REQ_DMA2D_TC 0x00000019U
565#define LL_MDMA_REQ_DMA2D_TW 0x0000001AU
566#if defined (DSI)
567#define LL_MDMA_REQ_DSI_TEARING_EFFECT 0x0000001BU
568#define LL_MDMA_REQ_DSI_END_REFRESH 0x0000001CU
569#endif /* DSI */
570#define LL_MDMA_REQ_SDMMC1_END_DATA 0x0000001DU
571#define LL_MDMA_REQ_SDMMC1_DMA_ENDBUFFER 0x0000001EU
572#define LL_MDMA_REQ_SDMMC1_COMMAND_END 0x0000001FU
573#if defined (OCTOSPI2)
574#define LL_MDMA_REQ_OCTOSPI2_FIFO_TH 0x00000020U
575#define LL_MDMA_REQ_OCTOSPI2_TC 0x00000021U
576#endif /* OCTOSPI2 */
585#define LL_MDMA_READ_ERROR 0x00000000U
586#define LL_MDMA_WRITE_ERROR MDMA_CESR_TED
595/* Exported macro ------------------------------------------------------------*/
612#define LL_MDMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
613
620#define LL_MDMA_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
634#define LL_MDMA_GET_INSTANCE(__CHANNEL_INSTANCE__) (MDMA)
635
641#define LL_MDMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
642(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)MDMA_Channel0 )) ? LL_MDMA_CHANNEL_0 : \
643 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)MDMA_Channel1 )) ? LL_MDMA_CHANNEL_1 : \
644 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)MDMA_Channel2 )) ? LL_MDMA_CHANNEL_2 : \
645 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)MDMA_Channel3 )) ? LL_MDMA_CHANNEL_3 : \
646 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)MDMA_Channel4 )) ? LL_MDMA_CHANNEL_4 : \
647 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)MDMA_Channel5 )) ? LL_MDMA_CHANNEL_5 : \
648 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)MDMA_Channel6 )) ? LL_MDMA_CHANNEL_6 : \
649 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)MDMA_Channel7 )) ? LL_MDMA_CHANNEL_7 : \
650 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)MDMA_Channel8 )) ? LL_MDMA_CHANNEL_8 : \
651 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)MDMA_Channel9 )) ? LL_MDMA_CHANNEL_9 : \
652 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)MDMA_Channel10)) ? LL_MDMA_CHANNEL_10 : \
653 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)MDMA_Channel11)) ? LL_MDMA_CHANNEL_11 : \
654 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)MDMA_Channel12)) ? LL_MDMA_CHANNEL_12 : \
655 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)MDMA_Channel13)) ? LL_MDMA_CHANNEL_13 : \
656 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)MDMA_Channel14)) ? LL_MDMA_CHANNEL_14 : \
657 LL_MDMA_CHANNEL_15)
658
665#define LL_MDMA_GET_CHANNEL_INSTANCE(__MDMA_INSTANCE__, __CHANNEL__) \
666(((uint32_t)(__CHANNEL__) == ((uint32_t)LL_MDMA_CHANNEL_0 )) ? MDMA_Channel0 : \
667 ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_MDMA_CHANNEL_1 )) ? MDMA_Channel1 : \
668 ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_MDMA_CHANNEL_2 )) ? MDMA_Channel2 : \
669 ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_MDMA_CHANNEL_3 )) ? MDMA_Channel3 : \
670 ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_MDMA_CHANNEL_4 )) ? MDMA_Channel4 : \
671 ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_MDMA_CHANNEL_5 )) ? MDMA_Channel5 : \
672 ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_MDMA_CHANNEL_6 )) ? MDMA_Channel6 : \
673 ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_MDMA_CHANNEL_7 )) ? MDMA_Channel7 : \
674 ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_MDMA_CHANNEL_8 )) ? MDMA_Channel8 : \
675 ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_MDMA_CHANNEL_9 )) ? MDMA_Channel9 : \
676 ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_MDMA_CHANNEL_10)) ? MDMA_Channel10 : \
677 ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_MDMA_CHANNEL_11)) ? MDMA_Channel11 : \
678 ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_MDMA_CHANNEL_12)) ? MDMA_Channel12 : \
679 ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_MDMA_CHANNEL_13)) ? MDMA_Channel13 : \
680 ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_MDMA_CHANNEL_14)) ? MDMA_Channel14 : \
681 MDMA_Channel15)
682
692/* Exported functions --------------------------------------------------------*/
725__STATIC_INLINE void LL_MDMA_EnableChannel(MDMA_TypeDef *MDMAx, uint32_t Channel)
726{
727 uint32_t mdma_base_addr = (uint32_t)MDMAx;
728
729 SET_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR, MDMA_CCR_EN);
730}
731
755__STATIC_INLINE void LL_MDMA_DisableChannel(MDMA_TypeDef *MDMAx, uint32_t Channel)
756{
757 uint32_t mdma_base_addr = (uint32_t)MDMAx;
758
759 CLEAR_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR, MDMA_CCR_EN);
760}
761
785__STATIC_INLINE uint32_t LL_MDMA_IsEnabledChannel(MDMA_TypeDef *MDMAx, uint32_t Channel)
786{
787 uint32_t mdma_base_addr = (uint32_t)MDMAx;
788
789 return ((READ_BIT(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR, MDMA_CCR_EN) == (MDMA_CCR_EN)) ? 1UL : 0UL);
790}
791
815__STATIC_INLINE void LL_MDMA_GenerateSWRequest(MDMA_TypeDef *MDMAx, uint32_t Channel)
816{
817 uint32_t mdma_base_addr = (uint32_t)MDMAx;
818
819 SET_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR, MDMA_CCR_SWRQ);
820}
821
851__STATIC_INLINE void LL_MDMA_ConfigXferEndianness(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Configuration)
852{
853 uint32_t mdma_base_addr = (uint32_t)MDMAx;
854
855 MODIFY_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR,
856 MDMA_CCR_WEX | MDMA_CCR_HEX | MDMA_CCR_BEX, Configuration);
857}
858
885__STATIC_INLINE void LL_MDMA_SetWordEndianness(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Endianness)
886{
887 uint32_t mdma_base_addr = (uint32_t)MDMAx;
888
889 MODIFY_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR, MDMA_CCR_WEX, Endianness);
890}
891
918__STATIC_INLINE uint32_t LL_MDMA_GetWordEndianness(MDMA_TypeDef *MDMAx, uint32_t Channel)
919{
920 uint32_t mdma_base_addr = (uint32_t)MDMAx;
921
922 return (READ_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR, MDMA_CCR_WEX));
923}
924
951__STATIC_INLINE void LL_MDMA_SetHalfWordEndianness(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Endianness)
952{
953 uint32_t mdma_base_addr = (uint32_t)MDMAx;
954
955 MODIFY_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR, MDMA_CCR_HEX, Endianness);
956}
957
984__STATIC_INLINE uint32_t LL_MDMA_GetHalfWordEndianness(MDMA_TypeDef *MDMAx, uint32_t Channel)
985{
986 uint32_t mdma_base_addr = (uint32_t)MDMAx;
987
988 return (READ_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR, MDMA_CCR_HEX));
989}
990
1017__STATIC_INLINE void LL_MDMA_SetByteEndianness(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Endianness)
1018{
1019 uint32_t mdma_base_addr = (uint32_t)MDMAx;
1020
1021 MODIFY_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR, MDMA_CCR_BEX, Endianness);
1022}
1023
1050__STATIC_INLINE uint32_t LL_MDMA_GetByteEndianness(MDMA_TypeDef *MDMAx, uint32_t Channel)
1051{
1052 uint32_t mdma_base_addr = (uint32_t)MDMAx;
1053
1054 return (READ_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR, MDMA_CCR_BEX));
1055}
1056
1085__STATIC_INLINE void LL_MDMA_SetChannelPriorityLevel(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Priority)
1086{
1087 uint32_t mdma_base_addr = (uint32_t)MDMAx;
1088
1089 MODIFY_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR, MDMA_CCR_PL, Priority);
1090}
1091
1120__STATIC_INLINE uint32_t LL_MDMA_GetChannelPriorityLevel(MDMA_TypeDef *MDMAx, uint32_t Channel)
1121{
1122 uint32_t mdma_base_addr = (uint32_t)MDMAx;
1123
1124 return (READ_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR, MDMA_CCR_PL));
1125}
1126
1180__STATIC_INLINE void LL_MDMA_ConfigTransfer(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Configuration, uint32_t BufferXferLength)
1181{
1182 uint32_t mdma_base_addr = (uint32_t)MDMAx;
1183
1184 WRITE_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR,
1185 Configuration | ((BufferXferLength << MDMA_CTCR_TLEN_Pos) & MDMA_CTCR_TLEN_Msk));
1186}
1187
1211__STATIC_INLINE void LL_MDMA_EnableBufferableWrMode(MDMA_TypeDef *MDMAx, uint32_t Channel)
1212{
1213 uint32_t mdma_base_addr = (uint32_t)MDMAx;
1214
1215 SET_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR, MDMA_CTCR_BWM);
1216}
1217
1241__STATIC_INLINE void LL_MDMA_DisableBufferableWrMode(MDMA_TypeDef *MDMAx, uint32_t Channel)
1242{
1243 uint32_t mdma_base_addr = (uint32_t)MDMAx;
1244
1245 CLEAR_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR, MDMA_CTCR_BWM);
1246}
1247
1271__STATIC_INLINE uint32_t LL_MDMA_IsEnabledBufferableWrMode(MDMA_TypeDef *MDMAx, uint32_t Channel)
1272{
1273 uint32_t mdma_base_addr = (uint32_t)MDMAx;
1274
1275 return ((READ_BIT(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR, MDMA_CTCR_BWM) == (MDMA_CTCR_BWM)) ? 1UL : 0UL);
1276}
1277
1304__STATIC_INLINE void LL_MDMA_SetRequestMode(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t RequestMode)
1305{
1306 uint32_t mdma_base_addr = (uint32_t)MDMAx;
1307
1308 MODIFY_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR, MDMA_CTCR_SWRM, RequestMode);
1309}
1310
1337__STATIC_INLINE uint32_t LL_MDMA_GetRequestMode(MDMA_TypeDef *MDMAx, uint32_t Channel)
1338{
1339 uint32_t mdma_base_addr = (uint32_t)MDMAx;
1340
1341 return (READ_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR, MDMA_CTCR_SWRM));
1342}
1343
1372__STATIC_INLINE void LL_MDMA_SetTriggerMode(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t TriggerMode)
1373{
1374 uint32_t mdma_base_addr = (uint32_t)MDMAx;
1375
1376 MODIFY_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR, MDMA_CTCR_TRGM, TriggerMode);
1377}
1378
1407__STATIC_INLINE uint32_t LL_MDMA_GetTriggerMode(MDMA_TypeDef *MDMAx, uint32_t Channel)
1408{
1409 uint32_t mdma_base_addr = (uint32_t)MDMAx;
1410
1411 return (READ_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR, MDMA_CTCR_TRGM));
1412}
1413
1441__STATIC_INLINE void LL_MDMA_SetPaddingAlignment(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t PaddingAlignment)
1442{
1443 uint32_t mdma_base_addr = (uint32_t)MDMAx;
1444
1445 MODIFY_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR, MDMA_CTCR_PAM, PaddingAlignment);
1446}
1447
1475__STATIC_INLINE uint32_t LL_MDMA_GetPaddingAlignment(MDMA_TypeDef *MDMAx, uint32_t Channel)
1476{
1477 uint32_t mdma_base_addr = (uint32_t)MDMAx;
1478
1479 return (READ_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR, MDMA_CTCR_PAM));
1480}
1481
1482
1506__STATIC_INLINE void LL_MDMA_EnablePacking(MDMA_TypeDef *MDMAx, uint32_t Channel)
1507{
1508 uint32_t mdma_base_addr = (uint32_t)MDMAx;
1509
1510 SET_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR, MDMA_CTCR_PKE);
1511}
1512
1536__STATIC_INLINE void LL_MDMA_DisablePacking(MDMA_TypeDef *MDMAx, uint32_t Channel)
1537{
1538 uint32_t mdma_base_addr = (uint32_t)MDMAx;
1539
1540 CLEAR_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR, MDMA_CTCR_PKE);
1541}
1542
1566__STATIC_INLINE uint32_t LL_MDMA_IsEnabledPacking(MDMA_TypeDef *MDMAx, uint32_t Channel)
1567{
1568 uint32_t mdma_base_addr = (uint32_t)MDMAx;
1569
1570 return ((READ_BIT(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR, MDMA_CTCR_PKE) == (MDMA_CTCR_PKE)) ? 1UL : 0UL);
1571}
1572
1597__STATIC_INLINE void LL_MDMA_SetBufferTransferLength(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Length)
1598{
1599 uint32_t mdma_base_addr = (uint32_t)MDMAx;
1600
1601 MODIFY_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR, MDMA_CTCR_TLEN,
1602 (Length << MDMA_CTCR_TLEN_Pos) & MDMA_CTCR_TLEN_Msk);
1603}
1604
1629__STATIC_INLINE uint32_t LL_MDMA_GetBufferTransferLength(MDMA_TypeDef *MDMAx, uint32_t Channel)
1630{
1631 uint32_t mdma_base_addr = (uint32_t)MDMAx;
1632
1633 return(READ_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR, MDMA_CTCR_TLEN) >> MDMA_CTCR_TLEN_Pos);
1634}
1635
1668__STATIC_INLINE void LL_MDMA_SetDestinationBurstSize(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Dburst)
1669{
1670 uint32_t mdma_base_addr = (uint32_t)MDMAx;
1671
1672 MODIFY_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR, MDMA_CTCR_DBURST, Dburst);
1673}
1674
1707__STATIC_INLINE uint32_t LL_MDMA_GetDestinationBurstSize(MDMA_TypeDef *MDMAx, uint32_t Channel)
1708{
1709 uint32_t mdma_base_addr = (uint32_t)MDMAx;
1710
1711 return(READ_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR, MDMA_CTCR_DBURST));
1712}
1713
1746__STATIC_INLINE void LL_MDMA_SetSourceBurstSize(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Sburst)
1747{
1748 uint32_t mdma_base_addr = (uint32_t)MDMAx;
1749
1750 MODIFY_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR, MDMA_CTCR_SBURST, Sburst);
1751}
1752
1785__STATIC_INLINE uint32_t LL_MDMA_GetSourceBurstSize(MDMA_TypeDef *MDMAx, uint32_t Channel)
1786{
1787 uint32_t mdma_base_addr = (uint32_t)MDMAx;
1788
1789 return(READ_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR, MDMA_CTCR_SBURST));
1790}
1791
1820__STATIC_INLINE void LL_MDMA_SetDestinationIncSize(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t IncSize)
1821{
1822 uint32_t mdma_base_addr = (uint32_t)MDMAx;
1823
1824 MODIFY_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR, MDMA_CTCR_DINCOS, IncSize);
1825}
1826
1855__STATIC_INLINE uint32_t LL_MDMA_GetDestinationIncSize(MDMA_TypeDef *MDMAx, uint32_t Channel)
1856{
1857 uint32_t mdma_base_addr = (uint32_t)MDMAx;
1858
1859 return (READ_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR, MDMA_CTCR_DINCOS));
1860}
1861
1890__STATIC_INLINE void LL_MDMA_SetSourceIncSize(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t IncSize)
1891{
1892 uint32_t mdma_base_addr = (uint32_t)MDMAx;
1893
1894 MODIFY_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR, MDMA_CTCR_SINCOS, IncSize);
1895}
1896
1925__STATIC_INLINE uint32_t LL_MDMA_GetSourceIncSize(MDMA_TypeDef *MDMAx, uint32_t Channel)
1926{
1927 uint32_t mdma_base_addr = (uint32_t)MDMAx;
1928
1929 return (READ_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR, MDMA_CTCR_SINCOS));
1930}
1931
1960__STATIC_INLINE void LL_MDMA_SetDestinationDataSize(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t DestDataSize)
1961{
1962 uint32_t mdma_base_addr = (uint32_t)MDMAx;
1963
1964 MODIFY_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR, MDMA_CTCR_DSIZE, DestDataSize);
1965}
1966
1995__STATIC_INLINE uint32_t LL_MDMA_GetDestinationDataSize(MDMA_TypeDef *MDMAx, uint32_t Channel)
1996{
1997 uint32_t mdma_base_addr = (uint32_t)MDMAx;
1998
1999 return (READ_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR, MDMA_CTCR_DSIZE));
2000}
2001
2030__STATIC_INLINE void LL_MDMA_SetSourceDataSize(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t SrcDataSize)
2031{
2032 uint32_t mdma_base_addr = (uint32_t)MDMAx;
2033
2034 MODIFY_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR, MDMA_CTCR_SSIZE, SrcDataSize);
2035}
2036
2065__STATIC_INLINE uint32_t LL_MDMA_GetSourceDataSize(MDMA_TypeDef *MDMAx, uint32_t Channel)
2066{
2067 uint32_t mdma_base_addr = (uint32_t)MDMAx;
2068
2069 return (READ_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR, MDMA_CTCR_SSIZE));
2070}
2071
2099__STATIC_INLINE void LL_MDMA_SetDestinationIncMode(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t DestIncMode)
2100{
2101 uint32_t mdma_base_addr = (uint32_t)MDMAx;
2102
2103 MODIFY_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR, MDMA_CTCR_DINC, DestIncMode);
2104}
2105
2133__STATIC_INLINE uint32_t LL_MDMA_GetDestinationIncMode(MDMA_TypeDef *MDMAx, uint32_t Channel)
2134{
2135 uint32_t mdma_base_addr = (uint32_t)MDMAx;
2136
2137 return (READ_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR, MDMA_CTCR_DINC));
2138}
2139
2167__STATIC_INLINE void LL_MDMA_SetSourceIncMode(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t SrcIncMode)
2168{
2169 uint32_t mdma_base_addr = (uint32_t)MDMAx;
2170
2171 MODIFY_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR, MDMA_CTCR_SINC, SrcIncMode);
2172}
2173
2201__STATIC_INLINE uint32_t LL_MDMA_GetSourceIncMode(MDMA_TypeDef *MDMAx, uint32_t Channel)
2202{
2203 uint32_t mdma_base_addr = (uint32_t)MDMAx;
2204
2205 return (READ_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR, MDMA_CTCR_SINC));
2206}
2207
2234__STATIC_INLINE void LL_MDMA_ConfigBlkCounters(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t BlockRepeatCount, uint32_t BlkDataLength)
2235{
2236 uint32_t mdma_base_addr = (uint32_t)MDMAx;
2237
2238 MODIFY_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CBNDTR,
2239 MDMA_CBNDTR_BRC | MDMA_CBNDTR_BNDT,
2240 ((BlockRepeatCount << MDMA_CBNDTR_BRC_Pos) & MDMA_CBNDTR_BRC_Msk) | (BlkDataLength & MDMA_CBNDTR_BNDT_Msk));
2241}
2242
2267__STATIC_INLINE void LL_MDMA_SetBlkDataLength(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t BlkDataLength)
2268{
2269 uint32_t mdma_base_addr = (uint32_t)MDMAx;
2270
2271 MODIFY_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CBNDTR, MDMA_CBNDTR_BNDT, (BlkDataLength & MDMA_CBNDTR_BNDT_Msk));
2272}
2273
2298__STATIC_INLINE uint32_t LL_MDMA_GetBlkDataLength(MDMA_TypeDef *MDMAx, uint32_t Channel)
2299{
2300 uint32_t mdma_base_addr = (uint32_t)MDMAx;
2301
2302 return (READ_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CBNDTR, MDMA_CBNDTR_BNDT));
2303}
2304
2329__STATIC_INLINE void LL_MDMA_SetBlkRepeatCount(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t BlockRepeatCount)
2330{
2331 uint32_t mdma_base_addr = (uint32_t)MDMAx;
2332
2333 MODIFY_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CBNDTR, MDMA_CBNDTR_BRC,
2334 (BlockRepeatCount << MDMA_CBNDTR_BRC_Pos) & MDMA_CBNDTR_BRC_Msk);
2335}
2336
2361__STATIC_INLINE uint32_t LL_MDMA_GetBlkRepeatCount(MDMA_TypeDef *MDMAx, uint32_t Channel)
2362{
2363 uint32_t mdma_base_addr = (uint32_t)MDMAx;
2364
2365 return (READ_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CBNDTR, MDMA_CBNDTR_BRC) >> MDMA_CBNDTR_BRC_Pos);
2366}
2367
2395__STATIC_INLINE void LL_MDMA_ConfigBlkRepeatAddrUpdate(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Configuration)
2396{
2397 uint32_t mdma_base_addr = (uint32_t)MDMAx;
2398
2399 MODIFY_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CBNDTR,
2400 MDMA_CBNDTR_BRDUM | MDMA_CBNDTR_BRSUM,
2401 Configuration);
2402}
2403
2430__STATIC_INLINE void LL_MDMA_SetBlkRepeatDestAddrUpdate(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t DestAdrUpdateMode)
2431{
2432 uint32_t mdma_base_addr = (uint32_t)MDMAx;
2433
2434 MODIFY_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CBNDTR, MDMA_CBNDTR_BRDUM, DestAdrUpdateMode);
2435}
2436
2463__STATIC_INLINE uint32_t LL_MDMA_GetBlkRepeatDestAddrUpdate(MDMA_TypeDef *MDMAx, uint32_t Channel)
2464{
2465 uint32_t mdma_base_addr = (uint32_t)MDMAx;
2466
2467 return (READ_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CBNDTR, MDMA_CBNDTR_BRDUM));
2468}
2469
2496__STATIC_INLINE void LL_MDMA_SetBlkRepeatSrcAddrUpdate(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t SrcAdrUpdateMode)
2497{
2498 uint32_t mdma_base_addr = (uint32_t)MDMAx;
2499
2500 MODIFY_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CBNDTR, MDMA_CBNDTR_BRSUM, SrcAdrUpdateMode);
2501}
2502
2529__STATIC_INLINE uint32_t LL_MDMA_GetBlkRepeatSrcAddrUpdate(MDMA_TypeDef *MDMAx, uint32_t Channel)
2530{
2531 uint32_t mdma_base_addr = (uint32_t)MDMAx;
2532
2533 return (READ_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CBNDTR, MDMA_CBNDTR_BRSUM));
2534}
2535
2563__STATIC_INLINE void LL_MDMA_ConfigAddresses(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t SrcAddress, uint32_t DstAddress)
2564{
2565 uint32_t mdma_base_addr = (uint32_t)MDMAx;
2566
2567 WRITE_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CSAR, SrcAddress);
2568 WRITE_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CDAR, DstAddress);
2569}
2594__STATIC_INLINE void LL_MDMA_SetSourceAddress(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t SrcAddress)
2595{
2596 uint32_t mdma_base_addr = (uint32_t)MDMAx;
2597
2598 WRITE_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CSAR, SrcAddress);
2599}
2600
2625__STATIC_INLINE uint32_t LL_MDMA_GetSourceAddress(MDMA_TypeDef *MDMAx, uint32_t Channel)
2626{
2627 uint32_t mdma_base_addr = (uint32_t)MDMAx;
2628
2629 return (READ_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CSAR));
2630}
2631
2656__STATIC_INLINE void LL_MDMA_SetDestinationAddress(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t DestAddress)
2657{
2658 uint32_t mdma_base_addr = (uint32_t)MDMAx;
2659
2660 WRITE_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CDAR, DestAddress);
2661}
2662
2687__STATIC_INLINE uint32_t LL_MDMA_GetDestinationAddress(MDMA_TypeDef *MDMAx, uint32_t Channel)
2688{
2689 uint32_t mdma_base_addr = (uint32_t)MDMAx;
2690
2691 return (READ_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CDAR));
2692}
2693
2721__STATIC_INLINE void LL_MDMA_ConfigBlkRptAddrUpdateValue(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t SrctAdrUpdateValue, uint32_t DestAdrUpdateValue)
2722{
2723 uint32_t mdma_base_addr = (uint32_t)MDMAx;
2724
2725 WRITE_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CBRUR,
2726 (SrctAdrUpdateValue & MDMA_CBRUR_SUV_Msk) | ((DestAdrUpdateValue << MDMA_CBRUR_DUV_Pos) & MDMA_CBRUR_DUV_Msk));
2727}
2728
2753__STATIC_INLINE void LL_MDMA_SetBlkRptDestAddrUpdateValue(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t DestAdrUpdateValue)
2754{
2755 uint32_t mdma_base_addr = (uint32_t)MDMAx;
2756
2757 MODIFY_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CBRUR, MDMA_CBRUR_DUV,
2758 ((DestAdrUpdateValue << MDMA_CBRUR_DUV_Pos) & MDMA_CBRUR_DUV_Msk));
2759}
2760
2785__STATIC_INLINE uint32_t LL_MDMA_GetBlkRptDestAddrUpdateValue(MDMA_TypeDef *MDMAx, uint32_t Channel)
2786{
2787 uint32_t mdma_base_addr = (uint32_t)MDMAx;
2788
2789 return (READ_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CBRUR, MDMA_CBRUR_DUV) >> MDMA_CBRUR_DUV_Pos);
2790}
2791
2816__STATIC_INLINE void LL_MDMA_SetBlkRptSrcAddrUpdateValue(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t SrcAdrUpdateValue)
2817{
2818 uint32_t mdma_base_addr = (uint32_t)MDMAx;
2819
2820 MODIFY_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CBRUR, MDMA_CBRUR_SUV, SrcAdrUpdateValue);
2821}
2822
2847__STATIC_INLINE uint32_t LL_MDMA_GetBlkRptSrcAddrUpdateValue(MDMA_TypeDef *MDMAx, uint32_t Channel)
2848{
2849 uint32_t mdma_base_addr = (uint32_t)MDMAx;
2850
2851 return (READ_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CBRUR, MDMA_CBRUR_SUV));
2852}
2853
2878__STATIC_INLINE void LL_MDMA_SetLinkAddress(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t LinkAddress)
2879{
2880 uint32_t mdma_base_addr = (uint32_t)MDMAx;
2881
2882 WRITE_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CLAR, LinkAddress);
2883}
2884
2909__STATIC_INLINE uint32_t LL_MDMA_GetLinkAddress(MDMA_TypeDef *MDMAx, uint32_t Channel)
2910{
2911 uint32_t mdma_base_addr = (uint32_t)MDMAx;
2912
2913 return (READ_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CLAR));
2914}
2915
2943__STATIC_INLINE void LL_MDMA_ConfigBusSelection(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Configuration)
2944{
2945 uint32_t mdma_base_addr = (uint32_t)MDMAx;
2946
2947 MODIFY_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTBR,
2948 MDMA_CTBR_DBUS | MDMA_CTBR_SBUS,
2949 Configuration);
2950}
2951
2978__STATIC_INLINE void LL_MDMA_SetDestBusSelection(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t DestBus)
2979{
2980 uint32_t mdma_base_addr = (uint32_t)MDMAx;
2981
2982 MODIFY_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTBR, MDMA_CTBR_DBUS, DestBus);
2983}
2984
3011__STATIC_INLINE uint32_t LL_MDMA_GetDestBusSelection(MDMA_TypeDef *MDMAx, uint32_t Channel)
3012{
3013 uint32_t mdma_base_addr = (uint32_t)MDMAx;
3014
3015 return (READ_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTBR, MDMA_CTBR_DBUS));
3016}
3017
3044__STATIC_INLINE void LL_MDMA_SetSrcBusSelection(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t SrcBus)
3045{
3046 uint32_t mdma_base_addr = (uint32_t)MDMAx;
3047
3048 MODIFY_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTBR, MDMA_CTBR_SBUS, SrcBus);
3049}
3050
3077__STATIC_INLINE uint32_t LL_MDMA_GetSrcBusSelection(MDMA_TypeDef *MDMAx, uint32_t Channel)
3078{
3079 uint32_t mdma_base_addr = (uint32_t)MDMAx;
3080
3081 return (READ_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTBR, MDMA_CTBR_SBUS));
3082}
3083
3145__STATIC_INLINE void LL_MDMA_SetHWTrigger(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t HWRequest)
3146{
3147 uint32_t mdma_base_addr = (uint32_t)MDMAx;
3148
3149 MODIFY_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTBR, MDMA_CTBR_TSEL, HWRequest);
3150}
3151
3213__STATIC_INLINE uint32_t LL_MDMA_GetHWTrigger(MDMA_TypeDef *MDMAx, uint32_t Channel)
3214{
3215 uint32_t mdma_base_addr = (uint32_t)MDMAx;
3216
3217 return (READ_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTBR, MDMA_CTBR_TSEL));
3218}
3219
3244__STATIC_INLINE void LL_MDMA_SetMaskAddress(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t MaskAddress)
3245{
3246 uint32_t mdma_base_addr = (uint32_t)MDMAx;
3247
3248 WRITE_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CMAR, MaskAddress);
3249}
3250
3275__STATIC_INLINE uint32_t LL_MDMA_GetMaskAddress(MDMA_TypeDef *MDMAx, uint32_t Channel)
3276{
3277 uint32_t mdma_base_addr = (uint32_t)MDMAx;
3278
3279 return (READ_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CMAR));
3280}
3281
3306__STATIC_INLINE void LL_MDMA_SetMaskData(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t MaskData)
3307{
3308 uint32_t mdma_base_addr = (uint32_t)MDMAx;
3309
3310 WRITE_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CMDR, MaskData);
3311}
3312
3337__STATIC_INLINE uint32_t LL_MDMA_GetMaskData(MDMA_TypeDef *MDMAx, uint32_t Channel)
3338{
3339 uint32_t mdma_base_addr = (uint32_t)MDMAx;
3340
3341 return (READ_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CMDR));
3342}
3343
3370__STATIC_INLINE uint32_t LL_MDMA_GetXferErrorDirection(MDMA_TypeDef *MDMAx, uint32_t Channel)
3371{
3372 uint32_t mdma_base_addr = (uint32_t)MDMAx;
3373
3374 return (READ_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CESR, MDMA_CESR_TED));
3375}
3376
3401__STATIC_INLINE uint32_t LL_MDMA_GetXferErrorLSBAddress(MDMA_TypeDef *MDMAx, uint32_t Channel)
3402{
3403 uint32_t mdma_base_addr = (uint32_t)MDMAx;
3404
3405 return (READ_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CESR, MDMA_CESR_TEA));
3406}
3407
3440__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_GI(MDMA_TypeDef *MDMAx, uint32_t Channel)
3441{
3442 return ((READ_BIT(MDMAx->GISR0 ,(MDMA_GISR0_GIF0 << (Channel & 0x0000000FU)))==(MDMA_GISR0_GIF0 << (Channel & 0x0000000FU))) ? 1UL : 0UL);
3443}
3444
3468__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_TE(MDMA_TypeDef *MDMAx, uint32_t Channel)
3469{
3470 uint32_t mdma_base_addr = (uint32_t)MDMAx;
3471
3472 return ((READ_BIT(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CISR, MDMA_CISR_TEIF) == (MDMA_CISR_TEIF)) ? 1UL : 0UL);
3473}
3474
3498__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_CTC(MDMA_TypeDef *MDMAx, uint32_t Channel)
3499{
3500 uint32_t mdma_base_addr = (uint32_t)MDMAx;
3501
3502 return ((READ_BIT(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CISR, MDMA_CISR_CTCIF) == (MDMA_CISR_CTCIF)) ? 1UL : 0UL);
3503}
3504
3528__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_BRT(MDMA_TypeDef *MDMAx, uint32_t Channel)
3529{
3530 uint32_t mdma_base_addr = (uint32_t)MDMAx;
3531
3532 return ((READ_BIT(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CISR, MDMA_CISR_BRTIF) == (MDMA_CISR_BRTIF)) ? 1UL : 0UL);
3533}
3534
3558__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_BT(MDMA_TypeDef *MDMAx, uint32_t Channel)
3559{
3560 uint32_t mdma_base_addr = (uint32_t)MDMAx;
3561
3562 return ((READ_BIT(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CISR, MDMA_CISR_BTIF) == (MDMA_CISR_BTIF)) ? 1UL : 0UL);
3563}
3564
3588__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_TC(MDMA_TypeDef *MDMAx, uint32_t Channel)
3589{
3590 uint32_t mdma_base_addr = (uint32_t)MDMAx;
3591
3592 return ((READ_BIT(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CISR, MDMA_CISR_TCIF) == (MDMA_CISR_TCIF)) ? 1UL : 0UL);
3593}
3594
3618__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_CRQA(MDMA_TypeDef *MDMAx, uint32_t Channel)
3619{
3620 uint32_t mdma_base_addr = (uint32_t)MDMAx;
3621
3622 return ((READ_BIT(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CISR, MDMA_CISR_CRQA) == (MDMA_CISR_CRQA)) ? 1UL : 0UL);
3623}
3624
3648__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_BSE(MDMA_TypeDef *MDMAx, uint32_t Channel)
3649{
3650 uint32_t mdma_base_addr = (uint32_t)MDMAx;
3651
3652 return ((READ_BIT(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CESR, MDMA_CESR_BSE) == (MDMA_CESR_BSE)) ? 1UL : 0UL);
3653}
3654
3678__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_ASE(MDMA_TypeDef *MDMAx, uint32_t Channel)
3679{
3680 uint32_t mdma_base_addr = (uint32_t)MDMAx;
3681
3682 return ((READ_BIT(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CESR, MDMA_CESR_ASE) == (MDMA_CESR_ASE)) ? 1UL : 0UL);
3683}
3684
3708__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_TEMD(MDMA_TypeDef *MDMAx, uint32_t Channel)
3709{
3710 uint32_t mdma_base_addr = (uint32_t)MDMAx;
3711
3712 return ((READ_BIT(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CESR, MDMA_CESR_TEMD) == (MDMA_CESR_TEMD)) ? 1UL : 0UL);
3713}
3714
3738__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_TELD(MDMA_TypeDef *MDMAx, uint32_t Channel)
3739{
3740 uint32_t mdma_base_addr = (uint32_t)MDMAx;
3741
3742 return ((READ_BIT(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CESR, MDMA_CESR_TELD) == (MDMA_CESR_TELD)) ? 1UL : 0UL);
3743}
3744
3768__STATIC_INLINE void LL_MDMA_ClearFlag_TE(MDMA_TypeDef *MDMAx, uint32_t Channel)
3769{
3770 uint32_t mdma_base_addr = (uint32_t)MDMAx;
3771
3772 WRITE_REG(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CIFCR ,MDMA_CIFCR_CTEIF);
3773}
3774
3798__STATIC_INLINE void LL_MDMA_ClearFlag_CTC(MDMA_TypeDef *MDMAx, uint32_t Channel)
3799{
3800 uint32_t mdma_base_addr = (uint32_t)MDMAx;
3801
3802 WRITE_REG(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CIFCR ,MDMA_CIFCR_CCTCIF);
3803}
3804
3828__STATIC_INLINE void LL_MDMA_ClearFlag_BRT(MDMA_TypeDef *MDMAx, uint32_t Channel)
3829{
3830 uint32_t mdma_base_addr = (uint32_t)MDMAx;
3831
3832 WRITE_REG(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CIFCR ,MDMA_CIFCR_CBRTIF);
3833}
3834
3858__STATIC_INLINE void LL_MDMA_ClearFlag_BT(MDMA_TypeDef *MDMAx, uint32_t Channel)
3859{
3860 uint32_t mdma_base_addr = (uint32_t)MDMAx;
3861
3862 WRITE_REG(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CIFCR ,MDMA_CIFCR_CBTIF);
3863}
3864
3888__STATIC_INLINE void LL_MDMA_ClearFlag_TC(MDMA_TypeDef *MDMAx, uint32_t Channel)
3889{
3890 uint32_t mdma_base_addr = (uint32_t)MDMAx;
3891
3892 WRITE_REG(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CIFCR ,MDMA_CIFCR_CLTCIF);
3893}
3894
3927__STATIC_INLINE void LL_MDMA_EnableIT_TE(MDMA_TypeDef *MDMAx, uint32_t Channel)
3928{
3929 uint32_t mdma_base_addr = (uint32_t)MDMAx;
3930
3931 SET_BIT(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR ,MDMA_CCR_TEIE);
3932}
3933
3957__STATIC_INLINE void LL_MDMA_EnableIT_CTC(MDMA_TypeDef *MDMAx, uint32_t Channel)
3958{
3959 uint32_t mdma_base_addr = (uint32_t)MDMAx;
3960
3961 SET_BIT(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR ,MDMA_CCR_CTCIE);
3962}
3963
3987__STATIC_INLINE void LL_MDMA_EnableIT_BRT(MDMA_TypeDef *MDMAx, uint32_t Channel)
3988{
3989 uint32_t mdma_base_addr = (uint32_t)MDMAx;
3990
3991 SET_BIT(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR ,MDMA_CCR_BRTIE);
3992}
3993
4017__STATIC_INLINE void LL_MDMA_EnableIT_BT(MDMA_TypeDef *MDMAx, uint32_t Channel)
4018{
4019 uint32_t mdma_base_addr = (uint32_t)MDMAx;
4020
4021 SET_BIT(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR ,MDMA_CCR_BTIE);
4022}
4023
4047__STATIC_INLINE void LL_MDMA_EnableIT_TC(MDMA_TypeDef *MDMAx, uint32_t Channel)
4048{
4049 uint32_t mdma_base_addr = (uint32_t)MDMAx;
4050
4051 SET_BIT(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR ,MDMA_CCR_TCIE);
4052}
4053
4077__STATIC_INLINE void LL_MDMA_DisableIT_TE(MDMA_TypeDef *MDMAx, uint32_t Channel)
4078{
4079 uint32_t mdma_base_addr = (uint32_t)MDMAx;
4080
4081 CLEAR_BIT(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR ,MDMA_CCR_TEIE);
4082}
4083
4107__STATIC_INLINE void LL_MDMA_DisableIT_CTC(MDMA_TypeDef *MDMAx, uint32_t Channel)
4108{
4109 uint32_t mdma_base_addr = (uint32_t)MDMAx;
4110
4111 CLEAR_BIT(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR ,MDMA_CCR_CTCIE);
4112}
4113
4137__STATIC_INLINE void LL_MDMA_DisableIT_BRT(MDMA_TypeDef *MDMAx, uint32_t Channel)
4138{
4139 uint32_t mdma_base_addr = (uint32_t)MDMAx;
4140
4141 CLEAR_BIT(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR ,MDMA_CCR_BRTIE);
4142}
4143
4167__STATIC_INLINE void LL_MDMA_DisableIT_BT(MDMA_TypeDef *MDMAx, uint32_t Channel)
4168{
4169 uint32_t mdma_base_addr = (uint32_t)MDMAx;
4170
4171 CLEAR_BIT(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR ,MDMA_CCR_BTIE);
4172}
4173
4197__STATIC_INLINE void LL_MDMA_DisableIT_TC(MDMA_TypeDef *MDMAx, uint32_t Channel)
4198{
4199 uint32_t mdma_base_addr = (uint32_t)MDMAx;
4200
4201 CLEAR_BIT(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR ,MDMA_CCR_TCIE);
4202}
4203
4227__STATIC_INLINE uint32_t LL_MDMA_IsEnabledIT_TE(MDMA_TypeDef *MDMAx, uint32_t Channel)
4228{
4229 uint32_t mdma_base_addr = (uint32_t)MDMAx;
4230
4231 return ((READ_BIT(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR ,MDMA_CCR_TEIE) == MDMA_CCR_TEIE) ? 1UL : 0UL);
4232}
4233
4257__STATIC_INLINE uint32_t LL_MDMA_IsEnabledIT_CTC(MDMA_TypeDef *MDMAx, uint32_t Channel)
4258{
4259 uint32_t mdma_base_addr = (uint32_t)MDMAx;
4260
4261 return ((READ_BIT(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR ,MDMA_CCR_CTCIE) == MDMA_CCR_CTCIE) ? 1UL : 0UL);
4262}
4263
4287__STATIC_INLINE uint32_t LL_MDMA_IsEnabledIT_BRT(MDMA_TypeDef *MDMAx, uint32_t Channel)
4288{
4289 uint32_t mdma_base_addr = (uint32_t)MDMAx;
4290
4291 return ((READ_BIT(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR ,MDMA_CCR_BRTIE) == MDMA_CCR_BRTIE) ? 1UL : 0UL);
4292}
4293
4317__STATIC_INLINE uint32_t LL_MDMA_IsEnabledIT_BT(MDMA_TypeDef *MDMAx, uint32_t Channel)
4318{
4319 uint32_t mdma_base_addr = (uint32_t)MDMAx;
4320
4321 return ((READ_BIT(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR ,MDMA_CCR_BTIE) == MDMA_CCR_BTIE) ? 1UL : 0UL);
4322}
4323
4347__STATIC_INLINE uint32_t LL_MDMA_IsEnabledIT_TC(MDMA_TypeDef *MDMAx, uint32_t Channel)
4348{
4349 uint32_t mdma_base_addr = (uint32_t)MDMAx;
4350
4351 return ((READ_BIT(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR ,MDMA_CCR_TCIE) == MDMA_CCR_TCIE) ? 1UL : 0UL);
4352}
4353
4358#if defined(USE_FULL_LL_DRIVER) || defined(__rtems__)
4364uint32_t LL_MDMA_Init(MDMA_TypeDef *MDMAx, uint32_t Channel, LL_MDMA_InitTypeDef *MDMA_InitStruct);
4365uint32_t LL_MDMA_DeInit(MDMA_TypeDef *MDMAx, uint32_t Channel);
4366void LL_MDMA_StructInit(LL_MDMA_InitTypeDef *MDMA_InitStruct);
4367void LL_MDMA_CreateLinkNode(LL_MDMA_InitTypeDef *MDMA_InitStruct, LL_MDMA_LinkNodeTypeDef *pNode);
4368void LL_MDMA_ConnectLinkNode(LL_MDMA_LinkNodeTypeDef *pPrevLinkNode, LL_MDMA_LinkNodeTypeDef *pNewLinkNode);
4369void LL_MDMA_DisconnectNextLinkNode(LL_MDMA_LinkNodeTypeDef *pLinkNode);
4370
4374#endif /* USE_FULL_LL_DRIVER */
4375
4384#endif /* MDMA */
4385
4390#ifdef __cplusplus
4391}
4392#endif
4393
4394#endif /* STM32H7xx_LL_MDMA_H */
4395
__IO
#define __IO
Definition: core_cm4.h:239
MDMA_CBRUR_SUV_Msk
#define MDMA_CBRUR_SUV_Msk
Definition: stm32h723xx.h:13787
MDMA_CTCR_SWRM
#define MDMA_CTCR_SWRM
Definition: stm32h723xx.h:13756
MDMA_CTCR_DBURST
#define MDMA_CTCR_DBURST
Definition: stm32h723xx.h:13734
MDMA_CBNDTR_BNDT_Msk
#define MDMA_CBNDTR_BNDT_Msk
Definition: stm32h723xx.h:13763
MDMA_CISR_CTCIF
#define MDMA_CISR_CTCIF
Definition: stm32h723xx.h:13607
MDMA_CTBR_DBUS
#define MDMA_CTBR_DBUS
Definition: stm32h723xx.h:13807
MDMA_CISR_BRTIF
#define MDMA_CISR_BRTIF
Definition: stm32h723xx.h:13610
MDMA_CTBR_TSEL
#define MDMA_CTBR_TSEL
Definition: stm32h723xx.h:13801
MDMA_CESR_TEA
#define MDMA_CESR_TEA
Definition: stm32h723xx.h:13641
MDMA_CCR_HEX
#define MDMA_CCR_HEX
Definition: stm32h723xx.h:13687
MDMA_CCR_SWRQ
#define MDMA_CCR_SWRQ
Definition: stm32h723xx.h:13693
MDMA_CCR_BRTIE
#define MDMA_CCR_BRTIE
Definition: stm32h723xx.h:13670
MDMA_CISR_TCIF
#define MDMA_CISR_TCIF
Definition: stm32h723xx.h:13616
MDMA_CBRUR_SUV
#define MDMA_CBRUR_SUV
Definition: stm32h723xx.h:13788
MDMA_CTCR_DINCOS
#define MDMA_CTCR_DINCOS
Definition: stm32h723xx.h:13723
MDMA_CCR_TCIE
#define MDMA_CCR_TCIE
Definition: stm32h723xx.h:13676
MDMA_CESR_ASE
#define MDMA_CESR_ASE
Definition: stm32h723xx.h:13653
MDMA_CBNDTR_BRC
#define MDMA_CBNDTR_BRC
Definition: stm32h723xx.h:13773
MDMA_CTCR_BWM
#define MDMA_CTCR_BWM
Definition: stm32h723xx.h:13759
MDMA_CBRUR_DUV_Msk
#define MDMA_CBRUR_DUV_Msk
Definition: stm32h723xx.h:13790
MDMA_CTCR_SINCOS
#define MDMA_CTCR_SINCOS
Definition: stm32h723xx.h:13718
MDMA_CTCR_SBURST
#define MDMA_CTCR_SBURST
Definition: stm32h723xx.h:13728
MDMA_CTCR_PAM
#define MDMA_CTCR_PAM
Definition: stm32h723xx.h:13746
MDMA_CTCR_DINC
#define MDMA_CTCR_DINC
Definition: stm32h723xx.h:13703
MDMA_CCR_EN
#define MDMA_CCR_EN
Definition: stm32h723xx.h:13661
MDMA_CBNDTR_BRC_Msk
#define MDMA_CBNDTR_BRC_Msk
Definition: stm32h723xx.h:13772
MDMA_CBNDTR_BRSUM
#define MDMA_CBNDTR_BRSUM
Definition: stm32h723xx.h:13767
MDMA_CISR_CRQA
#define MDMA_CISR_CRQA
Definition: stm32h723xx.h:13619
MDMA_CTCR_DSIZE
#define MDMA_CTCR_DSIZE
Definition: stm32h723xx.h:13713
MDMA_CIFCR_CCTCIF
#define MDMA_CIFCR_CCTCIF
Definition: stm32h723xx.h:13627
MDMA_CIFCR_CBTIF
#define MDMA_CIFCR_CBTIF
Definition: stm32h723xx.h:13633
MDMA_CTCR_SSIZE
#define MDMA_CTCR_SSIZE
Definition: stm32h723xx.h:13708
MDMA_CCR_BEX
#define MDMA_CCR_BEX
Definition: stm32h723xx.h:13684
MDMA_CTCR_TLEN_Msk
#define MDMA_CTCR_TLEN_Msk
Definition: stm32h723xx.h:13739
MDMA_CESR_TED
#define MDMA_CESR_TED
Definition: stm32h723xx.h:13644
MDMA_CTBR_SBUS
#define MDMA_CTBR_SBUS
Definition: stm32h723xx.h:13804
MDMA_CIFCR_CBRTIF
#define MDMA_CIFCR_CBRTIF
Definition: stm32h723xx.h:13630
MDMA_CTCR_TLEN
#define MDMA_CTCR_TLEN
Definition: stm32h723xx.h:13740
MDMA_CBNDTR_BRDUM
#define MDMA_CBNDTR_BRDUM
Definition: stm32h723xx.h:13770
MDMA_CCR_BTIE
#define MDMA_CCR_BTIE
Definition: stm32h723xx.h:13673
MDMA_CCR_WEX
#define MDMA_CCR_WEX
Definition: stm32h723xx.h:13690
MDMA_CESR_BSE
#define MDMA_CESR_BSE
Definition: stm32h723xx.h:13656
MDMA_CESR_TELD
#define MDMA_CESR_TELD
Definition: stm32h723xx.h:13647
MDMA_CTCR_PKE
#define MDMA_CTCR_PKE
Definition: stm32h723xx.h:13743
MDMA_CISR_BTIF
#define MDMA_CISR_BTIF
Definition: stm32h723xx.h:13613
MDMA_CCR_CTCIE
#define MDMA_CCR_CTCIE
Definition: stm32h723xx.h:13667
MDMA_CISR_TEIF
#define MDMA_CISR_TEIF
Definition: stm32h723xx.h:13604
MDMA_CCR_PL
#define MDMA_CCR_PL
Definition: stm32h723xx.h:13679
MDMA_CTCR_TRGM
#define MDMA_CTCR_TRGM
Definition: stm32h723xx.h:13751
MDMA_CBNDTR_BNDT
#define MDMA_CBNDTR_BNDT
Definition: stm32h723xx.h:13764
MDMA_GISR0_GIF0
#define MDMA_GISR0_GIF0
Definition: stm32h723xx.h:13554
MDMA_CBRUR_DUV
#define MDMA_CBRUR_DUV
Definition: stm32h723xx.h:13791
MDMA_CCR_TEIE
#define MDMA_CCR_TEIE
Definition: stm32h723xx.h:13664
MDMA_CIFCR_CTEIF
#define MDMA_CIFCR_CTEIF
Definition: stm32h723xx.h:13624
MDMA_CIFCR_CLTCIF
#define MDMA_CIFCR_CLTCIF
Definition: stm32h723xx.h:13636
MDMA_CTCR_SINC
#define MDMA_CTCR_SINC
Definition: stm32h723xx.h:13698
MDMA_CESR_TEMD
#define MDMA_CESR_TEMD
Definition: stm32h723xx.h:13650
stm32h7xx.h
CMSIS STM32H7xx Device Peripheral Access Layer Header File.
MDMA_Channel_TypeDef
Definition: stm32h723xx.h:664
MDMA_TypeDef
MDMA Controller.
Definition: stm32h723xx.h:659
MDMA_TypeDef::GISR0
__IO uint32_t GISR0
Definition: stm32h723xx.h:660
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