RTEMS 6.1-rc4
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stm32h7xx_ll_dma2d.h
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1
19/* Define to prevent recursive inclusion -------------------------------------*/
20#ifndef STM32H7xx_LL_DMA2D_H
21#define STM32H7xx_LL_DMA2D_H
22
23#ifdef __cplusplus
24extern "C" {
25#endif
26
27/* Includes ------------------------------------------------------------------*/
28#include "stm32h7xx.h"
29
34#if defined (DMA2D)
35
41/* Private types -------------------------------------------------------------*/
42/* Private variables ---------------------------------------------------------*/
43/* Private constants ---------------------------------------------------------*/
44/* Private macros ------------------------------------------------------------*/
45#if defined(USE_FULL_LL_DRIVER) || defined(__rtems__)
54#endif /*USE_FULL_LL_DRIVER*/
55
56/* Exported types ------------------------------------------------------------*/
57#if defined(USE_FULL_LL_DRIVER) || defined(__rtems__)
66typedef struct
67{
68 uint32_t Mode;
74 uint32_t ColorMode;
80 uint32_t OutputBlue;
96 uint32_t OutputGreen;
112 uint32_t OutputRed;
128 uint32_t OutputAlpha;
141 uint32_t OutputMemoryAddress;
148 uint32_t OutputSwapMode;
154 uint32_t LineOffsetMode;
160 uint32_t LineOffset;
166 uint32_t NbrOfLines;
173 uint32_t NbrOfPixelsPerLines;
179 uint32_t AlphaInversionMode;
185 uint32_t RBSwapMode;
191} LL_DMA2D_InitTypeDef;
192
196typedef struct
197{
198 uint32_t MemoryAddress;
206 uint32_t LineOffset;
213 uint32_t ColorMode;
220 uint32_t CLUTColorMode;
227 uint32_t CLUTSize;
234 uint32_t AlphaMode;
241 uint32_t Alpha;
248 uint32_t Blue;
255 uint32_t Green;
262 uint32_t Red;
269 uint32_t CLUTMemoryAddress;
277 uint32_t AlphaInversionMode;
284 uint32_t RBSwapMode;
291 uint32_t ChromaSubSampling;
298} LL_DMA2D_LayerCfgTypeDef;
299
303typedef struct
304{
305 uint32_t ColorMode;
311 uint32_t OutputBlue;
327 uint32_t OutputGreen;
343 uint32_t OutputRed;
359 uint32_t OutputAlpha;
372} LL_DMA2D_ColorTypeDef;
373
377#endif /* USE_FULL_LL_DRIVER */
378
379/* Exported constants --------------------------------------------------------*/
390#define LL_DMA2D_FLAG_CEIF DMA2D_ISR_CEIF
391#define LL_DMA2D_FLAG_CTCIF DMA2D_ISR_CTCIF
392#define LL_DMA2D_FLAG_CAEIF DMA2D_ISR_CAEIF
393#define LL_DMA2D_FLAG_TWIF DMA2D_ISR_TWIF
394#define LL_DMA2D_FLAG_TCIF DMA2D_ISR_TCIF
395#define LL_DMA2D_FLAG_TEIF DMA2D_ISR_TEIF
405#define LL_DMA2D_IT_CEIE DMA2D_CR_CEIE
406#define LL_DMA2D_IT_CTCIE DMA2D_CR_CTCIE
407#define LL_DMA2D_IT_CAEIE DMA2D_CR_CAEIE
408#define LL_DMA2D_IT_TWIE DMA2D_CR_TWIE
409#define LL_DMA2D_IT_TCIE DMA2D_CR_TCIE
410#define LL_DMA2D_IT_TEIE DMA2D_CR_TEIE
419#define LL_DMA2D_MODE_M2M 0x00000000U
420#define LL_DMA2D_MODE_M2M_PFC DMA2D_CR_MODE_0
421#define LL_DMA2D_MODE_M2M_BLEND DMA2D_CR_MODE_1
422#define LL_DMA2D_MODE_R2M (DMA2D_CR_MODE_0|DMA2D_CR_MODE_1)
423#define LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_FG DMA2D_CR_MODE_2
424#define LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_BG (DMA2D_CR_MODE_0|DMA2D_CR_MODE_2)
433#define LL_DMA2D_OUTPUT_MODE_ARGB8888 0x00000000U
434#define LL_DMA2D_OUTPUT_MODE_RGB888 DMA2D_OPFCCR_CM_0
435#define LL_DMA2D_OUTPUT_MODE_RGB565 DMA2D_OPFCCR_CM_1
436#define LL_DMA2D_OUTPUT_MODE_ARGB1555 (DMA2D_OPFCCR_CM_0|DMA2D_OPFCCR_CM_1)
437#define LL_DMA2D_OUTPUT_MODE_ARGB4444 DMA2D_OPFCCR_CM_2
446#define LL_DMA2D_INPUT_MODE_ARGB8888 0x00000000U
447#define LL_DMA2D_INPUT_MODE_RGB888 DMA2D_FGPFCCR_CM_0
448#define LL_DMA2D_INPUT_MODE_RGB565 DMA2D_FGPFCCR_CM_1
449#define LL_DMA2D_INPUT_MODE_ARGB1555 (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_1)
450#define LL_DMA2D_INPUT_MODE_ARGB4444 DMA2D_FGPFCCR_CM_2
451#define LL_DMA2D_INPUT_MODE_L8 (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_2)
452#define LL_DMA2D_INPUT_MODE_AL44 (DMA2D_FGPFCCR_CM_1|DMA2D_FGPFCCR_CM_2)
453#define LL_DMA2D_INPUT_MODE_AL88 (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_1|DMA2D_FGPFCCR_CM_2)
454#define LL_DMA2D_INPUT_MODE_L4 DMA2D_FGPFCCR_CM_3
455#define LL_DMA2D_INPUT_MODE_A8 (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_3)
456#define LL_DMA2D_INPUT_MODE_A4 (DMA2D_FGPFCCR_CM_1|DMA2D_FGPFCCR_CM_3)
457#define LL_DMA2D_INPUT_MODE_YCBCR (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_1|DMA2D_FGPFCCR_CM_3)
466#define LL_DMA2D_ALPHA_MODE_NO_MODIF 0x00000000U
467#define LL_DMA2D_ALPHA_MODE_REPLACE DMA2D_FGPFCCR_AM_0
469#define LL_DMA2D_ALPHA_MODE_COMBINE DMA2D_FGPFCCR_AM_1
480#define LL_DMA2D_SWAP_MODE_REGULAR 0x00000000U
481#define LL_DMA2D_SWAP_MODE_TWO_BY_TWO DMA2D_OPFCCR_SB
490#define LL_DMA2D_RB_MODE_REGULAR 0x00000000U
491#define LL_DMA2D_RB_MODE_SWAP DMA2D_FGPFCCR_RBS
500#define LL_DMA2D_ALPHA_REGULAR 0x00000000U
501#define LL_DMA2D_ALPHA_INVERTED DMA2D_FGPFCCR_AI
511#define LL_DMA2D_LINE_OFFSET_PIXELS 0x00000000U
512#define LL_DMA2D_LINE_OFFSET_BYTES DMA2D_CR_LOM
521#define LL_DMA2D_CLUT_COLOR_MODE_ARGB8888 0x00000000U
522#define LL_DMA2D_CLUT_COLOR_MODE_RGB888 DMA2D_FGPFCCR_CCM
531#define LL_DMA2D_CSS_444 0x00000000U
532#define LL_DMA2D_CSS_422 DMA2D_FGPFCCR_CSS_0
533#define LL_DMA2D_CSS_420 DMA2D_FGPFCCR_CSS_1
542/* Exported macro ------------------------------------------------------------*/
560#define LL_DMA2D_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
561
568#define LL_DMA2D_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
577/* Exported functions --------------------------------------------------------*/
594__STATIC_INLINE void LL_DMA2D_Start(DMA2D_TypeDef *DMA2Dx)
595{
596 SET_BIT(DMA2Dx->CR, DMA2D_CR_START);
597}
598
605__STATIC_INLINE uint32_t LL_DMA2D_IsTransferOngoing(DMA2D_TypeDef *DMA2Dx)
606{
607 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_START) == (DMA2D_CR_START)) ? 1UL : 0UL);
608}
609
617__STATIC_INLINE void LL_DMA2D_Suspend(DMA2D_TypeDef *DMA2Dx)
618{
619 MODIFY_REG(DMA2Dx->CR, DMA2D_CR_SUSP | DMA2D_CR_START, DMA2D_CR_SUSP);
620}
621
629__STATIC_INLINE void LL_DMA2D_Resume(DMA2D_TypeDef *DMA2Dx)
630{
631 CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_SUSP | DMA2D_CR_START);
632}
633
642__STATIC_INLINE uint32_t LL_DMA2D_IsSuspended(DMA2D_TypeDef *DMA2Dx)
643{
644 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_SUSP) == (DMA2D_CR_SUSP)) ? 1UL : 0UL);
645}
646
654__STATIC_INLINE void LL_DMA2D_Abort(DMA2D_TypeDef *DMA2Dx)
655{
656 MODIFY_REG(DMA2Dx->CR, DMA2D_CR_ABORT | DMA2D_CR_START, DMA2D_CR_ABORT);
657}
658
667__STATIC_INLINE uint32_t LL_DMA2D_IsAborted(DMA2D_TypeDef *DMA2Dx)
668{
669 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_ABORT) == (DMA2D_CR_ABORT)) ? 1UL : 0UL);
670}
671
685__STATIC_INLINE void LL_DMA2D_SetMode(DMA2D_TypeDef *DMA2Dx, uint32_t Mode)
686{
687 MODIFY_REG(DMA2Dx->CR, DMA2D_CR_MODE, Mode);
688}
689
702__STATIC_INLINE uint32_t LL_DMA2D_GetMode(DMA2D_TypeDef *DMA2Dx)
703{
704 return (uint32_t)(READ_BIT(DMA2Dx->CR, DMA2D_CR_MODE));
705}
706
719__STATIC_INLINE void LL_DMA2D_SetOutputColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
720{
721 MODIFY_REG(DMA2Dx->OPFCCR, DMA2D_OPFCCR_CM, ColorMode);
722}
723
735__STATIC_INLINE uint32_t LL_DMA2D_GetOutputColorMode(DMA2D_TypeDef *DMA2Dx)
736{
737 return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_CM));
738}
739
749__STATIC_INLINE void LL_DMA2D_SetOutputRBSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_t RBSwapMode)
750{
751 MODIFY_REG(DMA2Dx->OPFCCR, DMA2D_OPFCCR_RBS, RBSwapMode);
752}
753
762__STATIC_INLINE uint32_t LL_DMA2D_GetOutputRBSwapMode(DMA2D_TypeDef *DMA2Dx)
763{
764 return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_RBS));
765}
766
776__STATIC_INLINE void LL_DMA2D_SetOutputAlphaInvMode(DMA2D_TypeDef *DMA2Dx, uint32_t AlphaInversionMode)
777{
778 MODIFY_REG(DMA2Dx->OPFCCR, DMA2D_OPFCCR_AI, AlphaInversionMode);
779}
780
789__STATIC_INLINE uint32_t LL_DMA2D_GetOutputAlphaInvMode(DMA2D_TypeDef *DMA2Dx)
790{
791 return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_AI));
792}
793
794
804__STATIC_INLINE void LL_DMA2D_SetOutputSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_t OutputSwapMode)
805{
806 MODIFY_REG(DMA2Dx->OPFCCR, DMA2D_OPFCCR_SB, OutputSwapMode);
807}
808
817__STATIC_INLINE uint32_t LL_DMA2D_GetOutputSwapMode(DMA2D_TypeDef *DMA2Dx)
818{
819 return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_SB));
820}
821
831__STATIC_INLINE void LL_DMA2D_SetLineOffsetMode(DMA2D_TypeDef *DMA2Dx, uint32_t LineOffsetMode)
832{
833 MODIFY_REG(DMA2Dx->CR, DMA2D_CR_LOM, LineOffsetMode);
834}
835
844__STATIC_INLINE uint32_t LL_DMA2D_GetLineOffsetMode(DMA2D_TypeDef *DMA2Dx)
845{
846 return (uint32_t)(READ_BIT(DMA2Dx->CR, DMA2D_CR_LOM));
847}
848
856__STATIC_INLINE void LL_DMA2D_SetLineOffset(DMA2D_TypeDef *DMA2Dx, uint32_t LineOffset)
857{
858 MODIFY_REG(DMA2Dx->OOR, DMA2D_OOR_LO, LineOffset);
859}
860
867__STATIC_INLINE uint32_t LL_DMA2D_GetLineOffset(DMA2D_TypeDef *DMA2Dx)
868{
869 return (uint32_t)(READ_BIT(DMA2Dx->OOR, DMA2D_OOR_LO));
870}
871
879__STATIC_INLINE void LL_DMA2D_SetNbrOfPixelsPerLines(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfPixelsPerLines)
880{
881 MODIFY_REG(DMA2Dx->NLR, DMA2D_NLR_PL, (NbrOfPixelsPerLines << DMA2D_NLR_PL_Pos));
882}
883
890__STATIC_INLINE uint32_t LL_DMA2D_GetNbrOfPixelsPerLines(DMA2D_TypeDef *DMA2Dx)
891{
892 return (uint32_t)(READ_BIT(DMA2Dx->NLR, DMA2D_NLR_PL) >> DMA2D_NLR_PL_Pos);
893}
894
902__STATIC_INLINE void LL_DMA2D_SetNbrOfLines(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfLines)
903{
904 MODIFY_REG(DMA2Dx->NLR, DMA2D_NLR_NL, NbrOfLines);
905}
906
913__STATIC_INLINE uint32_t LL_DMA2D_GetNbrOfLines(DMA2D_TypeDef *DMA2Dx)
914{
915 return (uint32_t)(READ_BIT(DMA2Dx->NLR, DMA2D_NLR_NL));
916}
917
925__STATIC_INLINE void LL_DMA2D_SetOutputMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t OutputMemoryAddress)
926{
927 LL_DMA2D_WriteReg(DMA2Dx, OMAR, OutputMemoryAddress);
928}
929
936__STATIC_INLINE uint32_t LL_DMA2D_GetOutputMemAddr(DMA2D_TypeDef *DMA2Dx)
937{
938 return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, OMAR));
939}
940
955__STATIC_INLINE void LL_DMA2D_SetOutputColor(DMA2D_TypeDef *DMA2Dx, uint32_t OutputColor)
956{
958 OutputColor);
959}
960
973__STATIC_INLINE uint32_t LL_DMA2D_GetOutputColor(DMA2D_TypeDef *DMA2Dx)
974{
975 return (uint32_t)(READ_BIT(DMA2Dx->OCOLR, \
977}
978
986__STATIC_INLINE void LL_DMA2D_SetLineWatermark(DMA2D_TypeDef *DMA2Dx, uint32_t LineWatermark)
987{
988 MODIFY_REG(DMA2Dx->LWR, DMA2D_LWR_LW, LineWatermark);
989}
990
997__STATIC_INLINE uint32_t LL_DMA2D_GetLineWatermark(DMA2D_TypeDef *DMA2Dx)
998{
999 return (uint32_t)(READ_BIT(DMA2Dx->LWR, DMA2D_LWR_LW));
1000}
1001
1009__STATIC_INLINE void LL_DMA2D_SetDeadTime(DMA2D_TypeDef *DMA2Dx, uint32_t DeadTime)
1010{
1011 MODIFY_REG(DMA2Dx->AMTCR, DMA2D_AMTCR_DT, (DeadTime << DMA2D_AMTCR_DT_Pos));
1012}
1013
1020__STATIC_INLINE uint32_t LL_DMA2D_GetDeadTime(DMA2D_TypeDef *DMA2Dx)
1021{
1022 return (uint32_t)(READ_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_DT) >> DMA2D_AMTCR_DT_Pos);
1023}
1024
1031__STATIC_INLINE void LL_DMA2D_EnableDeadTime(DMA2D_TypeDef *DMA2Dx)
1032{
1033 SET_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN);
1034}
1035
1042__STATIC_INLINE void LL_DMA2D_DisableDeadTime(DMA2D_TypeDef *DMA2Dx)
1043{
1044 CLEAR_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN);
1045}
1046
1053__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledDeadTime(DMA2D_TypeDef *DMA2Dx)
1054{
1055 return ((READ_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN) == (DMA2D_AMTCR_EN)) ? 1UL : 0UL);
1056}
1057
1070__STATIC_INLINE void LL_DMA2D_FGND_SetMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t MemoryAddress)
1071{
1072 LL_DMA2D_WriteReg(DMA2Dx, FGMAR, MemoryAddress);
1073}
1074
1081__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetMemAddr(DMA2D_TypeDef *DMA2Dx)
1082{
1083 return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, FGMAR));
1084}
1085
1092__STATIC_INLINE void LL_DMA2D_FGND_EnableCLUTLoad(DMA2D_TypeDef *DMA2Dx)
1093{
1094 SET_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_START);
1095}
1096
1103__STATIC_INLINE uint32_t LL_DMA2D_FGND_IsEnabledCLUTLoad(DMA2D_TypeDef *DMA2Dx)
1104{
1105 return ((READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_START) == (DMA2D_FGPFCCR_START)) ? 1UL : 0UL);
1106}
1107
1126__STATIC_INLINE void LL_DMA2D_FGND_SetColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
1127{
1128 MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CM, ColorMode);
1129}
1130
1148__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetColorMode(DMA2D_TypeDef *DMA2Dx)
1149{
1150 return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CM));
1151}
1152
1163__STATIC_INLINE void LL_DMA2D_FGND_SetAlphaMode(DMA2D_TypeDef *DMA2Dx, uint32_t AphaMode)
1164{
1165 MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AM, AphaMode);
1166}
1167
1177__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlphaMode(DMA2D_TypeDef *DMA2Dx)
1178{
1179 return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AM));
1180}
1181
1189__STATIC_INLINE void LL_DMA2D_FGND_SetAlpha(DMA2D_TypeDef *DMA2Dx, uint32_t Alpha)
1190{
1191 MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_ALPHA, (Alpha << DMA2D_FGPFCCR_ALPHA_Pos));
1192}
1193
1200__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlpha(DMA2D_TypeDef *DMA2Dx)
1201{
1202 return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_ALPHA) >> DMA2D_FGPFCCR_ALPHA_Pos);
1203}
1204
1214__STATIC_INLINE void LL_DMA2D_FGND_SetRBSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_t RBSwapMode)
1215{
1216 MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_RBS, RBSwapMode);
1217}
1218
1227__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetRBSwapMode(DMA2D_TypeDef *DMA2Dx)
1228{
1229 return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_RBS));
1230}
1231
1241__STATIC_INLINE void LL_DMA2D_FGND_SetAlphaInvMode(DMA2D_TypeDef *DMA2Dx, uint32_t AlphaInversionMode)
1242{
1243 MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AI, AlphaInversionMode);
1244}
1245
1254__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlphaInvMode(DMA2D_TypeDef *DMA2Dx)
1255{
1256 return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AI));
1257}
1258
1266__STATIC_INLINE void LL_DMA2D_FGND_SetLineOffset(DMA2D_TypeDef *DMA2Dx, uint32_t LineOffset)
1267{
1268 MODIFY_REG(DMA2Dx->FGOR, DMA2D_FGOR_LO, LineOffset);
1269}
1270
1277__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetLineOffset(DMA2D_TypeDef *DMA2Dx)
1278{
1279 return (uint32_t)(READ_BIT(DMA2Dx->FGOR, DMA2D_FGOR_LO));
1280}
1281
1293__STATIC_INLINE void LL_DMA2D_FGND_SetColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red, uint32_t Green, uint32_t Blue)
1294{
1295 MODIFY_REG(DMA2Dx->FGCOLR, (DMA2D_FGCOLR_RED | DMA2D_FGCOLR_GREEN | DMA2D_FGCOLR_BLUE), \
1296 ((Red << DMA2D_FGCOLR_RED_Pos) | (Green << DMA2D_FGCOLR_GREEN_Pos) | Blue));
1297}
1298
1306__STATIC_INLINE void LL_DMA2D_FGND_SetRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red)
1307{
1308 MODIFY_REG(DMA2Dx->FGCOLR, DMA2D_FGCOLR_RED, (Red << DMA2D_FGCOLR_RED_Pos));
1309}
1310
1317__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetRedColor(DMA2D_TypeDef *DMA2Dx)
1318{
1319 return (uint32_t)(READ_BIT(DMA2Dx->FGCOLR, DMA2D_FGCOLR_RED) >> DMA2D_FGCOLR_RED_Pos);
1320}
1321
1329__STATIC_INLINE void LL_DMA2D_FGND_SetGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t Green)
1330{
1331 MODIFY_REG(DMA2Dx->FGCOLR, DMA2D_FGCOLR_GREEN, (Green << DMA2D_FGCOLR_GREEN_Pos));
1332}
1333
1340__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetGreenColor(DMA2D_TypeDef *DMA2Dx)
1341{
1342 return (uint32_t)(READ_BIT(DMA2Dx->FGCOLR, DMA2D_FGCOLR_GREEN) >> DMA2D_FGCOLR_GREEN_Pos);
1343}
1344
1352__STATIC_INLINE void LL_DMA2D_FGND_SetBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t Blue)
1353{
1354 MODIFY_REG(DMA2Dx->FGCOLR, DMA2D_FGCOLR_BLUE, Blue);
1355}
1356
1363__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetBlueColor(DMA2D_TypeDef *DMA2Dx)
1364{
1365 return (uint32_t)(READ_BIT(DMA2Dx->FGCOLR, DMA2D_FGCOLR_BLUE));
1366}
1367
1375__STATIC_INLINE void LL_DMA2D_FGND_SetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTMemoryAddress)
1376{
1377 LL_DMA2D_WriteReg(DMA2Dx, FGCMAR, CLUTMemoryAddress);
1378}
1379
1386__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx)
1387{
1388 return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, FGCMAR));
1389}
1390
1398__STATIC_INLINE void LL_DMA2D_FGND_SetCLUTSize(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTSize)
1399{
1400 MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CS, (CLUTSize << DMA2D_FGPFCCR_CS_Pos));
1401}
1402
1409__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTSize(DMA2D_TypeDef *DMA2Dx)
1410{
1411 return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CS) >> DMA2D_FGPFCCR_CS_Pos);
1412}
1413
1423__STATIC_INLINE void LL_DMA2D_FGND_SetCLUTColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTColorMode)
1424{
1425 MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CCM, CLUTColorMode);
1426}
1427
1436__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTColorMode(DMA2D_TypeDef *DMA2Dx)
1437{
1438 return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CCM));
1439}
1440
1451__STATIC_INLINE void LL_DMA2D_FGND_SetChrSubSampling(DMA2D_TypeDef *DMA2Dx, uint32_t ChromaSubSampling)
1452{
1453 MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CSS, ChromaSubSampling);
1454}
1455
1465__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetChrSubSampling(DMA2D_TypeDef *DMA2Dx)
1466{
1467 return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CSS));
1468}
1485__STATIC_INLINE void LL_DMA2D_BGND_SetMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t MemoryAddress)
1486{
1487 LL_DMA2D_WriteReg(DMA2Dx, BGMAR, MemoryAddress);
1488}
1489
1496__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetMemAddr(DMA2D_TypeDef *DMA2Dx)
1497{
1498 return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, BGMAR));
1499}
1500
1507__STATIC_INLINE void LL_DMA2D_BGND_EnableCLUTLoad(DMA2D_TypeDef *DMA2Dx)
1508{
1509 SET_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_START);
1510}
1511
1518__STATIC_INLINE uint32_t LL_DMA2D_BGND_IsEnabledCLUTLoad(DMA2D_TypeDef *DMA2Dx)
1519{
1520 return ((READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_START) == (DMA2D_BGPFCCR_START)) ? 1UL : 0UL);
1521}
1522
1541__STATIC_INLINE void LL_DMA2D_BGND_SetColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
1542{
1543 MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CM, ColorMode);
1544}
1545
1563__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetColorMode(DMA2D_TypeDef *DMA2Dx)
1564{
1565 return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CM));
1566}
1567
1578__STATIC_INLINE void LL_DMA2D_BGND_SetAlphaMode(DMA2D_TypeDef *DMA2Dx, uint32_t AphaMode)
1579{
1580 MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AM, AphaMode);
1581}
1582
1592__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetAlphaMode(DMA2D_TypeDef *DMA2Dx)
1593{
1594 return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AM));
1595}
1596
1604__STATIC_INLINE void LL_DMA2D_BGND_SetAlpha(DMA2D_TypeDef *DMA2Dx, uint32_t Alpha)
1605{
1606 MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_ALPHA, (Alpha << DMA2D_BGPFCCR_ALPHA_Pos));
1607}
1608
1615__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetAlpha(DMA2D_TypeDef *DMA2Dx)
1616{
1617 return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_ALPHA) >> DMA2D_BGPFCCR_ALPHA_Pos);
1618}
1619
1629__STATIC_INLINE void LL_DMA2D_BGND_SetRBSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_t RBSwapMode)
1630{
1631 MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_RBS, RBSwapMode);
1632}
1633
1642__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetRBSwapMode(DMA2D_TypeDef *DMA2Dx)
1643{
1644 return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_RBS));
1645}
1646
1656__STATIC_INLINE void LL_DMA2D_BGND_SetAlphaInvMode(DMA2D_TypeDef *DMA2Dx, uint32_t AlphaInversionMode)
1657{
1658 MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AI, AlphaInversionMode);
1659}
1660
1669__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetAlphaInvMode(DMA2D_TypeDef *DMA2Dx)
1670{
1671 return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AI));
1672}
1673
1681__STATIC_INLINE void LL_DMA2D_BGND_SetLineOffset(DMA2D_TypeDef *DMA2Dx, uint32_t LineOffset)
1682{
1683 MODIFY_REG(DMA2Dx->BGOR, DMA2D_BGOR_LO, LineOffset);
1684}
1685
1692__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetLineOffset(DMA2D_TypeDef *DMA2Dx)
1693{
1694 return (uint32_t)(READ_BIT(DMA2Dx->BGOR, DMA2D_BGOR_LO));
1695}
1696
1708__STATIC_INLINE void LL_DMA2D_BGND_SetColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red, uint32_t Green, uint32_t Blue)
1709{
1710 MODIFY_REG(DMA2Dx->BGCOLR, (DMA2D_BGCOLR_RED | DMA2D_BGCOLR_GREEN | DMA2D_BGCOLR_BLUE), \
1711 ((Red << DMA2D_BGCOLR_RED_Pos) | (Green << DMA2D_BGCOLR_GREEN_Pos) | Blue));
1712}
1713
1721__STATIC_INLINE void LL_DMA2D_BGND_SetRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red)
1722{
1723 MODIFY_REG(DMA2Dx->BGCOLR, DMA2D_BGCOLR_RED, (Red << DMA2D_BGCOLR_RED_Pos));
1724}
1725
1732__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetRedColor(DMA2D_TypeDef *DMA2Dx)
1733{
1734 return (uint32_t)(READ_BIT(DMA2Dx->BGCOLR, DMA2D_BGCOLR_RED) >> DMA2D_BGCOLR_RED_Pos);
1735}
1736
1744__STATIC_INLINE void LL_DMA2D_BGND_SetGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t Green)
1745{
1746 MODIFY_REG(DMA2Dx->BGCOLR, DMA2D_BGCOLR_GREEN, (Green << DMA2D_BGCOLR_GREEN_Pos));
1747}
1748
1755__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetGreenColor(DMA2D_TypeDef *DMA2Dx)
1756{
1757 return (uint32_t)(READ_BIT(DMA2Dx->BGCOLR, DMA2D_BGCOLR_GREEN) >> DMA2D_BGCOLR_GREEN_Pos);
1758}
1759
1767__STATIC_INLINE void LL_DMA2D_BGND_SetBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t Blue)
1768{
1769 MODIFY_REG(DMA2Dx->BGCOLR, DMA2D_BGCOLR_BLUE, Blue);
1770}
1771
1778__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetBlueColor(DMA2D_TypeDef *DMA2Dx)
1779{
1780 return (uint32_t)(READ_BIT(DMA2Dx->BGCOLR, DMA2D_BGCOLR_BLUE));
1781}
1782
1790__STATIC_INLINE void LL_DMA2D_BGND_SetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTMemoryAddress)
1791{
1792 LL_DMA2D_WriteReg(DMA2Dx, BGCMAR, CLUTMemoryAddress);
1793}
1794
1801__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx)
1802{
1803 return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, BGCMAR));
1804}
1805
1813__STATIC_INLINE void LL_DMA2D_BGND_SetCLUTSize(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTSize)
1814{
1815 MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CS, (CLUTSize << DMA2D_BGPFCCR_CS_Pos));
1816}
1817
1824__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTSize(DMA2D_TypeDef *DMA2Dx)
1825{
1826 return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CS) >> DMA2D_BGPFCCR_CS_Pos);
1827}
1828
1838__STATIC_INLINE void LL_DMA2D_BGND_SetCLUTColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTColorMode)
1839{
1840 MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CCM, CLUTColorMode);
1841}
1842
1851__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTColorMode(DMA2D_TypeDef *DMA2Dx)
1852{
1853 return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CCM));
1854}
1855
1876__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CE(DMA2D_TypeDef *DMA2Dx)
1877{
1878 return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CEIF) == (DMA2D_ISR_CEIF)) ? 1UL : 0UL);
1879}
1880
1887__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CTC(DMA2D_TypeDef *DMA2Dx)
1888{
1889 return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CTCIF) == (DMA2D_ISR_CTCIF)) ? 1UL : 0UL);
1890}
1891
1898__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CAE(DMA2D_TypeDef *DMA2Dx)
1899{
1900 return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CAEIF) == (DMA2D_ISR_CAEIF)) ? 1UL : 0UL);
1901}
1902
1909__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TW(DMA2D_TypeDef *DMA2Dx)
1910{
1911 return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TWIF) == (DMA2D_ISR_TWIF)) ? 1UL : 0UL);
1912}
1913
1920__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TC(DMA2D_TypeDef *DMA2Dx)
1921{
1922 return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TCIF) == (DMA2D_ISR_TCIF)) ? 1UL : 0UL);
1923}
1924
1931__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TE(DMA2D_TypeDef *DMA2Dx)
1932{
1933 return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TEIF) == (DMA2D_ISR_TEIF)) ? 1UL : 0UL);
1934}
1935
1942__STATIC_INLINE void LL_DMA2D_ClearFlag_CE(DMA2D_TypeDef *DMA2Dx)
1943{
1944 WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CCEIF);
1945}
1946
1953__STATIC_INLINE void LL_DMA2D_ClearFlag_CTC(DMA2D_TypeDef *DMA2Dx)
1954{
1955 WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CCTCIF);
1956}
1957
1964__STATIC_INLINE void LL_DMA2D_ClearFlag_CAE(DMA2D_TypeDef *DMA2Dx)
1965{
1966 WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CAECIF);
1967}
1968
1975__STATIC_INLINE void LL_DMA2D_ClearFlag_TW(DMA2D_TypeDef *DMA2Dx)
1976{
1977 WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CTWIF);
1978}
1979
1986__STATIC_INLINE void LL_DMA2D_ClearFlag_TC(DMA2D_TypeDef *DMA2Dx)
1987{
1988 WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CTCIF);
1989}
1990
1997__STATIC_INLINE void LL_DMA2D_ClearFlag_TE(DMA2D_TypeDef *DMA2Dx)
1998{
1999 WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CTEIF);
2000}
2001
2017__STATIC_INLINE void LL_DMA2D_EnableIT_CE(DMA2D_TypeDef *DMA2Dx)
2018{
2019 SET_BIT(DMA2Dx->CR, DMA2D_CR_CEIE);
2020}
2021
2028__STATIC_INLINE void LL_DMA2D_EnableIT_CTC(DMA2D_TypeDef *DMA2Dx)
2029{
2030 SET_BIT(DMA2Dx->CR, DMA2D_CR_CTCIE);
2031}
2032
2039__STATIC_INLINE void LL_DMA2D_EnableIT_CAE(DMA2D_TypeDef *DMA2Dx)
2040{
2041 SET_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE);
2042}
2043
2050__STATIC_INLINE void LL_DMA2D_EnableIT_TW(DMA2D_TypeDef *DMA2Dx)
2051{
2052 SET_BIT(DMA2Dx->CR, DMA2D_CR_TWIE);
2053}
2054
2061__STATIC_INLINE void LL_DMA2D_EnableIT_TC(DMA2D_TypeDef *DMA2Dx)
2062{
2063 SET_BIT(DMA2Dx->CR, DMA2D_CR_TCIE);
2064}
2065
2072__STATIC_INLINE void LL_DMA2D_EnableIT_TE(DMA2D_TypeDef *DMA2Dx)
2073{
2074 SET_BIT(DMA2Dx->CR, DMA2D_CR_TEIE);
2075}
2076
2083__STATIC_INLINE void LL_DMA2D_DisableIT_CE(DMA2D_TypeDef *DMA2Dx)
2084{
2085 CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_CEIE);
2086}
2087
2094__STATIC_INLINE void LL_DMA2D_DisableIT_CTC(DMA2D_TypeDef *DMA2Dx)
2095{
2096 CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_CTCIE);
2097}
2098
2105__STATIC_INLINE void LL_DMA2D_DisableIT_CAE(DMA2D_TypeDef *DMA2Dx)
2106{
2107 CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE);
2108}
2109
2116__STATIC_INLINE void LL_DMA2D_DisableIT_TW(DMA2D_TypeDef *DMA2Dx)
2117{
2118 CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_TWIE);
2119}
2120
2127__STATIC_INLINE void LL_DMA2D_DisableIT_TC(DMA2D_TypeDef *DMA2Dx)
2128{
2129 CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_TCIE);
2130}
2131
2138__STATIC_INLINE void LL_DMA2D_DisableIT_TE(DMA2D_TypeDef *DMA2Dx)
2139{
2140 CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_TEIE);
2141}
2142
2149__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CE(DMA2D_TypeDef *DMA2Dx)
2150{
2151 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_CEIE) == (DMA2D_CR_CEIE)) ? 1UL : 0UL);
2152}
2153
2160__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CTC(DMA2D_TypeDef *DMA2Dx)
2161{
2162 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_CTCIE) == (DMA2D_CR_CTCIE)) ? 1UL : 0UL);
2163}
2164
2171__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CAE(DMA2D_TypeDef *DMA2Dx)
2172{
2173 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE) == (DMA2D_CR_CAEIE)) ? 1UL : 0UL);
2174}
2175
2182__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TW(DMA2D_TypeDef *DMA2Dx)
2183{
2184 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_TWIE) == (DMA2D_CR_TWIE)) ? 1UL : 0UL);
2185}
2186
2193__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TC(DMA2D_TypeDef *DMA2Dx)
2194{
2195 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_TCIE) == (DMA2D_CR_TCIE)) ? 1UL : 0UL);
2196}
2197
2204__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TE(DMA2D_TypeDef *DMA2Dx)
2205{
2206 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_TEIE) == (DMA2D_CR_TEIE)) ? 1UL : 0UL);
2207}
2208
2209
2210
2215#if defined(USE_FULL_LL_DRIVER) || defined(__rtems__)
2221ErrorStatus LL_DMA2D_DeInit(DMA2D_TypeDef *DMA2Dx);
2222ErrorStatus LL_DMA2D_Init(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_InitTypeDef *DMA2D_InitStruct);
2223void LL_DMA2D_StructInit(LL_DMA2D_InitTypeDef *DMA2D_InitStruct);
2224void LL_DMA2D_ConfigLayer(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_LayerCfgTypeDef *DMA2D_LayerCfg, uint32_t LayerIdx);
2225void LL_DMA2D_LayerCfgStructInit(LL_DMA2D_LayerCfgTypeDef *DMA2D_LayerCfg);
2226void LL_DMA2D_ConfigOutputColor(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_ColorTypeDef *DMA2D_ColorStruct);
2227uint32_t LL_DMA2D_GetOutputBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode);
2228uint32_t LL_DMA2D_GetOutputGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode);
2229uint32_t LL_DMA2D_GetOutputRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode);
2230uint32_t LL_DMA2D_GetOutputAlphaColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode);
2231void LL_DMA2D_ConfigSize(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfLines, uint32_t NbrOfPixelsPerLines);
2232
2236#endif /* USE_FULL_LL_DRIVER */
2237
2246#endif /* defined (DMA2D) */
2247
2252#ifdef __cplusplus
2253}
2254#endif
2255
2256#endif /* STM32H7xx_LL_DMA2D_H */
#define DMA2D_ISR_CEIF
Definition: stm32h723xx.h:9443
#define DMA2D_BGCOLR_GREEN
Definition: stm32h723xx.h:9580
#define DMA2D_FGCOLR_RED
Definition: stm32h723xx.h:9538
#define DMA2D_OCOLR_BLUE_1
Definition: stm32h723xx.h:9621
#define DMA2D_CR_CTCIE
Definition: stm32h723xx.h:9413
#define DMA2D_CR_START
Definition: stm32h723xx.h:9389
#define DMA2D_IFCR_CTCIF
Definition: stm32h723xx.h:9452
#define DMA2D_ISR_TWIF
Definition: stm32h723xx.h:9434
#define DMA2D_IFCR_CCEIF
Definition: stm32h723xx.h:9464
#define DMA2D_IFCR_CTEIF
Definition: stm32h723xx.h:9449
#define DMA2D_FGPFCCR_ALPHA
Definition: stm32h723xx.h:9526
#define DMA2D_IFCR_CAECIF
Definition: stm32h723xx.h:9458
#define DMA2D_AMTCR_DT
Definition: stm32h723xx.h:9705
#define DMA2D_OPFCCR_AI
Definition: stm32h723xx.h:9610
#define DMA2D_BGCOLR_RED
Definition: stm32h723xx.h:9583
#define DMA2D_BGPFCCR_RBS
Definition: stm32h723xx.h:9568
#define DMA2D_FGPFCCR_CS
Definition: stm32h723xx.h:9507
#define DMA2D_BGPFCCR_ALPHA
Definition: stm32h723xx.h:9571
#define DMA2D_BGOR_LO
Definition: stm32h723xx.h:9488
#define DMA2D_BGPFCCR_AI
Definition: stm32h723xx.h:9565
#define DMA2D_FGCOLR_BLUE
Definition: stm32h723xx.h:9532
#define DMA2D_CR_TEIE
Definition: stm32h723xx.h:9401
#define DMA2D_CR_SUSP
Definition: stm32h723xx.h:9392
#define DMA2D_FGPFCCR_AM
Definition: stm32h723xx.h:9510
#define DMA2D_FGPFCCR_RBS
Definition: stm32h723xx.h:9523
#define DMA2D_BGPFCCR_CS
Definition: stm32h723xx.h:9557
#define DMA2D_BGPFCCR_CM
Definition: stm32h723xx.h:9544
#define DMA2D_CR_CEIE
Definition: stm32h723xx.h:9416
#define DMA2D_IFCR_CCTCIF
Definition: stm32h723xx.h:9461
#define DMA2D_FGPFCCR_START
Definition: stm32h723xx.h:9504
#define DMA2D_ISR_TEIF
Definition: stm32h723xx.h:9428
#define DMA2D_BGPFCCR_CCM
Definition: stm32h723xx.h:9551
#define DMA2D_ISR_CTCIF
Definition: stm32h723xx.h:9440
#define DMA2D_BGCOLR_BLUE
Definition: stm32h723xx.h:9577
#define DMA2D_FGPFCCR_AI
Definition: stm32h723xx.h:9520
#define DMA2D_OCOLR_GREEN_1
Definition: stm32h723xx.h:9624
#define DMA2D_FGCOLR_GREEN
Definition: stm32h723xx.h:9535
#define DMA2D_BGPFCCR_START
Definition: stm32h723xx.h:9554
#define DMA2D_FGPFCCR_CCM
Definition: stm32h723xx.h:9501
#define DMA2D_LWR_LW
Definition: stm32h723xx.h:9696
#define DMA2D_IFCR_CTWIF
Definition: stm32h723xx.h:9455
#define DMA2D_CR_TWIE
Definition: stm32h723xx.h:9407
#define DMA2D_OCOLR_ALPHA_1
Definition: stm32h723xx.h:9630
#define DMA2D_BGPFCCR_AM
Definition: stm32h723xx.h:9560
#define DMA2D_OPFCCR_RBS
Definition: stm32h723xx.h:9613
#define DMA2D_CR_MODE
Definition: stm32h723xx.h:9419
#define DMA2D_OPFCCR_SB
Definition: stm32h723xx.h:9607
#define DMA2D_FGOR_LO
Definition: stm32h723xx.h:9476
#define DMA2D_OPFCCR_CM
Definition: stm32h723xx.h:9601
#define DMA2D_FGPFCCR_CM
Definition: stm32h723xx.h:9494
#define DMA2D_AMTCR_EN
Definition: stm32h723xx.h:9702
#define DMA2D_CR_CAEIE
Definition: stm32h723xx.h:9410
#define DMA2D_CR_LOM
Definition: stm32h723xx.h:9398
#define DMA2D_CR_ABORT
Definition: stm32h723xx.h:9395
#define DMA2D_OCOLR_RED_1
Definition: stm32h723xx.h:9627
#define DMA2D_NLR_PL
Definition: stm32h723xx.h:9690
#define DMA2D_ISR_CAEIF
Definition: stm32h723xx.h:9437
#define DMA2D_ISR_TCIF
Definition: stm32h723xx.h:9431
#define DMA2D_CR_TCIE
Definition: stm32h723xx.h:9404
#define DMA2D_NLR_NL
Definition: stm32h723xx.h:9687
#define DMA2D_OOR_LO
Definition: stm32h723xx.h:9681
CMSIS STM32H7xx Device Peripheral Access Layer Header File.
DMA2D Controller.
Definition: stm32h723xx.h:686
__IO uint32_t ISR
Definition: stm32h723xx.h:688
__IO uint32_t OCOLR
Definition: stm32h723xx.h:701
__IO uint32_t OOR
Definition: stm32h723xx.h:703
__IO uint32_t BGPFCCR
Definition: stm32h723xx.h:696
__IO uint32_t OPFCCR
Definition: stm32h723xx.h:700
__IO uint32_t AMTCR
Definition: stm32h723xx.h:706
__IO uint32_t FGCOLR
Definition: stm32h723xx.h:695
__IO uint32_t BGOR
Definition: stm32h723xx.h:693
__IO uint32_t NLR
Definition: stm32h723xx.h:704
__IO uint32_t FGOR
Definition: stm32h723xx.h:691
__IO uint32_t BGCOLR
Definition: stm32h723xx.h:697
__IO uint32_t LWR
Definition: stm32h723xx.h:705
__IO uint32_t FGPFCCR
Definition: stm32h723xx.h:694
__IO uint32_t IFCR
Definition: stm32h723xx.h:689
__IO uint32_t CR
Definition: stm32h723xx.h:687