RTEMS 6.1-rc4
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stm32h7xx_ll_bdma.h
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1
19/* Define to prevent recursive inclusion -------------------------------------*/
20#ifndef STM32H7xx_LL_BDMA_H
21#define STM32H7xx_LL_BDMA_H
22
23#ifdef __cplusplus
24extern "C" {
25#endif
26
27/* Includes ------------------------------------------------------------------*/
28#include "stm32h7xx.h"
29#include "stm32h7xx_ll_dmamux.h"
30
35#if defined (BDMA) || defined (BDMA1) || defined (BDMA2)
36
42/* Private types -------------------------------------------------------------*/
43/* Private variables ---------------------------------------------------------*/
48/* Array used to get the BDMA channel register offset versus channel index LL_BDMA_CHANNEL_x */
49static const uint8_t LL_BDMA_CH_OFFSET_TAB[] =
50{
51 (uint8_t)(BDMA_Channel0_BASE - BDMA_BASE),
52 (uint8_t)(BDMA_Channel1_BASE - BDMA_BASE),
53 (uint8_t)(BDMA_Channel2_BASE - BDMA_BASE),
54 (uint8_t)(BDMA_Channel3_BASE - BDMA_BASE),
55 (uint8_t)(BDMA_Channel4_BASE - BDMA_BASE),
56 (uint8_t)(BDMA_Channel5_BASE - BDMA_BASE),
57 (uint8_t)(BDMA_Channel6_BASE - BDMA_BASE),
58 (uint8_t)(BDMA_Channel7_BASE - BDMA_BASE)
59};
64/* Private constants ---------------------------------------------------------*/
65/* Private macros ------------------------------------------------------------*/
70#if !defined(UNUSED)
71#define UNUSED(x) ((void)(x))
72#endif
76/* Exported types ------------------------------------------------------------*/
77#if defined(USE_FULL_LL_DRIVER) || defined(__rtems__)
82typedef struct
83{
84 uint32_t PeriphOrM2MSrcAddress;
89 uint32_t MemoryOrM2MDstAddress;
94 uint32_t Direction;
100 uint32_t Mode;
107 uint32_t PeriphOrM2MSrcIncMode;
113 uint32_t MemoryOrM2MDstIncMode;
119 uint32_t PeriphOrM2MSrcDataSize;
125 uint32_t MemoryOrM2MDstDataSize;
131 uint32_t NbData;
138 uint32_t PeriphRequest;
143 uint32_t Priority;
148 uint32_t DoubleBufferMode;
153 uint32_t TargetMemInDoubleBufferMode;
157} LL_BDMA_InitTypeDef;
161#endif /* USE_FULL_LL_DRIVER */
162
163/* Exported constants --------------------------------------------------------*/
173#define LL_BDMA_IFCR_CGIF1 BDMA_IFCR_CGIF1
174#define LL_BDMA_IFCR_CTCIF1 BDMA_IFCR_CTCIF1
175#define LL_BDMA_IFCR_CHTIF1 BDMA_IFCR_CHTIF1
176#define LL_BDMA_IFCR_CTEIF1 BDMA_IFCR_CTEIF1
177#define LL_BDMA_IFCR_CGIF2 BDMA_IFCR_CGIF2
178#define LL_BDMA_IFCR_CTCIF2 BDMA_IFCR_CTCIF2
179#define LL_BDMA_IFCR_CHTIF2 BDMA_IFCR_CHTIF2
180#define LL_BDMA_IFCR_CTEIF2 BDMA_IFCR_CTEIF2
181#define LL_BDMA_IFCR_CGIF3 BDMA_IFCR_CGIF3
182#define LL_BDMA_IFCR_CTCIF3 BDMA_IFCR_CTCIF3
183#define LL_BDMA_IFCR_CHTIF3 BDMA_IFCR_CHTIF3
184#define LL_BDMA_IFCR_CTEIF3 BDMA_IFCR_CTEIF3
185#define LL_BDMA_IFCR_CGIF4 BDMA_IFCR_CGIF4
186#define LL_BDMA_IFCR_CTCIF4 BDMA_IFCR_CTCIF4
187#define LL_BDMA_IFCR_CHTIF4 BDMA_IFCR_CHTIF4
188#define LL_BDMA_IFCR_CTEIF4 BDMA_IFCR_CTEIF4
189#define LL_BDMA_IFCR_CGIF5 BDMA_IFCR_CGIF5
190#define LL_BDMA_IFCR_CTCIF5 BDMA_IFCR_CTCIF5
191#define LL_BDMA_IFCR_CHTIF5 BDMA_IFCR_CHTIF5
192#define LL_BDMA_IFCR_CTEIF5 BDMA_IFCR_CTEIF5
193#define LL_BDMA_IFCR_CGIF6 BDMA_IFCR_CGIF6
194#define LL_BDMA_IFCR_CTCIF6 BDMA_IFCR_CTCIF6
195#define LL_BDMA_IFCR_CHTIF6 BDMA_IFCR_CHTIF6
196#define LL_BDMA_IFCR_CTEIF6 BDMA_IFCR_CTEIF6
197#define LL_BDMA_IFCR_CGIF7 BDMA_IFCR_CGIF7
198#define LL_BDMA_IFCR_CTCIF7 BDMA_IFCR_CTCIF7
199#define LL_BDMA_IFCR_CHTIF7 BDMA_IFCR_CHTIF7
200#define LL_BDMA_IFCR_CTEIF7 BDMA_IFCR_CTEIF7
210#define LL_BDMA_ISR_GIF0 BDMA_ISR_GIF0
211#define LL_BDMA_ISR_TCIF0 BDMA_ISR_TCIF0
212#define LL_BDMA_ISR_HTIF0 BDMA_ISR_HTIF0
213#define LL_BDMA_ISR_TEIF0 BDMA_ISR_TEIF0
214#define LL_BDMA_ISR_GIF1 BDMA_ISR_GIF1
215#define LL_BDMA_ISR_TCIF1 BDMA_ISR_TCIF1
216#define LL_BDMA_ISR_HTIF1 BDMA_ISR_HTIF1
217#define LL_BDMA_ISR_TEIF1 BDMA_ISR_TEIF1
218#define LL_BDMA_ISR_GIF2 BDMA_ISR_GIF2
219#define LL_BDMA_ISR_TCIF2 BDMA_ISR_TCIF2
220#define LL_BDMA_ISR_HTIF2 BDMA_ISR_HTIF2
221#define LL_BDMA_ISR_TEIF2 BDMA_ISR_TEIF2
222#define LL_BDMA_ISR_GIF3 BDMA_ISR_GIF3
223#define LL_BDMA_ISR_TCIF3 BDMA_ISR_TCIF3
224#define LL_BDMA_ISR_HTIF3 BDMA_ISR_HTIF3
225#define LL_BDMA_ISR_TEIF3 BDMA_ISR_TEIF3
226#define LL_BDMA_ISR_GIF4 BDMA_ISR_GIF4
227#define LL_BDMA_ISR_TCIF4 BDMA_ISR_TCIF4
228#define LL_BDMA_ISR_HTIF4 BDMA_ISR_HTIF4
229#define LL_BDMA_ISR_TEIF4 BDMA_ISR_TEIF4
230#define LL_BDMA_ISR_GIF5 BDMA_ISR_GIF5
231#define LL_BDMA_ISR_TCIF5 BDMA_ISR_TCIF5
232#define LL_BDMA_ISR_HTIF5 BDMA_ISR_HTIF5
233#define LL_BDMA_ISR_TEIF5 BDMA_ISR_TEIF5
234#define LL_BDMA_ISR_GIF6 BDMA_ISR_GIF6
235#define LL_BDMA_ISR_TCIF6 BDMA_ISR_TCIF6
236#define LL_BDMA_ISR_HTIF6 BDMA_ISR_HTIF6
237#define LL_BDMA_ISR_TEIF6 BDMA_ISR_TEIF6
238#define LL_BDMA_ISR_GIF7 BDMA_ISR_GIF7
239#define LL_BDMA_ISR_TCIF7 BDMA_ISR_TCIF7
240#define LL_BDMA_ISR_HTIF7 BDMA_ISR_HTIF7
241#define LL_BDMA_ISR_TEIF7 BDMA_ISR_TEIF7
251#define LL_BDMA_CCR_TCIE BDMA_CCR_TCIE
252#define LL_BDMA_CCR_HTIE BDMA_CCR_HTIE
253#define LL_BDMA_CCR_TEIE BDMA_CCR_TEIE
262#define LL_BDMA_CHANNEL_0 0x00000000U
263#define LL_BDMA_CHANNEL_1 0x00000001U
264#define LL_BDMA_CHANNEL_2 0x00000002U
265#define LL_BDMA_CHANNEL_3 0x00000003U
266#define LL_BDMA_CHANNEL_4 0x00000004U
267#define LL_BDMA_CHANNEL_5 0x00000005U
268#define LL_BDMA_CHANNEL_6 0x00000006U
269#define LL_BDMA_CHANNEL_7 0x00000007U
270#if defined(USE_FULL_LL_DRIVER) || defined(__rtems__)
271#define LL_BDMA_CHANNEL_ALL 0xFFFF0000U
272#endif /*USE_FULL_LL_DRIVER*/
281#define LL_BDMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U
282#define LL_BDMA_DIRECTION_MEMORY_TO_PERIPH BDMA_CCR_DIR
283#define LL_BDMA_DIRECTION_MEMORY_TO_MEMORY BDMA_CCR_MEM2MEM
292#define LL_BDMA_MODE_NORMAL 0x00000000U
293#define LL_BDMA_MODE_CIRCULAR BDMA_CCR_CIRC
302#define LL_BDMA_DOUBLEBUFFER_MODE_DISABLE 0x00000000U
303#define LL_BDMA_DOUBLEBUFFER_MODE_ENABLE BDMA_CCR_DBM
311#define LL_BDMA_CURRENTTARGETMEM0 0x00000000U
312#define LL_BDMA_CURRENTTARGETMEM1 BDMA_CCR_CT
321#define LL_BDMA_PERIPH_INCREMENT BDMA_CCR_PINC
322#define LL_BDMA_PERIPH_NOINCREMENT 0x00000000U
331#define LL_BDMA_MEMORY_INCREMENT BDMA_CCR_MINC
332#define LL_BDMA_MEMORY_NOINCREMENT 0x00000000U
341#define LL_BDMA_PDATAALIGN_BYTE 0x00000000U
342#define LL_BDMA_PDATAALIGN_HALFWORD BDMA_CCR_PSIZE_0
343#define LL_BDMA_PDATAALIGN_WORD BDMA_CCR_PSIZE_1
352#define LL_BDMA_MDATAALIGN_BYTE 0x00000000U
353#define LL_BDMA_MDATAALIGN_HALFWORD BDMA_CCR_MSIZE_0
354#define LL_BDMA_MDATAALIGN_WORD BDMA_CCR_MSIZE_1
363#define LL_BDMA_PRIORITY_LOW 0x00000000U
364#define LL_BDMA_PRIORITY_MEDIUM BDMA_CCR_PL_0
365#define LL_BDMA_PRIORITY_HIGH BDMA_CCR_PL_1
366#define LL_BDMA_PRIORITY_VERYHIGH BDMA_CCR_PL
375/* Exported macro ------------------------------------------------------------*/
392#define LL_BDMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
393
400#define LL_BDMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
414#if defined (BDMA1)
415#define __LL_BDMA_GET_INSTANCE(__CHANNEL_INSTANCE__) \
416(((uint32_t)(__CHANNEL_INSTANCE__) < LL_BDMA_CHANNEL_0) ? BDMA1 : BDMA)
417#else
418#define __LL_BDMA_GET_INSTANCE(__CHANNEL_INSTANCE__) (BDMA)
419#endif /* BDMA1 */
420
426#if defined (BDMA1)
427#define __LL_BDMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
428(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel0)) ? LL_BDMA_CHANNEL_0 : \
429 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA1_Channel0)) ? LL_BDMA_CHANNEL_0 : \
430 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel1)) ? LL_BDMA_CHANNEL_1 : \
431 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA1_Channel1)) ? LL_BDMA_CHANNEL_1 : \
432 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel2)) ? LL_BDMA_CHANNEL_2 : \
433 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA1_Channel2)) ? LL_BDMA_CHANNEL_2 : \
434 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel3)) ? LL_BDMA_CHANNEL_3 : \
435 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA1_Channel3)) ? LL_BDMA_CHANNEL_3 : \
436 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel4)) ? LL_BDMA_CHANNEL_4 : \
437 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA1_Channel4)) ? LL_BDMA_CHANNEL_4 : \
438 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel5)) ? LL_BDMA_CHANNEL_5 : \
439 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA1_Channel5)) ? LL_BDMA_CHANNEL_5 : \
440 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel6)) ? LL_BDMA_CHANNEL_6 : \
441 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA1_Channel6)) ? LL_BDMA_CHANNEL_6 : \
442 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel7)) ? LL_BDMA_CHANNEL_7 : \
443LL_BDMA_CHANNEL_7)
444#else
445#define __LL_BDMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
446(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel0)) ? LL_BDMA_CHANNEL_0 : \
447 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel1)) ? LL_BDMA_CHANNEL_1 : \
448 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel2)) ? LL_BDMA_CHANNEL_2 : \
449 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel3)) ? LL_BDMA_CHANNEL_3 : \
450 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel4)) ? LL_BDMA_CHANNEL_4 : \
451 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel5)) ? LL_BDMA_CHANNEL_5 : \
452 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel6)) ? LL_BDMA_CHANNEL_6 : \
453 LL_BDMA_CHANNEL_7)
454#endif /* BDMA1 */
455
462#if defined (BDMA1)
463#define __LL_BDMA_GET_CHANNEL_INSTANCE(__BDMA_INSTANCE__, __CHANNEL__) \
464((((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_0))) ? BDMA_Channel0 : \
465 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_0))) ? BDMA1_Channel0 : \
466 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_1))) ? BDMA_Channel1 : \
467 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_1))) ? BDMA1_Channel1 : \
468 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_2))) ? BDMA_Channel2 : \
469 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_2))) ? BDMA1_Channel2 : \
470 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_3))) ? BDMA_Channel3 : \
471 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_3))) ? BDMA1_Channel3 : \
472 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_4))) ? BDMA_Channel4 : \
473 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_4))) ? BDMA1_Channel4 : \
474 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_5))) ? BDMA_Channel5 : \
475 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_5))) ? BDMA1_Channel5 : \
476 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_6))) ? BDMA_Channel6 : \
477 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_6))) ? BDMA1_Channel6 : \
478 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_7))) ? BDMA_Channel7 : \
479 BDMA1_Channel7)
480#else
481#define __LL_BDMA_GET_CHANNEL_INSTANCE(__BDMA_INSTANCE__, __CHANNEL__) \
482((((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_0))) ? BDMA_Channel0 : \
483 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_1))) ? BDMA_Channel1 : \
484 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_2))) ? BDMA_Channel2 : \
485 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_3))) ? BDMA_Channel3 : \
486 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_4))) ? BDMA_Channel4 : \
487 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_5))) ? BDMA_Channel5 : \
488 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_6))) ? BDMA_Channel6 : \
489 BDMA_Channel7)
490#endif /* BDMA1 */
499/* Exported functions --------------------------------------------------------*/
524__STATIC_INLINE void LL_BDMA_EnableChannel(BDMA_TypeDef *BDMAx, uint32_t Channel)
525{
526 uint32_t bdma_base_addr = (uint32_t)BDMAx;
527
528 SET_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_EN);
529}
530
546__STATIC_INLINE void LL_BDMA_DisableChannel(BDMA_TypeDef *BDMAx, uint32_t Channel)
547{
548 uint32_t bdma_base_addr = (uint32_t)BDMAx;
549
550 CLEAR_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_EN);
551}
552
568__STATIC_INLINE uint32_t LL_BDMA_IsEnabledChannel(BDMA_TypeDef *BDMAx, uint32_t Channel)
569{
570 uint32_t bdma_base_addr = (uint32_t)BDMAx;
571
572 return ((READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_EN) == (BDMA_CCR_EN)) ? 1UL : 0UL);
573}
574
609__STATIC_INLINE void LL_BDMA_ConfigTransfer(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Configuration)
610{
611 uint32_t bdma_base_addr = (uint32_t)BDMAx;
612
613 MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR,
614 BDMA_CCR_DIR | BDMA_CCR_MEM2MEM | BDMA_CCR_CIRC | BDMA_CCR_PINC | BDMA_CCR_MINC | BDMA_CCR_PSIZE | BDMA_CCR_MSIZE | BDMA_CCR_PL | \
615 BDMA_CCR_DBM | BDMA_CCR_CT, Configuration);
616}
617
638__STATIC_INLINE void LL_BDMA_SetDataTransferDirection(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Direction)
639{
640 uint32_t bdma_base_addr = (uint32_t)BDMAx;
641
642 MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR,
643 BDMA_CCR_DIR | BDMA_CCR_MEM2MEM, Direction);
644}
645
665__STATIC_INLINE uint32_t LL_BDMA_GetDataTransferDirection(BDMA_TypeDef *BDMAx, uint32_t Channel)
666{
667 uint32_t bdma_base_addr = (uint32_t)BDMAx;
668
669 return (READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR,
670 BDMA_CCR_DIR | BDMA_CCR_MEM2MEM));
671}
672
693__STATIC_INLINE void LL_BDMA_SetMode(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Mode)
694{
695 uint32_t bdma_base_addr = (uint32_t)BDMAx;
696
697 MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_CIRC,
698 Mode);
699}
700
718__STATIC_INLINE uint32_t LL_BDMA_GetMode(BDMA_TypeDef *BDMAx, uint32_t Channel)
719{
720 uint32_t bdma_base_addr = (uint32_t)BDMAx;
721
722 return (READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR,
723 BDMA_CCR_CIRC));
724}
725
744__STATIC_INLINE void LL_BDMA_SetPeriphIncMode(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode)
745{
746 uint32_t bdma_base_addr = (uint32_t)BDMAx;
747
748 MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_PINC,
749 PeriphOrM2MSrcIncMode);
750}
751
769__STATIC_INLINE uint32_t LL_BDMA_GetPeriphIncMode(BDMA_TypeDef *BDMAx, uint32_t Channel)
770{
771 uint32_t bdma_base_addr = (uint32_t)BDMAx;
772
773 return (READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR,
774 BDMA_CCR_PINC));
775}
776
795__STATIC_INLINE void LL_BDMA_SetMemoryIncMode(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode)
796{
797 uint32_t bdma_base_addr = (uint32_t)BDMAx;
798
799 MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_MINC,
800 MemoryOrM2MDstIncMode);
801}
802
820__STATIC_INLINE uint32_t LL_BDMA_GetMemoryIncMode(BDMA_TypeDef *BDMAx, uint32_t Channel)
821{
822 uint32_t bdma_base_addr = (uint32_t)BDMAx;
823
824 return (READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR,
825 BDMA_CCR_MINC));
826}
827
847__STATIC_INLINE void LL_BDMA_SetPeriphSize(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize)
848{
849 uint32_t bdma_base_addr = (uint32_t)BDMAx;
850
851 MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_PSIZE,
852 PeriphOrM2MSrcDataSize);
853}
854
873__STATIC_INLINE uint32_t LL_BDMA_GetPeriphSize(BDMA_TypeDef *BDMAx, uint32_t Channel)
874{
875 uint32_t bdma_base_addr = (uint32_t)BDMAx;
876
877 return (READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR,
878 BDMA_CCR_PSIZE));
879}
880
900__STATIC_INLINE void LL_BDMA_SetMemorySize(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize)
901{
902 uint32_t bdma_base_addr = (uint32_t)BDMAx;
903
904 MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_MSIZE,
905 MemoryOrM2MDstDataSize);
906}
907
926__STATIC_INLINE uint32_t LL_BDMA_GetMemorySize(BDMA_TypeDef *BDMAx, uint32_t Channel)
927{
928 uint32_t bdma_base_addr = (uint32_t)BDMAx;
929
930 return (READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR,
931 BDMA_CCR_MSIZE));
932}
933
954__STATIC_INLINE void LL_BDMA_SetChannelPriorityLevel(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Priority)
955{
956 uint32_t bdma_base_addr = (uint32_t)BDMAx;
957
958 MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_PL,
959 Priority);
960}
961
981__STATIC_INLINE uint32_t LL_BDMA_GetChannelPriorityLevel(BDMA_TypeDef *BDMAx, uint32_t Channel)
982{
983 uint32_t bdma_base_addr = (uint32_t)BDMAx;
984
985 return (READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR,
986 BDMA_CCR_PL));
987}
988
1007__STATIC_INLINE void LL_BDMA_SetDataLength(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t NbData)
1008{
1009 uint32_t bdma_base_addr = (uint32_t)BDMAx;
1010
1011 MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CNDTR,
1012 BDMA_CNDTR_NDT, NbData);
1013}
1014
1032__STATIC_INLINE uint32_t LL_BDMA_GetDataLength(BDMA_TypeDef *BDMAx, uint32_t Channel)
1033{
1034 uint32_t bdma_base_addr = (uint32_t)BDMAx;
1035
1036 return (READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CNDTR,
1037 BDMA_CNDTR_NDT));
1038}
1039
1058__STATIC_INLINE void LL_BDMA_SetCurrentTargetMem(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t CurrentMemory)
1059{
1060 uint32_t bdma_base_addr = (uint32_t)BDMAx;
1061
1062 MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_CT, CurrentMemory);
1063}
1064
1082__STATIC_INLINE uint32_t LL_BDMA_GetCurrentTargetMem(BDMA_TypeDef *BDMAx, uint32_t Channel)
1083{
1084 uint32_t bdma_base_addr = (uint32_t)BDMAx;
1085
1086 return (READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_CT));
1087}
1088
1104__STATIC_INLINE void LL_BDMA_EnableDoubleBufferMode(BDMA_TypeDef *BDMAx, uint32_t Channel)
1105{
1106 uint32_t bdma_base_addr = (uint32_t)BDMAx;
1107
1108 SET_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_DBM);
1109}
1110
1126__STATIC_INLINE void LL_BDMA_DisableDoubleBufferMode(BDMA_TypeDef *BDMAx, uint32_t Channel)
1127{
1128 uint32_t bdma_base_addr = (uint32_t)BDMAx;
1129
1130 CLEAR_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_DBM);
1131}
1132
1148__STATIC_INLINE uint32_t LL_BDMA_IsEnabledDoubleBufferMode(BDMA_TypeDef *BDMAx, uint32_t Channel)
1149{
1150 register uint32_t bdma_base_addr = (uint32_t)BDMAx;
1151
1152 return ((READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_DBM) == (BDMA_CCR_DBM)) ? 1UL : 0UL);
1153}
1154
1179__STATIC_INLINE void LL_BDMA_ConfigAddresses(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t SrcAddress,
1180 uint32_t DstAddress, uint32_t Direction)
1181{
1182 uint32_t bdma_base_addr = (uint32_t)BDMAx;
1183
1184 /* Direction Memory to Periph */
1185 if (Direction == LL_BDMA_DIRECTION_MEMORY_TO_PERIPH)
1186 {
1187 WRITE_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CM0AR, SrcAddress);
1188 WRITE_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CPAR, DstAddress);
1189 }
1190 /* Direction Periph to Memory and Memory to Memory */
1191 else
1192 {
1193 WRITE_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CPAR, SrcAddress);
1194 WRITE_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CM0AR, DstAddress);
1195 }
1196}
1197
1216__STATIC_INLINE void LL_BDMA_SetMemoryAddress(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t MemoryAddress)
1217{
1218 uint32_t bdma_base_addr = (uint32_t)BDMAx;
1219
1220 WRITE_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CM0AR, MemoryAddress);
1221}
1222
1241__STATIC_INLINE void LL_BDMA_SetPeriphAddress(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t PeriphAddress)
1242{
1243 uint32_t bdma_base_addr = (uint32_t)BDMAx;
1244
1245 WRITE_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CPAR, PeriphAddress);
1246}
1247
1264__STATIC_INLINE uint32_t LL_BDMA_GetMemoryAddress(BDMA_TypeDef *BDMAx, uint32_t Channel)
1265{
1266 uint32_t bdma_base_addr = (uint32_t)BDMAx;
1267
1268 return (READ_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CM0AR));
1269}
1270
1287__STATIC_INLINE uint32_t LL_BDMA_GetPeriphAddress(BDMA_TypeDef *BDMAx, uint32_t Channel)
1288{
1289 uint32_t bdma_base_addr = (uint32_t)BDMAx;
1290
1291 return (READ_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CPAR));
1292}
1293
1312__STATIC_INLINE void LL_BDMA_SetM2MSrcAddress(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t MemoryAddress)
1313{
1314 uint32_t bdma_base_addr = (uint32_t)BDMAx;
1315
1316 WRITE_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CPAR, MemoryAddress);
1317}
1318
1337__STATIC_INLINE void LL_BDMA_SetM2MDstAddress(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t MemoryAddress)
1338{
1339 uint32_t bdma_base_addr = (uint32_t)BDMAx;
1340
1341 WRITE_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CM0AR, MemoryAddress);
1342}
1343
1360__STATIC_INLINE uint32_t LL_BDMA_GetM2MSrcAddress(BDMA_TypeDef *BDMAx, uint32_t Channel)
1361{
1362 uint32_t bdma_base_addr = (uint32_t)BDMAx;
1363
1364 return (READ_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CPAR));
1365}
1366
1383__STATIC_INLINE uint32_t LL_BDMA_GetM2MDstAddress(BDMA_TypeDef *BDMAx, uint32_t Channel)
1384{
1385 uint32_t bdma_base_addr = (uint32_t)BDMAx;
1386
1387 return (READ_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CM0AR));
1388}
1389
1406__STATIC_INLINE void LL_BDMA_SetMemory1Address(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Address)
1407{
1408 uint32_t bdma_base_addr = (uint32_t)BDMAx;
1409
1410 MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CM1AR, BDMA_CM1AR_MA, Address);
1411}
1412
1428__STATIC_INLINE uint32_t LL_BDMA_GetMemory1Address(BDMA_TypeDef *BDMAx, uint32_t Channel)
1429{
1430 uint32_t bdma_base_addr = (uint32_t)BDMAx;
1431
1432 return (((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CM1AR);
1433}
1434
1474__STATIC_INLINE void LL_BDMA_SetPeriphRequest(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Request)
1475{
1476 UNUSED(BDMAx);
1477 MODIFY_REG(((DMAMUX_Channel_TypeDef *)(uint32_t)((uint32_t)DMAMUX2_Channel0 + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_DMAREQ_ID, Request);
1478}
1479
1518__STATIC_INLINE uint32_t LL_BDMA_GetPeriphRequest(BDMA_TypeDef *BDMAx, uint32_t Channel)
1519{
1520 UNUSED(BDMAx);
1521 return (READ_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)((uint32_t)DMAMUX2_Channel0 + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, DMAMUX_CxCR_DMAREQ_ID));
1522}
1523
1539__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI0(BDMA_TypeDef *BDMAx)
1540{
1541 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_GIF0) == (BDMA_ISR_GIF0)) ? 1UL : 0UL);
1542}
1543
1550__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI1(BDMA_TypeDef *BDMAx)
1551{
1552 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_GIF1) == (BDMA_ISR_GIF1)) ? 1UL : 0UL);
1553}
1554
1561__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI2(BDMA_TypeDef *BDMAx)
1562{
1563 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_GIF2) == (BDMA_ISR_GIF2)) ? 1UL : 0UL);
1564}
1565
1572__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI3(BDMA_TypeDef *BDMAx)
1573{
1574 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_GIF3) == (BDMA_ISR_GIF3)) ? 1UL : 0UL);
1575}
1576
1583__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI4(BDMA_TypeDef *BDMAx)
1584{
1585 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_GIF4) == (BDMA_ISR_GIF4)) ? 1UL : 0UL);
1586}
1587
1594__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI5(BDMA_TypeDef *BDMAx)
1595{
1596 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_GIF5) == (BDMA_ISR_GIF5)) ? 1UL : 0UL);
1597}
1598
1605__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI6(BDMA_TypeDef *BDMAx)
1606{
1607 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_GIF6) == (BDMA_ISR_GIF6)) ? 1UL : 0UL);
1608}
1609
1616__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI7(BDMA_TypeDef *BDMAx)
1617{
1618 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_GIF7) == (BDMA_ISR_GIF7)) ? 1UL : 0UL);
1619}
1620
1627__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC0(BDMA_TypeDef *BDMAx)
1628{
1629 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TCIF0) == (BDMA_ISR_TCIF0)) ? 1UL : 0UL);
1630}
1637__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC1(BDMA_TypeDef *BDMAx)
1638{
1639 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TCIF1) == (BDMA_ISR_TCIF1)) ? 1UL : 0UL);
1640}
1641
1648__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC2(BDMA_TypeDef *BDMAx)
1649{
1650 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TCIF2) == (BDMA_ISR_TCIF2)) ? 1UL : 0UL);
1651}
1652
1659__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC3(BDMA_TypeDef *BDMAx)
1660{
1661 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TCIF3) == (BDMA_ISR_TCIF3)) ? 1UL : 0UL);
1662}
1663
1670__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC4(BDMA_TypeDef *BDMAx)
1671{
1672 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TCIF4) == (BDMA_ISR_TCIF4)) ? 1UL : 0UL);
1673}
1674
1681__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC5(BDMA_TypeDef *BDMAx)
1682{
1683 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TCIF5) == (BDMA_ISR_TCIF5)) ? 1UL : 0UL);
1684}
1685
1692__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC6(BDMA_TypeDef *BDMAx)
1693{
1694 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TCIF6) == (BDMA_ISR_TCIF6)) ? 1UL : 0UL);
1695}
1696
1703__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC7(BDMA_TypeDef *BDMAx)
1704{
1705 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TCIF7) == (BDMA_ISR_TCIF7)) ? 1UL : 0UL);
1706}
1707
1714__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT0(BDMA_TypeDef *BDMAx)
1715{
1716 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_HTIF0) == (BDMA_ISR_HTIF0)) ? 1UL : 0UL);
1717}
1718
1725__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT1(BDMA_TypeDef *BDMAx)
1726{
1727 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_HTIF1) == (BDMA_ISR_HTIF1)) ? 1UL : 0UL);
1728}
1729
1736__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT2(BDMA_TypeDef *BDMAx)
1737{
1738 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_HTIF2) == (BDMA_ISR_HTIF2)) ? 1UL : 0UL);
1739}
1740
1747__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT3(BDMA_TypeDef *BDMAx)
1748{
1749 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_HTIF3) == (BDMA_ISR_HTIF3)) ? 1UL : 0UL);
1750}
1751
1758__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT4(BDMA_TypeDef *BDMAx)
1759{
1760 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_HTIF4) == (BDMA_ISR_HTIF4)) ? 1UL : 0UL);
1761}
1762
1769__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT5(BDMA_TypeDef *BDMAx)
1770{
1771 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_HTIF5) == (BDMA_ISR_HTIF5)) ? 1UL : 0UL);
1772}
1773
1780__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT6(BDMA_TypeDef *BDMAx)
1781{
1782 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_HTIF6) == (BDMA_ISR_HTIF6)) ? 1UL : 0UL);
1783}
1784
1791__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT7(BDMA_TypeDef *BDMAx)
1792{
1793 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_HTIF7) == (BDMA_ISR_HTIF7)) ? 1UL : 0UL);
1794}
1795
1802__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE0(BDMA_TypeDef *BDMAx)
1803{
1804 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TEIF0) == (BDMA_ISR_TEIF0)) ? 1UL : 0UL);
1805}
1806
1813__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE1(BDMA_TypeDef *BDMAx)
1814{
1815 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TEIF1) == (BDMA_ISR_TEIF1)) ? 1UL : 0UL);
1816}
1817
1824__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE2(BDMA_TypeDef *BDMAx)
1825{
1826 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TEIF2) == (BDMA_ISR_TEIF2)) ? 1UL : 0UL);
1827}
1828
1835__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE3(BDMA_TypeDef *BDMAx)
1836{
1837 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TEIF3) == (BDMA_ISR_TEIF3)) ? 1UL : 0UL);
1838}
1839
1846__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE4(BDMA_TypeDef *BDMAx)
1847{
1848 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TEIF4) == (BDMA_ISR_TEIF4)) ? 1UL : 0UL);
1849}
1850
1857__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE5(BDMA_TypeDef *BDMAx)
1858{
1859 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TEIF5) == (BDMA_ISR_TEIF5)) ? 1UL : 0UL);
1860}
1861
1868__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE6(BDMA_TypeDef *BDMAx)
1869{
1870 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TEIF6) == (BDMA_ISR_TEIF6)) ? 1UL : 0UL);
1871}
1872
1879__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE7(BDMA_TypeDef *BDMAx)
1880{
1881 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TEIF7) == (BDMA_ISR_TEIF7)) ? 1UL : 0UL);
1882}
1883
1894__STATIC_INLINE void LL_BDMA_ClearFlag_GI0(BDMA_TypeDef *BDMAx)
1895{
1896 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CGIF0);
1897}
1898
1909__STATIC_INLINE void LL_BDMA_ClearFlag_GI1(BDMA_TypeDef *BDMAx)
1910{
1911 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CGIF1);
1912}
1913
1924__STATIC_INLINE void LL_BDMA_ClearFlag_GI2(BDMA_TypeDef *BDMAx)
1925{
1926 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CGIF2);
1927}
1928
1939__STATIC_INLINE void LL_BDMA_ClearFlag_GI3(BDMA_TypeDef *BDMAx)
1940{
1941 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CGIF3);
1942}
1943
1954__STATIC_INLINE void LL_BDMA_ClearFlag_GI4(BDMA_TypeDef *BDMAx)
1955{
1956 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CGIF4);
1957}
1958
1969__STATIC_INLINE void LL_BDMA_ClearFlag_GI5(BDMA_TypeDef *BDMAx)
1970{
1971 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CGIF5);
1972}
1973
1984__STATIC_INLINE void LL_BDMA_ClearFlag_GI6(BDMA_TypeDef *BDMAx)
1985{
1986 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CGIF6);
1987}
1988
1999__STATIC_INLINE void LL_BDMA_ClearFlag_GI7(BDMA_TypeDef *BDMAx)
2000{
2001 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CGIF7);
2002}
2003
2010__STATIC_INLINE void LL_BDMA_ClearFlag_TC0(BDMA_TypeDef *BDMAx)
2011{
2012 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTCIF0);
2013}
2014
2021__STATIC_INLINE void LL_BDMA_ClearFlag_TC1(BDMA_TypeDef *BDMAx)
2022{
2023 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTCIF1);
2024}
2025
2032__STATIC_INLINE void LL_BDMA_ClearFlag_TC2(BDMA_TypeDef *BDMAx)
2033{
2034 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTCIF2);
2035}
2036
2043__STATIC_INLINE void LL_BDMA_ClearFlag_TC3(BDMA_TypeDef *BDMAx)
2044{
2045 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTCIF3);
2046}
2047
2054__STATIC_INLINE void LL_BDMA_ClearFlag_TC4(BDMA_TypeDef *BDMAx)
2055{
2056 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTCIF4);
2057}
2058
2065__STATIC_INLINE void LL_BDMA_ClearFlag_TC5(BDMA_TypeDef *BDMAx)
2066{
2067 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTCIF5);
2068}
2069
2076__STATIC_INLINE void LL_BDMA_ClearFlag_TC6(BDMA_TypeDef *BDMAx)
2077{
2078 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTCIF6);
2079}
2080
2087__STATIC_INLINE void LL_BDMA_ClearFlag_TC7(BDMA_TypeDef *BDMAx)
2088{
2089 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTCIF7);
2090}
2091
2098__STATIC_INLINE void LL_BDMA_ClearFlag_HT0(BDMA_TypeDef *BDMAx)
2099{
2100 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CHTIF0);
2101}
2102
2109__STATIC_INLINE void LL_BDMA_ClearFlag_HT1(BDMA_TypeDef *BDMAx)
2110{
2111 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CHTIF1);
2112}
2113
2120__STATIC_INLINE void LL_BDMA_ClearFlag_HT2(BDMA_TypeDef *BDMAx)
2121{
2122 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CHTIF2);
2123}
2124
2131__STATIC_INLINE void LL_BDMA_ClearFlag_HT3(BDMA_TypeDef *BDMAx)
2132{
2133 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CHTIF3);
2134}
2135
2142__STATIC_INLINE void LL_BDMA_ClearFlag_HT4(BDMA_TypeDef *BDMAx)
2143{
2144 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CHTIF4);
2145}
2146
2153__STATIC_INLINE void LL_BDMA_ClearFlag_HT5(BDMA_TypeDef *BDMAx)
2154{
2155 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CHTIF5);
2156}
2157
2164__STATIC_INLINE void LL_BDMA_ClearFlag_HT6(BDMA_TypeDef *BDMAx)
2165{
2166 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CHTIF6);
2167}
2168
2175__STATIC_INLINE void LL_BDMA_ClearFlag_HT7(BDMA_TypeDef *BDMAx)
2176{
2177 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CHTIF7);
2178}
2179
2186__STATIC_INLINE void LL_BDMA_ClearFlag_TE0(BDMA_TypeDef *BDMAx)
2187{
2188 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTEIF0);
2189}
2190
2197__STATIC_INLINE void LL_BDMA_ClearFlag_TE1(BDMA_TypeDef *BDMAx)
2198{
2199 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTEIF1);
2200}
2201
2208__STATIC_INLINE void LL_BDMA_ClearFlag_TE2(BDMA_TypeDef *BDMAx)
2209{
2210 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTEIF2);
2211}
2212
2219__STATIC_INLINE void LL_BDMA_ClearFlag_TE3(BDMA_TypeDef *BDMAx)
2220{
2221 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTEIF3);
2222}
2223
2230__STATIC_INLINE void LL_BDMA_ClearFlag_TE4(BDMA_TypeDef *BDMAx)
2231{
2232 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTEIF4);
2233}
2234
2241__STATIC_INLINE void LL_BDMA_ClearFlag_TE5(BDMA_TypeDef *BDMAx)
2242{
2243 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTEIF5);
2244}
2245
2252__STATIC_INLINE void LL_BDMA_ClearFlag_TE6(BDMA_TypeDef *BDMAx)
2253{
2254 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTEIF6);
2255}
2256
2263__STATIC_INLINE void LL_BDMA_ClearFlag_TE7(BDMA_TypeDef *BDMAx)
2264{
2265 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTEIF7);
2266}
2267
2291__STATIC_INLINE void LL_BDMA_EnableIT_TC(BDMA_TypeDef *BDMAx, uint32_t Channel)
2292{
2293 uint32_t bdma_base_addr = (uint32_t)BDMAx;
2294
2295 SET_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_TCIE);
2296}
2297
2313__STATIC_INLINE void LL_BDMA_EnableIT_HT(BDMA_TypeDef *BDMAx, uint32_t Channel)
2314{
2315 uint32_t bdma_base_addr = (uint32_t)BDMAx;
2316
2317 SET_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_HTIE);
2318}
2319
2335__STATIC_INLINE void LL_BDMA_EnableIT_TE(BDMA_TypeDef *BDMAx, uint32_t Channel)
2336{
2337 uint32_t bdma_base_addr = (uint32_t)BDMAx;
2338
2339 SET_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_TEIE);
2340}
2341
2357__STATIC_INLINE void LL_BDMA_DisableIT_TC(BDMA_TypeDef *BDMAx, uint32_t Channel)
2358{
2359 uint32_t bdma_base_addr = (uint32_t)BDMAx;
2360
2361 CLEAR_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_TCIE);
2362}
2363
2379__STATIC_INLINE void LL_BDMA_DisableIT_HT(BDMA_TypeDef *BDMAx, uint32_t Channel)
2380{
2381 uint32_t bdma_base_addr = (uint32_t)BDMAx;
2382
2383 CLEAR_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_HTIE);
2384}
2385
2401__STATIC_INLINE void LL_BDMA_DisableIT_TE(BDMA_TypeDef *BDMAx, uint32_t Channel)
2402{
2403 uint32_t bdma_base_addr = (uint32_t)BDMAx;
2404
2405 CLEAR_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_TEIE);
2406}
2407
2423__STATIC_INLINE uint32_t LL_BDMA_IsEnabledIT_TC(BDMA_TypeDef *BDMAx, uint32_t Channel)
2424{
2425 uint32_t bdma_base_addr = (uint32_t)BDMAx;
2426
2427 return ((READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_TCIE) == (BDMA_CCR_TCIE)) ? 1UL : 0UL);
2428}
2429
2445__STATIC_INLINE uint32_t LL_BDMA_IsEnabledIT_HT(BDMA_TypeDef *BDMAx, uint32_t Channel)
2446{
2447 uint32_t bdma_base_addr = (uint32_t)BDMAx;
2448
2449 return ((READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_HTIE) == (BDMA_CCR_HTIE)) ? 1UL : 0UL);
2450}
2451
2467__STATIC_INLINE uint32_t LL_BDMA_IsEnabledIT_TE(BDMA_TypeDef *BDMAx, uint32_t Channel)
2468{
2469 uint32_t bdma_base_addr = (uint32_t)BDMAx;
2470
2471 return ((READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_TEIE) == (BDMA_CCR_TEIE)) ? 1UL : 0UL);
2472}
2473
2478#if defined(USE_FULL_LL_DRIVER) || defined(__rtems__)
2484uint32_t LL_BDMA_Init(BDMA_TypeDef *BDMAx, uint32_t Channel, LL_BDMA_InitTypeDef *BDMA_InitStruct);
2485uint32_t LL_BDMA_DeInit(BDMA_TypeDef *BDMAx, uint32_t Channel);
2486void LL_BDMA_StructInit(LL_BDMA_InitTypeDef *BDMA_InitStruct);
2487
2491#endif /* USE_FULL_LL_DRIVER */
2492
2501#endif /* BDMA || BDMA1 || BDMA2 */
2506#ifdef __cplusplus
2507}
2508#endif
2509
2510#endif /* STM32H7xx_LL_BDMA_H */
2511
BDMA_ISR_HTIF1
#define BDMA_ISR_HTIF1
Definition: stm32h723xx.h:6657
BDMA_ISR_HTIF5
#define BDMA_ISR_HTIF5
Definition: stm32h723xx.h:6705
BDMA_ISR_GIF2
#define BDMA_ISR_GIF2
Definition: stm32h723xx.h:6663
BDMA_IFCR_CTEIF2
#define BDMA_IFCR_CTEIF2
Definition: stm32h723xx.h:6770
BDMA_IFCR_CGIF6
#define BDMA_IFCR_CGIF6
Definition: stm32h723xx.h:6809
BDMA_IFCR_CTCIF6
#define BDMA_IFCR_CTCIF6
Definition: stm32h723xx.h:6812
BDMA_CCR_MEM2MEM
#define BDMA_CCR_MEM2MEM
Definition: stm32h723xx.h:6878
BDMA_ISR_TCIF2
#define BDMA_ISR_TCIF2
Definition: stm32h723xx.h:6666
BDMA_CCR_MINC
#define BDMA_CCR_MINC
Definition: stm32h723xx.h:6856
BDMA_CCR_PL
#define BDMA_CCR_PL
Definition: stm32h723xx.h:6872
BDMA_CCR_TCIE
#define BDMA_CCR_TCIE
Definition: stm32h723xx.h:6838
BDMA_CM1AR_MA
#define BDMA_CM1AR_MA
Definition: stm32h723xx.h:6904
BDMA_IFCR_CTCIF0
#define BDMA_IFCR_CTCIF0
Definition: stm32h723xx.h:6740
BDMA_CCR_EN
#define BDMA_CCR_EN
Definition: stm32h723xx.h:6835
BDMA_ISR_TCIF1
#define BDMA_ISR_TCIF1
Definition: stm32h723xx.h:6654
BDMA_ISR_GIF6
#define BDMA_ISR_GIF6
Definition: stm32h723xx.h:6711
BDMA_IFCR_CHTIF3
#define BDMA_IFCR_CHTIF3
Definition: stm32h723xx.h:6779
BDMA_ISR_HTIF6
#define BDMA_ISR_HTIF6
Definition: stm32h723xx.h:6717
BDMA_ISR_HTIF2
#define BDMA_ISR_HTIF2
Definition: stm32h723xx.h:6669
BDMA_ISR_TEIF5
#define BDMA_ISR_TEIF5
Definition: stm32h723xx.h:6708
DMAMUX_CxCR_DMAREQ_ID
#define DMAMUX_CxCR_DMAREQ_ID
Definition: stm32h723xx.h:9158
BDMA_ISR_TCIF6
#define BDMA_ISR_TCIF6
Definition: stm32h723xx.h:6714
BDMA_IFCR_CTEIF6
#define BDMA_IFCR_CTEIF6
Definition: stm32h723xx.h:6818
BDMA_ISR_TCIF0
#define BDMA_ISR_TCIF0
Definition: stm32h723xx.h:6642
BDMA_ISR_TEIF3
#define BDMA_ISR_TEIF3
Definition: stm32h723xx.h:6684
BDMA_ISR_TEIF7
#define BDMA_ISR_TEIF7
Definition: stm32h723xx.h:6732
BDMA_ISR_TEIF0
#define BDMA_ISR_TEIF0
Definition: stm32h723xx.h:6648
BDMA_IFCR_CTCIF1
#define BDMA_IFCR_CTCIF1
Definition: stm32h723xx.h:6752
BDMA_ISR_GIF0
#define BDMA_ISR_GIF0
Definition: stm32h723xx.h:6639
BDMA_ISR_HTIF0
#define BDMA_ISR_HTIF0
Definition: stm32h723xx.h:6645
BDMA_IFCR_CHTIF4
#define BDMA_IFCR_CHTIF4
Definition: stm32h723xx.h:6791
BDMA_IFCR_CTCIF4
#define BDMA_IFCR_CTCIF4
Definition: stm32h723xx.h:6788
BDMA_CNDTR_NDT
#define BDMA_CNDTR_NDT
Definition: stm32h723xx.h:6889
BDMA_IFCR_CTCIF5
#define BDMA_IFCR_CTCIF5
Definition: stm32h723xx.h:6800
BDMA_IFCR_CGIF2
#define BDMA_IFCR_CGIF2
Definition: stm32h723xx.h:6761
BDMA_IFCR_CGIF0
#define BDMA_IFCR_CGIF0
Definition: stm32h723xx.h:6737
BDMA_ISR_TCIF4
#define BDMA_ISR_TCIF4
Definition: stm32h723xx.h:6690
BDMA_IFCR_CTEIF3
#define BDMA_IFCR_CTEIF3
Definition: stm32h723xx.h:6782
BDMA_ISR_TEIF4
#define BDMA_ISR_TEIF4
Definition: stm32h723xx.h:6696
BDMA_IFCR_CTEIF4
#define BDMA_IFCR_CTEIF4
Definition: stm32h723xx.h:6794
BDMA_IFCR_CHTIF0
#define BDMA_IFCR_CHTIF0
Definition: stm32h723xx.h:6743
BDMA_CCR_HTIE
#define BDMA_CCR_HTIE
Definition: stm32h723xx.h:6841
BDMA_CCR_MSIZE
#define BDMA_CCR_MSIZE
Definition: stm32h723xx.h:6866
BDMA_IFCR_CTEIF5
#define BDMA_IFCR_CTEIF5
Definition: stm32h723xx.h:6806
BDMA_ISR_GIF4
#define BDMA_ISR_GIF4
Definition: stm32h723xx.h:6687
BDMA_CCR_DBM
#define BDMA_CCR_DBM
Definition: stm32h723xx.h:6881
BDMA_IFCR_CGIF1
#define BDMA_IFCR_CGIF1
Definition: stm32h723xx.h:6749
BDMA_ISR_TCIF5
#define BDMA_ISR_TCIF5
Definition: stm32h723xx.h:6702
BDMA_CCR_CIRC
#define BDMA_CCR_CIRC
Definition: stm32h723xx.h:6850
BDMA_IFCR_CHTIF6
#define BDMA_IFCR_CHTIF6
Definition: stm32h723xx.h:6815
BDMA_ISR_GIF7
#define BDMA_ISR_GIF7
Definition: stm32h723xx.h:6723
BDMA_IFCR_CTEIF0
#define BDMA_IFCR_CTEIF0
Definition: stm32h723xx.h:6746
BDMA_ISR_HTIF7
#define BDMA_ISR_HTIF7
Definition: stm32h723xx.h:6729
BDMA_ISR_HTIF3
#define BDMA_ISR_HTIF3
Definition: stm32h723xx.h:6681
BDMA_IFCR_CHTIF7
#define BDMA_IFCR_CHTIF7
Definition: stm32h723xx.h:6827
BDMA_CCR_PINC
#define BDMA_CCR_PINC
Definition: stm32h723xx.h:6853
BDMA_IFCR_CGIF7
#define BDMA_IFCR_CGIF7
Definition: stm32h723xx.h:6821
BDMA_IFCR_CHTIF5
#define BDMA_IFCR_CHTIF5
Definition: stm32h723xx.h:6803
BDMA_ISR_HTIF4
#define BDMA_ISR_HTIF4
Definition: stm32h723xx.h:6693
BDMA_IFCR_CTEIF1
#define BDMA_IFCR_CTEIF1
Definition: stm32h723xx.h:6758
BDMA_ISR_GIF1
#define BDMA_ISR_GIF1
Definition: stm32h723xx.h:6651
BDMA_ISR_GIF5
#define BDMA_ISR_GIF5
Definition: stm32h723xx.h:6699
BDMA_IFCR_CTEIF7
#define BDMA_IFCR_CTEIF7
Definition: stm32h723xx.h:6830
BDMA_CCR_CT
#define BDMA_CCR_CT
Definition: stm32h723xx.h:6884
BDMA_IFCR_CHTIF1
#define BDMA_IFCR_CHTIF1
Definition: stm32h723xx.h:6755
BDMA_CCR_PSIZE
#define BDMA_CCR_PSIZE
Definition: stm32h723xx.h:6860
BDMA_IFCR_CTCIF7
#define BDMA_IFCR_CTCIF7
Definition: stm32h723xx.h:6824
BDMA_CCR_DIR
#define BDMA_CCR_DIR
Definition: stm32h723xx.h:6847
BDMA_IFCR_CTCIF2
#define BDMA_IFCR_CTCIF2
Definition: stm32h723xx.h:6764
BDMA_ISR_TEIF1
#define BDMA_ISR_TEIF1
Definition: stm32h723xx.h:6660
BDMA_IFCR_CGIF4
#define BDMA_IFCR_CGIF4
Definition: stm32h723xx.h:6785
BDMA_IFCR_CGIF5
#define BDMA_IFCR_CGIF5
Definition: stm32h723xx.h:6797
BDMA_ISR_TEIF6
#define BDMA_ISR_TEIF6
Definition: stm32h723xx.h:6720
BDMA_CCR_TEIE
#define BDMA_CCR_TEIE
Definition: stm32h723xx.h:6844
BDMA_IFCR_CGIF3
#define BDMA_IFCR_CGIF3
Definition: stm32h723xx.h:6773
BDMA_ISR_TCIF3
#define BDMA_ISR_TCIF3
Definition: stm32h723xx.h:6678
BDMA_ISR_TEIF2
#define BDMA_ISR_TEIF2
Definition: stm32h723xx.h:6672
BDMA_IFCR_CHTIF2
#define BDMA_IFCR_CHTIF2
Definition: stm32h723xx.h:6767
BDMA_ISR_TCIF7
#define BDMA_ISR_TCIF7
Definition: stm32h723xx.h:6726
BDMA_ISR_GIF3
#define BDMA_ISR_GIF3
Definition: stm32h723xx.h:6675
BDMA_IFCR_CTCIF3
#define BDMA_IFCR_CTCIF3
Definition: stm32h723xx.h:6776
stm32h7xx.h
CMSIS STM32H7xx Device Peripheral Access Layer Header File.
stm32h7xx_ll_dmamux.h
Header file of DMAMUX LL module.
BDMA_Channel_TypeDef
Definition: stm32h723xx.h:619
BDMA_TypeDef
Definition: stm32h723xx.h:628
BDMA_TypeDef::ISR
__IO uint32_t ISR
Definition: stm32h723xx.h:629
BDMA_TypeDef::IFCR
__IO uint32_t IFCR
Definition: stm32h723xx.h:630
DMAMUX_Channel_TypeDef
Definition: stm32h723xx.h:634
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