RTEMS 6.1-rc4
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stm32h7xx_ll_adc.h
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1
19/* Define to prevent recursive inclusion -------------------------------------*/
20#ifndef STM32H7xx_LL_ADC_H
21#define STM32H7xx_LL_ADC_H
22
23#ifdef __cplusplus
24extern "C" {
25#endif
26
27/* Includes ------------------------------------------------------------------*/
28#include "stm32h7xx.h"
29
34#if defined (ADC1) || defined (ADC2) || defined (ADC3)
35
41/* Private types -------------------------------------------------------------*/
42/* Private variables ---------------------------------------------------------*/
43
44/* Private constants ---------------------------------------------------------*/
50/* Internal mask for ADC calibration: */
51/* Internal register offset for ADC calibration factors configuration */
52
53/* To select into literals LL_ADC_CALIB_OFFSET, LL_ADC_CALIB_LINEARITY, ... */
54/* the relevant bits for: */
55/* (concatenation of multiple bits used in different registers) */
56/* - ADC calibration configuration: configuration before calibration start */
57/* - ADC calibration factors: register offset */
58#define ADC_CALIB_FACTOR_OFFSET_REGOFFSET (0x00000000UL) /* Register CALFACT defined as reference register */
59#define ADC_CALIB_FACTOR_LINEARITY_REGOFFSET (0x00000001UL) /* Register CALFACT2 offset vs register CALFACT */
60#define ADC_CALIB_FACTOR_REGOFFSET_MASK (ADC_CALIB_FACTOR_OFFSET_REGOFFSET | ADC_CALIB_FACTOR_LINEARITY_REGOFFSET)
61#define ADC_CALIB_MODE_MASK (ADC_CR_ADCALLIN)
62#define ADC_CALIB_MODE_BINARY_MASK (ADC_CALIB_FACTOR_REGOFFSET_MASK) /* Mask to get binary value of calibration mode: 0 for offset, 1 for linearity */
63
64
65/* Internal mask for ADC group regular sequencer: */
66/* To select into literal LL_ADC_REG_RANK_x the relevant bits for: */
67/* - sequencer register offset */
68/* - sequencer rank bits position into the selected register */
69
70/* Internal register offset for ADC group regular sequencer configuration */
71/* (offset placed into a spare area of literal definition) */
72#define ADC_SQR1_REGOFFSET (0x00000000UL)
73#define ADC_SQR2_REGOFFSET (0x00000100UL)
74#define ADC_SQR3_REGOFFSET (0x00000200UL)
75#define ADC_SQR4_REGOFFSET (0x00000300UL)
76
77#define ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET)
78#define ADC_SQRX_REGOFFSET_POS (8UL) /* Position of bits ADC_SQRx_REGOFFSET in ADC_REG_SQRX_REGOFFSET_MASK */
79#define ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
80
81/* Definition of ADC group regular sequencer bits information to be inserted */
82/* into ADC group regular sequencer ranks literals definition. */
83#define ADC_REG_RANK_1_SQRX_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_SQR1_SQ1" position in register */
84#define ADC_REG_RANK_2_SQRX_BITOFFSET_POS (12UL) /* Value equivalent to bitfield "ADC_SQR1_SQ2" position in register */
85#define ADC_REG_RANK_3_SQRX_BITOFFSET_POS (18UL) /* Value equivalent to bitfield "ADC_SQR1_SQ3" position in register */
86#define ADC_REG_RANK_4_SQRX_BITOFFSET_POS (24UL) /* Value equivalent to bitfield "ADC_SQR1_SQ4" position in register */
87#define ADC_REG_RANK_5_SQRX_BITOFFSET_POS ( 0UL) /* Value equivalent to bitfield "ADC_SQR2_SQ5" position in register */
88#define ADC_REG_RANK_6_SQRX_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_SQR2_SQ6" position in register */
89#define ADC_REG_RANK_7_SQRX_BITOFFSET_POS (12UL) /* Value equivalent to bitfield "ADC_SQR2_SQ7" position in register */
90#define ADC_REG_RANK_8_SQRX_BITOFFSET_POS (18UL) /* Value equivalent to bitfield "ADC_SQR2_SQ8" position in register */
91#define ADC_REG_RANK_9_SQRX_BITOFFSET_POS (24UL) /* Value equivalent to bitfield "ADC_SQR2_SQ9" position in register */
92#define ADC_REG_RANK_10_SQRX_BITOFFSET_POS ( 0UL) /* Value equivalent to bitfield "ADC_SQR3_SQ10" position in register */
93#define ADC_REG_RANK_11_SQRX_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_SQR3_SQ11" position in register */
94#define ADC_REG_RANK_12_SQRX_BITOFFSET_POS (12UL) /* Value equivalent to bitfield "ADC_SQR3_SQ12" position in register */
95#define ADC_REG_RANK_13_SQRX_BITOFFSET_POS (18UL) /* Value equivalent to bitfield "ADC_SQR3_SQ13" position in register */
96#define ADC_REG_RANK_14_SQRX_BITOFFSET_POS (24UL) /* Value equivalent to bitfield "ADC_SQR3_SQ14" position in register */
97#define ADC_REG_RANK_15_SQRX_BITOFFSET_POS ( 0UL) /* Value equivalent to bitfield "ADC_SQR4_SQ15" position in register */
98#define ADC_REG_RANK_16_SQRX_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_SQR4_SQ16" position in register */
99
100
101
102/* Internal mask for ADC group injected sequencer: */
103/* To select into literal LL_ADC_INJ_RANK_x the relevant bits for: */
104/* - data register offset */
105/* - sequencer rank bits position into the selected register */
106
107/* Internal register offset for ADC group injected data register */
108/* (offset placed into a spare area of literal definition) */
109#define ADC_JDR1_REGOFFSET (0x00000000UL)
110#define ADC_JDR2_REGOFFSET (0x00000100UL)
111#define ADC_JDR3_REGOFFSET (0x00000200UL)
112#define ADC_JDR4_REGOFFSET (0x00000300UL)
113
114#define ADC_INJ_JDRX_REGOFFSET_MASK (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET)
115#define ADC_INJ_RANK_ID_JSQR_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
116#define ADC_JDRX_REGOFFSET_POS (8UL) /* Position of bits ADC_JDRx_REGOFFSET in ADC_INJ_JDRX_REGOFFSET_MASK */
117
118/* Definition of ADC group injected sequencer bits information to be inserted */
119/* into ADC group injected sequencer ranks literals definition. */
120#define ADC_INJ_RANK_1_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ1_Pos)
121#define ADC_INJ_RANK_2_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ2_Pos)
122#define ADC_INJ_RANK_3_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ3_Pos)
123#define ADC_INJ_RANK_4_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ4_Pos)
124
125
126
127/* Internal mask for ADC group regular trigger: */
128/* To select into literal LL_ADC_REG_TRIG_x the relevant bits for: */
129/* - regular trigger source */
130/* - regular trigger edge */
131#define ADC_REG_TRIG_EXT_EDGE_DEFAULT (ADC_CFGR_EXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
132
133/* Mask containing trigger source masks for each of possible */
134/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
135/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
136#define ADC_REG_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTSEL) << (4U * 0UL)) | \
137 ((ADC_CFGR_EXTSEL) << (4U * 1UL)) | \
138 ((ADC_CFGR_EXTSEL) << (4U * 2UL)) | \
139 ((ADC_CFGR_EXTSEL) << (4U * 3UL)) )
140
141/* Mask containing trigger edge masks for each of possible */
142/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
143/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
144#define ADC_REG_TRIG_EDGE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN) << (4U * 0UL)) | \
145 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 1UL)) | \
146 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 2UL)) | \
147 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 3UL)) )
148
149/* Definition of ADC group regular trigger bits information. */
150#define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_CFGR_EXTSEL" position in register */
151#define ADC_REG_TRIG_EXTEN_BITOFFSET_POS (10UL) /* Value equivalent to bitfield "ADC_CFGR_EXTEN" position in register */
152
153
154
155/* Internal mask for ADC group injected trigger: */
156/* To select into literal LL_ADC_INJ_TRIG_x the relevant bits for: */
157/* - injected trigger source */
158/* - injected trigger edge */
159#define ADC_INJ_TRIG_EXT_EDGE_DEFAULT (ADC_JSQR_JEXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
160
161/* Mask containing trigger source masks for each of possible */
162/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
163/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
164#define ADC_INJ_TRIG_SOURCE_MASK (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTSEL) << (4U * 0UL)) | \
165 ((ADC_JSQR_JEXTSEL) << (4U * 1UL)) | \
166 ((ADC_JSQR_JEXTSEL) << (4U * 2UL)) | \
167 ((ADC_JSQR_JEXTSEL) << (4U * 3UL)) )
168
169/* Mask containing trigger edge masks for each of possible */
170/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
171/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
172#define ADC_INJ_TRIG_EDGE_MASK (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN) << (4U * 0UL)) | \
173 ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 1UL)) | \
174 ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 2UL)) | \
175 ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 3UL)) )
176
177/* Definition of ADC group injected trigger bits information. */
178#define ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS ( 2UL) /* Value equivalent to bitfield "ADC_JSQR_JEXTSEL" position in register */
179#define ADC_INJ_TRIG_EXTEN_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_JSQR_JEXTEN" position in register */
180
181
182
183
184
185
186/* Internal mask for ADC channel: */
187/* To select into literal LL_ADC_CHANNEL_x the relevant bits for: */
188/* - channel identifier defined by number */
189/* - channel identifier defined by bitfield */
190/* - channel differentiation between external channels (connected to */
191/* GPIO pins) and internal channels (connected to internal paths) */
192/* - channel sampling time defined by SMPRx register offset */
193/* and SMPx bits positions into SMPRx register */
194#define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CFGR_AWD1CH)
195#define ADC_CHANNEL_ID_BITFIELD_MASK (ADC_AWD2CR_AWD2CH)
196#define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS (26UL)/* Value equivalent to bitfield "ADC_CHANNEL_ID_NUMBER_MASK" position in register */
197#define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_BITFIELD_MASK | ADC_CHANNEL_ID_INTERNAL_CH_MASK)
198/* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */
199#define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 (ADC_SQR2_SQ5) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> [Position of bitfield "ADC_CHANNEL_NUMBER_MASK" in register]) */
200
201/* Channel differentiation between external and internal channels */
202#define ADC_CHANNEL_ID_INTERNAL_CH (0x80000000UL) /* Marker of internal channel */
203#define ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH)
204
205/* Internal register offset for ADC channel sampling time configuration */
206/* (offset placed into a spare area of literal definition) */
207#define ADC_SMPR1_REGOFFSET (0x00000000UL)
208#define ADC_SMPR2_REGOFFSET (0x02000000UL)
209#define ADC_CHANNEL_SMPRX_REGOFFSET_MASK (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET)
210#define ADC_SMPRX_REGOFFSET_POS (25UL) /* Position of bits ADC_SMPRx_REGOFFSET in ADC_CHANNEL_SMPRX_REGOFFSET_MASK */
211
212#define ADC_CHANNEL_SMPx_BITOFFSET_MASK (0x01F00000UL)
213#define ADC_CHANNEL_SMPx_BITOFFSET_POS (20UL) /* Value equivalent to bitfield "ADC_CHANNEL_SMPx_BITOFFSET_MASK" position in register */
214
215/* Definition of channels ID number information to be inserted into */
216/* channels literals definition. */
217#define ADC_CHANNEL_0_NUMBER (0x00000000UL)
218#define ADC_CHANNEL_1_NUMBER ( ADC_CFGR_AWD1CH_0)
219#define ADC_CHANNEL_2_NUMBER ( ADC_CFGR_AWD1CH_1 )
220#define ADC_CHANNEL_3_NUMBER ( ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
221#define ADC_CHANNEL_4_NUMBER ( ADC_CFGR_AWD1CH_2 )
222#define ADC_CHANNEL_5_NUMBER ( ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0)
223#define ADC_CHANNEL_6_NUMBER ( ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 )
224#define ADC_CHANNEL_7_NUMBER ( ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
225#define ADC_CHANNEL_8_NUMBER ( ADC_CFGR_AWD1CH_3 )
226#define ADC_CHANNEL_9_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_0)
227#define ADC_CHANNEL_10_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1 )
228#define ADC_CHANNEL_11_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
229#define ADC_CHANNEL_12_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 )
230#define ADC_CHANNEL_13_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0)
231#define ADC_CHANNEL_14_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 )
232#define ADC_CHANNEL_15_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
233#define ADC_CHANNEL_16_NUMBER (ADC_CFGR_AWD1CH_4 )
234#define ADC_CHANNEL_17_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_0)
235#define ADC_CHANNEL_18_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_1 )
236#define ADC_CHANNEL_19_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
237
238/* Definition of channels ID bitfield information to be inserted into */
239/* channels literals definition. */
240#define ADC_CHANNEL_0_BITFIELD (ADC_AWD2CR_AWD2CH_0)
241#define ADC_CHANNEL_1_BITFIELD (ADC_AWD2CR_AWD2CH_1)
242#define ADC_CHANNEL_2_BITFIELD (ADC_AWD2CR_AWD2CH_2)
243#define ADC_CHANNEL_3_BITFIELD (ADC_AWD2CR_AWD2CH_3)
244#define ADC_CHANNEL_4_BITFIELD (ADC_AWD2CR_AWD2CH_4)
245#define ADC_CHANNEL_5_BITFIELD (ADC_AWD2CR_AWD2CH_5)
246#define ADC_CHANNEL_6_BITFIELD (ADC_AWD2CR_AWD2CH_6)
247#define ADC_CHANNEL_7_BITFIELD (ADC_AWD2CR_AWD2CH_7)
248#define ADC_CHANNEL_8_BITFIELD (ADC_AWD2CR_AWD2CH_8)
249#define ADC_CHANNEL_9_BITFIELD (ADC_AWD2CR_AWD2CH_9)
250#define ADC_CHANNEL_10_BITFIELD (ADC_AWD2CR_AWD2CH_10)
251#define ADC_CHANNEL_11_BITFIELD (ADC_AWD2CR_AWD2CH_11)
252#define ADC_CHANNEL_12_BITFIELD (ADC_AWD2CR_AWD2CH_12)
253#define ADC_CHANNEL_13_BITFIELD (ADC_AWD2CR_AWD2CH_13)
254#define ADC_CHANNEL_14_BITFIELD (ADC_AWD2CR_AWD2CH_14)
255#define ADC_CHANNEL_15_BITFIELD (ADC_AWD2CR_AWD2CH_15)
256#define ADC_CHANNEL_16_BITFIELD (ADC_AWD2CR_AWD2CH_16)
257#define ADC_CHANNEL_17_BITFIELD (ADC_AWD2CR_AWD2CH_17)
258#define ADC_CHANNEL_18_BITFIELD (ADC_AWD2CR_AWD2CH_18)
259#define ADC_CHANNEL_19_BITFIELD (ADC_AWD2CR_AWD2CH_19)
260
261/* Definition of channels sampling time information to be inserted into */
262/* channels literals definition. */
263#define ADC_CHANNEL_0_SMP (ADC_SMPR1_REGOFFSET | (( 0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP0" position in register */
264#define ADC_CHANNEL_1_SMP (ADC_SMPR1_REGOFFSET | (( 3UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP1" position in register */
265#define ADC_CHANNEL_2_SMP (ADC_SMPR1_REGOFFSET | (( 6UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP2" position in register */
266#define ADC_CHANNEL_3_SMP (ADC_SMPR1_REGOFFSET | (( 9UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP3" position in register */
267#define ADC_CHANNEL_4_SMP (ADC_SMPR1_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP4" position in register */
268#define ADC_CHANNEL_5_SMP (ADC_SMPR1_REGOFFSET | ((15UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP5" position in register */
269#define ADC_CHANNEL_6_SMP (ADC_SMPR1_REGOFFSET | ((18UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP6" position in register */
270#define ADC_CHANNEL_7_SMP (ADC_SMPR1_REGOFFSET | ((21UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP7" position in register */
271#define ADC_CHANNEL_8_SMP (ADC_SMPR1_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP8" position in register */
272#define ADC_CHANNEL_9_SMP (ADC_SMPR1_REGOFFSET | ((27UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP9" position in register */
273#define ADC_CHANNEL_10_SMP (ADC_SMPR2_REGOFFSET | (( 0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP10" position in register */
274#define ADC_CHANNEL_11_SMP (ADC_SMPR2_REGOFFSET | (( 3UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP11" position in register */
275#define ADC_CHANNEL_12_SMP (ADC_SMPR2_REGOFFSET | (( 6UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP12" position in register */
276#define ADC_CHANNEL_13_SMP (ADC_SMPR2_REGOFFSET | (( 9UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP13" position in register */
277#define ADC_CHANNEL_14_SMP (ADC_SMPR2_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP14" position in register */
278#define ADC_CHANNEL_15_SMP (ADC_SMPR2_REGOFFSET | ((15UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP15" position in register */
279#define ADC_CHANNEL_16_SMP (ADC_SMPR2_REGOFFSET | ((18UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP16" position in register */
280#define ADC_CHANNEL_17_SMP (ADC_SMPR2_REGOFFSET | ((21UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP17" position in register */
281#define ADC_CHANNEL_18_SMP (ADC_SMPR2_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP18" position in register */
282#define ADC_CHANNEL_19_SMP (ADC_SMPR2_REGOFFSET | ((27UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP19" position in register */
283
284
285/* Internal mask for ADC mode single or differential ended: */
286/* To select into literals LL_ADC_SINGLE_ENDED or LL_ADC_SINGLE_DIFFERENTIAL */
287/* the relevant bits for: */
288/* (concatenation of multiple bits used in different registers) */
289/* - ADC calibration: calibration start, calibration factor get or set */
290/* - ADC channels: set each ADC channel ending mode */
291#define ADC_SINGLEDIFF_CALIB_START_MASK (ADC_CR_ADCALDIF)
292#define ADC_SINGLEDIFF_CALIB_FACTOR_MASK (ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S)
293#define ADC_SINGLEDIFF_CHANNEL_MASK (ADC_CHANNEL_ID_BITFIELD_MASK) /* Equivalent to ADC_DIFSEL_DIFSEL */
294#define ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK (ADC_CALFACT_CALFACT_S_4 | ADC_CALFACT_CALFACT_S_3) /* Bits chosen to perform of shift when single mode is selected, shift value out of channels bits range. */
295#define ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK (0x00010000UL) /* Selection of 1 bit to discriminate differential mode: mask of bit */
296#define ADC_SINGLEDIFF_CALIB_F_BIT_D_POS (16UL) /* Selection of 1 bit to discriminate differential mode: position of bit */
297#define ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4 (ADC_SINGLEDIFF_CALIB_F_BIT_D_POS - 4UL) /* Shift of bit ADC_SINGLEDIFF_CALIB_F_BIT_D to position to perform a shift of 4 ranks */
298
299/* Internal mask for ADC analog watchdog: */
300/* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for: */
301/* (concatenation of multiple bits used in different analog watchdogs, */
302/* (feature of several watchdogs not available on all STM32 families)). */
303/* - analog watchdog 1: monitored channel defined by number, */
304/* selection of ADC group (ADC groups regular and-or injected). */
305/* - analog watchdog 2 and 3: monitored channel defined by bitfield, no */
306/* selection on groups. */
307
308/* Internal register offset for ADC analog watchdog channel configuration */
309#define ADC_AWD_CR1_REGOFFSET (0x00000000UL)
310#define ADC_AWD_CR2_REGOFFSET (0x00100000UL)
311#define ADC_AWD_CR3_REGOFFSET (0x00200000UL)
312
313/* Register offset gap between AWD1 and AWD2-AWD3 configuration registers */
314/* (Set separately as ADC_AWD_CRX_REGOFFSET to spare 32 bits space */
315#define ADC_AWD_CR12_REGOFFSETGAP_MASK (ADC_AWD2CR_AWD2CH_0)
316#define ADC_AWD_CR12_REGOFFSETGAP_VAL (0x00000024UL)
317
318#define ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET | ADC_AWD_CR2_REGOFFSET | ADC_AWD_CR3_REGOFFSET)
319
320#define ADC_AWD_CR1_CHANNEL_MASK (ADC_CFGR_AWD1CH | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
321#define ADC_AWD_CR23_CHANNEL_MASK (ADC_AWD2CR_AWD2CH)
322#define ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR23_CHANNEL_MASK)
323
324#define ADC_AWD_CRX_REGOFFSET_POS (20UL) /* Position of bits ADC_AWD_CRx_REGOFFSET in ADC_AWD_CRX_REGOFFSET_MASK */
325
326/* Internal register offset for ADC analog watchdog threshold configuration */
327#define ADC_AWD_TR1_REGOFFSET (ADC_AWD_CR1_REGOFFSET)
328#define ADC_AWD_TR2_REGOFFSET (ADC_AWD_CR2_REGOFFSET)
329#define ADC_AWD_TR3_REGOFFSET (ADC_AWD_CR3_REGOFFSET)
330#define ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_REGOFFSET | ADC_AWD_TR2_REGOFFSET | ADC_AWD_TR3_REGOFFSET)
331#define ADC_AWD_TRX_REGOFFSET_POS (ADC_AWD_CRX_REGOFFSET_POS) /* Position of bits ADC_TRx_REGOFFSET in ADC_AWD_TRX_REGOFFSET_MASK */
332#if defined(ADC_VER_V5_V90)
333#define ADC_AWD_TRX_BIT_HIGH_MASK (0x00010000UL) /* Selection of 1 bit to discriminate threshold high: mask of bit */
334#define ADC_AWD_TRX_BIT_HIGH_POS (16UL) /* Selection of 1 bit to discriminate threshold high: position of bit */
335#define ADC_AWD_TRX_BIT_HIGH_SHIFT4 (ADC_AWD_TRX_BIT_HIGH_POS - 4UL) /* Shift of bit ADC_AWD_TRX_BIT_HIGH to position to perform a shift of 4 ranks */
336#endif /* ADC_VER_V5_V90 */
337
338/* Register offset gap between AWD1 and AWD2-AWD3 thresholds registers */
339/* (Set separately as ADC_AWD_TRX_REGOFFSET to spare 32 bits space */
340#define ADC_AWD_TR12_REGOFFSETGAP_MASK (ADC_AWD2CR_AWD2CH_0)
341#define ADC_AWD_TR12_REGOFFSETGAP_VAL (0x00000022UL)
342
343/* Legacy literals */
344#define LL_ADC_AWD1_TR LL_ADC_AWD1
345#define LL_ADC_AWD2_TR LL_ADC_AWD2
346#define LL_ADC_AWD3_TR LL_ADC_AWD3
347
348/* Internal mask for ADC offset: */
349/* Internal register offset for ADC offset number configuration */
350#define ADC_OFR1_REGOFFSET (0x00000000UL)
351#define ADC_OFR2_REGOFFSET (0x00000001UL)
352#define ADC_OFR3_REGOFFSET (0x00000002UL)
353#define ADC_OFR4_REGOFFSET (0x00000003UL)
354#define ADC_OFRx_REGOFFSET_MASK (ADC_OFR1_REGOFFSET | ADC_OFR2_REGOFFSET | ADC_OFR3_REGOFFSET | ADC_OFR4_REGOFFSET)
355
356
357/* ADC registers bits positions */
358#define ADC_CFGR_RES_BITOFFSET_POS (ADC_CFGR_RES_Pos)
359#define ADC_CFGR_AWD1SGL_BITOFFSET_POS (ADC_CFGR_AWD1SGL_Pos)
360#define ADC_CFGR_AWD1EN_BITOFFSET_POS (ADC_CFGR_AWD1EN_Pos)
361#define ADC_CFGR_JAWD1EN_BITOFFSET_POS (ADC_CFGR_JAWD1EN_Pos)
362#if defined(ADC_VER_V5_V90)
363#define ADC_CFGR_RES_BITOFFSET_POS_ADC3 (ADC3_CFGR_RES_Pos)
364#endif /* ADC_VER_V5_V90 */
365
366
367/* ADC registers bits groups */
368#define ADC_CR_BITS_PROPERTY_RS (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN) /* ADC register CR bits with HW property "rs": Software can read as well as set this bit. Writing '0' has no effect on the bit value. */
369
370
371/* ADC internal channels related definitions */
372/* Internal voltage reference VrefInt */
373#if defined(ADC_VER_V5_3)
374#define VREFINT_CAL_ADDR ((uint16_t*) (0x8fff810UL)) /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
375 /* Address related to STM32H7A3 */
376#else /* ADC_VER_V5_90 || ADC_VER_V5_X */
377#define VREFINT_CAL_ADDR ((uint16_t*) (0x1FF1E860UL)) /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
378#endif /* ADC_VER_V5_3 */
379#define VREFINT_CAL_VREF (3300UL) /* Analog voltage reference (Vref+) value with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */
380/* Temperature sensor */
381#if defined(ADC_VER_V5_3)
382#define TEMPSENSOR_CAL1_ADDR ((uint16_t*) (0x8fff814UL)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32H7, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
383#define TEMPSENSOR_CAL2_ADDR ((uint16_t*) (0x8fff818UL)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32H7, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
384 /* Addresses related to STM32H7A3 */
385#else /* ADC_VER_V5_90 || ADC_VER_V5_X */
386#define TEMPSENSOR_CAL1_ADDR ((uint16_t*) (0x1FF1E820UL)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32H7, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
387#define TEMPSENSOR_CAL2_ADDR ((uint16_t*) (0x1FF1E840UL)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32H7, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
388#endif /* ADC_VER_V5_3 */
389
390#define TEMPSENSOR_CAL1_TEMP (30L) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */
391#if defined (STM32H742xx) || defined (STM32H743xx) || defined (STM32H753xx)
392#define TEMPSENSOR_CAL2_TEMP ((((DBGMCU->IDCODE) >> 16) <= ((uint32_t)0x1003)) ? 110L : 130L) /* Internal temperature sensor ,
393 temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR
394 110 °C for revision Y and 130 °C for revision V (tolerance: +-5 DegC) (unit: DegC). */
395#else
396#define TEMPSENSOR_CAL2_TEMP (110L) /* Internal temperature sensor, temperature at which temperature sensor has been
397 calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */
398#endif /* defined (STM32H742xx) || defined (STM32H743xx) || defined (STM32H753xx) */
399#define TEMPSENSOR_CAL_VREFANALOG (3300UL) /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */
400
401/* Registers addresses with ADC linearity calibration content (programmed during device production, specific to each device) */
402#define ADC_LINEAR_CALIB_REG_1_ADDR ((uint32_t*) (0x1FF1EC00UL))
403#define ADC_LINEAR_CALIB_REG_2_ADDR ((uint32_t*) (0x1FF1EC04UL))
404#define ADC_LINEAR_CALIB_REG_3_ADDR ((uint32_t*) (0x1FF1EC08UL))
405#define ADC_LINEAR_CALIB_REG_4_ADDR ((uint32_t*) (0x1FF1EC0CUL))
406#define ADC_LINEAR_CALIB_REG_5_ADDR ((uint32_t*) (0x1FF1EC10UL))
407#define ADC_LINEAR_CALIB_REG_6_ADDR ((uint32_t*) (0x1FF1EC14UL))
408#define ADC_LINEAR_CALIB_REG_COUNT (6UL)
417#define LL_ADC_SetChannelPreSelection LL_ADC_SetChannelPreselection /* Alias of LL_ADC_SetChannelPreselection for backward compatibility. */
418
423/* Private macros ------------------------------------------------------------*/
437#define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
438 ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))
439
445/* Exported types ------------------------------------------------------------*/
446#if defined(USE_FULL_LL_DRIVER) || defined(__rtems__)
462typedef struct
463{
464 uint32_t CommonClock;
472 uint32_t Multimode;
477 uint32_t MultiDMATransfer;
482 uint32_t MultiTwoSamplingDelay;
487} LL_ADC_CommonInitTypeDef;
488
509typedef struct
510{
511 uint32_t Resolution;
516 uint32_t LeftBitShift;
519 uint32_t LowPowerMode;
524} LL_ADC_InitTypeDef;
525
545typedef struct
546{
547 uint32_t TriggerSource;
555 uint32_t SequencerLength;
560 uint32_t SequencerDiscont;
567 uint32_t ContinuousMode;
573 uint32_t DataTransferMode;
578 uint32_t Overrun;
584} LL_ADC_REG_InitTypeDef;
585
605typedef struct
606{
607 uint32_t TriggerSource;
615 uint32_t SequencerLength;
620 uint32_t SequencerDiscont;
627 uint32_t TrigAuto;
633} LL_ADC_INJ_InitTypeDef;
634
638#endif /* USE_FULL_LL_DRIVER */
639
640/* Exported constants --------------------------------------------------------*/
651#define LL_ADC_FLAG_ADRDY ADC_ISR_ADRDY
652#define LL_ADC_FLAG_EOC ADC_ISR_EOC
653#define LL_ADC_FLAG_EOS ADC_ISR_EOS
654#define LL_ADC_FLAG_OVR ADC_ISR_OVR
655#define LL_ADC_FLAG_EOSMP ADC_ISR_EOSMP
656#define LL_ADC_FLAG_JEOC ADC_ISR_JEOC
657#define LL_ADC_FLAG_JEOS ADC_ISR_JEOS
658#define LL_ADC_FLAG_JQOVF ADC_ISR_JQOVF
659#define LL_ADC_FLAG_AWD1 ADC_ISR_AWD1
660#define LL_ADC_FLAG_AWD2 ADC_ISR_AWD2
661#define LL_ADC_FLAG_AWD3 ADC_ISR_AWD3
662#define LL_ADC_FLAG_LDORDY ADC_ISR_LDORDY
663#define LL_ADC_FLAG_ADRDY_MST ADC_CSR_ADRDY_MST
664#define LL_ADC_FLAG_ADRDY_SLV ADC_CSR_ADRDY_SLV
665#define LL_ADC_FLAG_EOC_MST ADC_CSR_EOC_MST
666#define LL_ADC_FLAG_EOC_SLV ADC_CSR_EOC_SLV
667#define LL_ADC_FLAG_EOS_MST ADC_CSR_EOS_MST
668#define LL_ADC_FLAG_EOS_SLV ADC_CSR_EOS_SLV
669#define LL_ADC_FLAG_OVR_MST ADC_CSR_OVR_MST
670#define LL_ADC_FLAG_OVR_SLV ADC_CSR_OVR_SLV
671#define LL_ADC_FLAG_EOSMP_MST ADC_CSR_EOSMP_MST
672#define LL_ADC_FLAG_EOSMP_SLV ADC_CSR_EOSMP_SLV
673#define LL_ADC_FLAG_JEOC_MST ADC_CSR_JEOC_MST
674#define LL_ADC_FLAG_JEOC_SLV ADC_CSR_JEOC_SLV
675#define LL_ADC_FLAG_JEOS_MST ADC_CSR_JEOS_MST
676#define LL_ADC_FLAG_JEOS_SLV ADC_CSR_JEOS_SLV
677#define LL_ADC_FLAG_JQOVF_MST ADC_CSR_JQOVF_MST
678#define LL_ADC_FLAG_JQOVF_SLV ADC_CSR_JQOVF_SLV
679#define LL_ADC_FLAG_AWD1_MST ADC_CSR_AWD1_MST
680#define LL_ADC_FLAG_AWD1_SLV ADC_CSR_AWD1_SLV
681#define LL_ADC_FLAG_AWD2_MST ADC_CSR_AWD2_MST
682#define LL_ADC_FLAG_AWD2_SLV ADC_CSR_AWD2_SLV
683#define LL_ADC_FLAG_AWD3_MST ADC_CSR_AWD3_MST
684#define LL_ADC_FLAG_AWD3_SLV ADC_CSR_AWD3_SLV
694#define LL_ADC_IT_ADRDY ADC_IER_ADRDYIE
695#define LL_ADC_IT_EOC ADC_IER_EOCIE
696#define LL_ADC_IT_EOS ADC_IER_EOSIE
697#define LL_ADC_IT_OVR ADC_IER_OVRIE
698#define LL_ADC_IT_EOSMP ADC_IER_EOSMPIE
699#define LL_ADC_IT_JEOC ADC_IER_JEOCIE
700#define LL_ADC_IT_JEOS ADC_IER_JEOSIE
701#define LL_ADC_IT_JQOVF ADC_IER_JQOVFIE
702#define LL_ADC_IT_AWD1 ADC_IER_AWD1IE
703#define LL_ADC_IT_AWD2 ADC_IER_AWD2IE
704#define LL_ADC_IT_AWD3 ADC_IER_AWD3IE
713/* List of ADC registers intended to be used (most commonly) with */
714/* DMA transfer. */
715/* Refer to function @ref LL_ADC_DMA_GetRegAddr(). */
716#define LL_ADC_DMA_REG_REGULAR_DATA (0x00000000UL) /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */
717#define LL_ADC_DMA_REG_REGULAR_DATA_MULTI (0x00000001UL) /* ADC group regular conversion data register (corresponding to register CDR) to be used with ADC configured in multimode (available on STM32 devices with several ADC instances). Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadMultiConversionData32() */
726#define LL_ADC_CLOCK_SYNC_PCLK_DIV1 (ADC_CCR_CKMODE_0)
727#define LL_ADC_CLOCK_SYNC_PCLK_DIV2 (ADC_CCR_CKMODE_1 )
728#define LL_ADC_CLOCK_SYNC_PCLK_DIV4 (ADC_CCR_CKMODE_1 | ADC_CCR_CKMODE_0)
729#define LL_ADC_CLOCK_ASYNC_DIV1 (0x00000000UL)
730#define LL_ADC_CLOCK_ASYNC_DIV2 (ADC_CCR_PRESC_0)
731#define LL_ADC_CLOCK_ASYNC_DIV4 (ADC_CCR_PRESC_1 )
732#define LL_ADC_CLOCK_ASYNC_DIV6 (ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0)
733#define LL_ADC_CLOCK_ASYNC_DIV8 (ADC_CCR_PRESC_2 )
734#define LL_ADC_CLOCK_ASYNC_DIV10 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_0)
735#define LL_ADC_CLOCK_ASYNC_DIV12 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 )
736#define LL_ADC_CLOCK_ASYNC_DIV16 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0)
737#define LL_ADC_CLOCK_ASYNC_DIV32 (ADC_CCR_PRESC_3)
738#define LL_ADC_CLOCK_ASYNC_DIV64 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_0)
739#define LL_ADC_CLOCK_ASYNC_DIV128 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1)
740#define LL_ADC_CLOCK_ASYNC_DIV256 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0)
749/* Note: Other measurement paths to internal channels may be available */
750/* (connections to other peripherals). */
751/* If they are not listed below, they do not require any specific */
752/* path enable. In this case, Access to measurement path is done */
753/* only by selecting the corresponding ADC internal channel. */
754#define LL_ADC_PATH_INTERNAL_NONE (0x00000000UL)
755#define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_VREFEN)
756#define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_TSEN)
757#define LL_ADC_PATH_INTERNAL_VBAT (ADC_CCR_VBATEN)
766#define LL_ADC_BOOST_MODE_6MHZ25 (0x00000000UL)
767#define LL_ADC_BOOST_MODE_12MHZ5 ( ADC_CR_BOOST_0)
768#define LL_ADC_BOOST_MODE_20MHZ ( ADC_CR_BOOST_1 )
769#define LL_ADC_BOOST_MODE_25MHZ ((ADC_CR_BOOST_0 <<2) | ADC_CR_BOOST_1 )
770#define LL_ADC_BOOST_MODE_50MHZ ((ADC_CR_BOOST_0 <<2) | ADC_CR_BOOST_1 | ADC_CR_BOOST_0)
779#define LL_ADC_CALIB_OFFSET (ADC_CALIB_FACTOR_OFFSET_REGOFFSET)
780#define LL_ADC_CALIB_LINEARITY (ADC_CALIB_FACTOR_LINEARITY_REGOFFSET)
781#define LL_ADC_CALIB_OFFSET_LINEARITY (ADC_CALIB_FACTOR_LINEARITY_REGOFFSET | ADC_CR_ADCALLIN)
790#define LL_ADC_CALIB_LINEARITY_WORD1 (ADC_CR_LINCALRDYW1)
791#define LL_ADC_CALIB_LINEARITY_WORD2 (ADC_CR_LINCALRDYW2)
792#define LL_ADC_CALIB_LINEARITY_WORD3 (ADC_CR_LINCALRDYW3)
793#define LL_ADC_CALIB_LINEARITY_WORD4 (ADC_CR_LINCALRDYW4)
794#define LL_ADC_CALIB_LINEARITY_WORD5 (ADC_CR_LINCALRDYW5)
795#define LL_ADC_CALIB_LINEARITY_WORD6 (ADC_CR_LINCALRDYW6)
804#define LL_ADC_RESOLUTION_16B (0x00000000UL)
805#define LL_ADC_RESOLUTION_14B ( ADC_CFGR_RES_0)
806#define LL_ADC_RESOLUTION_12B ( ADC_CFGR_RES_1 )
807#define LL_ADC_RESOLUTION_10B ( ADC_CFGR_RES_1 | ADC_CFGR_RES_0)
809#if defined (ADC_VER_V5_X)
810#define LL_ADC_RESOLUTION_14B_OPT (ADC_CFGR_RES_2 | ADC_CFGR_RES_0)
811#define LL_ADC_RESOLUTION_12B_OPT (ADC_CFGR_RES_2 | ADC_CFGR_RES_1 )
812#endif
813
814#if defined (ADC_VER_V5_3) || defined(ADC_VER_V5_V90)
815#define LL_ADC_RESOLUTION_8B (ADC_CFGR_RES_2|ADC_CFGR_RES_1 | ADC_CFGR_RES_0)
816#else
817#define LL_ADC_RESOLUTION_8B (ADC_CFGR_RES_2 )
821#endif
822#if defined(ADC_VER_V5_V90)
823#define LL_ADC_RESOLUTION_6B (ADC3_CFGR_RES_1 | ADC3_CFGR_RES_0)
824#endif /* ADC_VER_V5_V90 */
829#if defined(ADC_VER_V5_V90)
834#define LL_ADC_DATA_ALIGN_RIGHT (0x00000000UL)
835#define LL_ADC_DATA_ALIGN_LEFT (ADC3_CFGR_ALIGN)
840#endif /* ADC_VER_V5_V90 */
841
846#define LL_ADC_LEFT_BIT_SHIFT_NONE (0x00000000UL)
847#define LL_ADC_LEFT_BIT_SHIFT_1 (ADC_CFGR2_LSHIFT_0)
848#define LL_ADC_LEFT_BIT_SHIFT_2 (ADC_CFGR2_LSHIFT_1)
849#define LL_ADC_LEFT_BIT_SHIFT_3 (ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0)
850#define LL_ADC_LEFT_BIT_SHIFT_4 (ADC_CFGR2_LSHIFT_2)
851#define LL_ADC_LEFT_BIT_SHIFT_5 (ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_0)
852#define LL_ADC_LEFT_BIT_SHIFT_6 (ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1)
853#define LL_ADC_LEFT_BIT_SHIFT_7 (ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0)
854#define LL_ADC_LEFT_BIT_SHIFT_8 (ADC_CFGR2_LSHIFT_3)
855#define LL_ADC_LEFT_BIT_SHIFT_9 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_0)
856#define LL_ADC_LEFT_BIT_SHIFT_10 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_1)
857#define LL_ADC_LEFT_BIT_SHIFT_11 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0)
858#define LL_ADC_LEFT_BIT_SHIFT_12 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2)
859#define LL_ADC_LEFT_BIT_SHIFT_13 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_0)
860#define LL_ADC_LEFT_BIT_SHIFT_14 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1)
861#define LL_ADC_LEFT_BIT_SHIFT_15 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0)
870#define LL_ADC_LP_MODE_NONE (0x00000000UL)
871#define LL_ADC_LP_AUTOWAIT (ADC_CFGR_AUTDLY)
880#define LL_ADC_OFFSET_1 ADC_OFR1_REGOFFSET
881#define LL_ADC_OFFSET_2 ADC_OFR2_REGOFFSET
882#define LL_ADC_OFFSET_3 ADC_OFR3_REGOFFSET
883#define LL_ADC_OFFSET_4 ADC_OFR4_REGOFFSET
892#define LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE (0x00000000UL)
893#define LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE (ADC_OFR1_SSATE)
902#define LL_ADC_OFFSET_RSHIFT_DISABLE (0x00000000UL)
903#define LL_ADC_OFFSET_RSHIFT_ENABLE (ADC_CFGR2_RSHIFT1)
907#if defined(ADC_VER_V5_V90)
912#define LL_ADC_OFFSET_SATURATION_DISABLE (0x00000000UL)
913#define LL_ADC_OFFSET_SATURATION_ENABLE (ADC3_OFR1_SATEN)
922#define LL_ADC_OFFSET_DISABLE (0x00000000UL)
923#define LL_ADC_OFFSET_ENABLE (ADC3_OFR1_OFFSET1_EN)
927#if defined(ADC_VER_V5_V90)
932#define LL_ADC_OFFSET_SIGN_NEGATIVE (0x00000000UL)
933#define LL_ADC_OFFSET_SIGN_POSITIVE (ADC3_OFR1_OFFSETPOS)
937#endif /* ADC_VER_V5_V90 */
938
939#endif /* ADC_VER_V5_V90 */
940
945#define LL_ADC_GROUP_REGULAR (0x00000001UL)
946#define LL_ADC_GROUP_INJECTED (0x00000002UL)
947#define LL_ADC_GROUP_REGULAR_INJECTED (0x00000003UL)
956#define LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER | ADC_CHANNEL_0_SMP | ADC_CHANNEL_0_BITFIELD )
957#define LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER | ADC_CHANNEL_1_SMP | ADC_CHANNEL_1_BITFIELD )
958#define LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER | ADC_CHANNEL_2_SMP | ADC_CHANNEL_2_BITFIELD )
959#define LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER | ADC_CHANNEL_3_SMP | ADC_CHANNEL_3_BITFIELD )
960#define LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER | ADC_CHANNEL_4_SMP | ADC_CHANNEL_4_BITFIELD )
961#define LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER | ADC_CHANNEL_5_SMP | ADC_CHANNEL_5_BITFIELD )
962#define LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER | ADC_CHANNEL_6_SMP | ADC_CHANNEL_6_BITFIELD )
963#define LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER | ADC_CHANNEL_7_SMP | ADC_CHANNEL_7_BITFIELD )
964#define LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER | ADC_CHANNEL_8_SMP | ADC_CHANNEL_8_BITFIELD )
965#define LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER | ADC_CHANNEL_9_SMP | ADC_CHANNEL_9_BITFIELD )
966#define LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_SMP | ADC_CHANNEL_10_BITFIELD)
967#define LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_SMP | ADC_CHANNEL_11_BITFIELD)
968#define LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_SMP | ADC_CHANNEL_12_BITFIELD)
969#define LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_SMP | ADC_CHANNEL_13_BITFIELD)
970#define LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_SMP | ADC_CHANNEL_14_BITFIELD)
971#define LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_SMP | ADC_CHANNEL_15_BITFIELD)
972#define LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_SMP | ADC_CHANNEL_16_BITFIELD)
973#define LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_SMP | ADC_CHANNEL_17_BITFIELD)
974#define LL_ADC_CHANNEL_18 (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_SMP | ADC_CHANNEL_18_BITFIELD)
975#define LL_ADC_CHANNEL_19 (ADC_CHANNEL_19_NUMBER | ADC_CHANNEL_19_SMP | ADC_CHANNEL_19_BITFIELD)
976#if defined(ADC3)
977#if defined(ADC_VER_V5_V90)
978#define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH)
979#define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH)
980#define LL_ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH)
981#else
982#define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_19 | ADC_CHANNEL_ID_INTERNAL_CH)
983#define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH)
984#define LL_ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH)
985#endif /* ADC_VER_V5_V90 */
986#else
988#define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_19 | ADC_CHANNEL_ID_INTERNAL_CH)
989#define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH)
990#define LL_ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_14 | ADC_CHANNEL_ID_INTERNAL_CH)
991#endif
992#define LL_ADC_CHANNEL_DAC1CH1_ADC2 (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH)
993#define LL_ADC_CHANNEL_DAC1CH2_ADC2 (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH)
994#if defined(DAC2)
996#define LL_ADC_CHANNEL_DAC2CH1_ADC2 (LL_ADC_CHANNEL_15 | ADC_CHANNEL_ID_INTERNAL_CH)
997#endif
1006#define LL_ADC_REG_TRIG_SOFTWARE (0x00000000UL)
1007#define LL_ADC_REG_TRIG_EXT_TIM1_CH1 (ADC_REG_TRIG_EXT_EDGE_DEFAULT)
1008#define LL_ADC_REG_TRIG_EXT_TIM1_CH2 (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
1009#define LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
1010#define LL_ADC_REG_TRIG_EXT_TIM2_CH2 (ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
1011#define LL_ADC_REG_TRIG_EXT_TIM3_TRGO (ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
1012#define LL_ADC_REG_TRIG_EXT_TIM4_CH4 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
1013#define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
1014#define LL_ADC_REG_TRIG_EXT_TIM8_TRGO (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
1015#define LL_ADC_REG_TRIG_EXT_TIM8_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
1016#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
1017#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
1018#define LL_ADC_REG_TRIG_EXT_TIM2_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
1019#define LL_ADC_REG_TRIG_EXT_TIM4_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
1020#define LL_ADC_REG_TRIG_EXT_TIM6_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
1021#define LL_ADC_REG_TRIG_EXT_TIM15_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
1022#define LL_ADC_REG_TRIG_EXT_TIM3_CH4 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
1023#define LL_ADC_REG_TRIG_EXT_HRTIM_TRG1 (ADC_CFGR_EXTSEL_4 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
1024#define LL_ADC_REG_TRIG_EXT_HRTIM_TRG3 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
1025#define LL_ADC_REG_TRIG_EXT_LPTIM1_OUT (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
1026#define LL_ADC_REG_TRIG_EXT_LPTIM2_OUT (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
1027#define LL_ADC_REG_TRIG_EXT_LPTIM3_OUT (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
1028#if defined (TIM23)
1029#define LL_ADC_REG_TRIG_EXT_TIM23_TRGO (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
1030#endif /* TIM23 */
1031#if defined (TIM24)
1032#define LL_ADC_REG_TRIG_EXT_TIM24_TRGO (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
1033#endif /* TIM24 */
1042#define LL_ADC_REG_TRIG_EXT_RISING ( ADC_CFGR_EXTEN_0)
1043#define LL_ADC_REG_TRIG_EXT_FALLING (ADC_CFGR_EXTEN_1 )
1044#define LL_ADC_REG_TRIG_EXT_RISINGFALLING (ADC_CFGR_EXTEN_1 | ADC_CFGR_EXTEN_0)
1048#if defined(ADC_VER_V5_V90)
1053#define LL_ADC_REG_SAMPLING_MODE_NORMAL (0x00000000UL)
1054#define LL_ADC_REG_SAMPLING_MODE_BULB (ADC3_CFGR2_BULB)
1056#define LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED (ADC3_CFGR2_SMPTRIG)
1062#endif /* ADC_VER_V5_V90 */
1063
1068#define LL_ADC_REG_CONV_SINGLE (0x00000000UL)
1069#define LL_ADC_REG_CONV_CONTINUOUS (ADC_CFGR_CONT)
1078#define LL_ADC_REG_DR_TRANSFER (0x00000000UL)
1079#define LL_ADC_REG_DMA_TRANSFER_LIMITED ( ADC_CFGR_DMNGT_0)
1080#define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CFGR_DMNGT_1 | ADC_CFGR_DMNGT_0)
1081#define LL_ADC_REG_DFSDM_TRANSFER (ADC_CFGR_DMNGT_1 )
1086#if defined(ADC_VER_V5_V90)
1092#define LL_ADC3_REG_DMA_TRANSFER_NONE (0x00000000UL)
1093#define LL_ADC3_REG_DMA_TRANSFER_LIMITED ( ADC3_CFGR_DMAEN)
1094#define LL_ADC3_REG_DMA_TRANSFER_UNLIMITED (ADC3_CFGR_DMACFG | ADC3_CFGR_DMAEN)
1098#endif /* ADC_VER_V5_V90 */
1099
1104#define LL_ADC_REG_OVR_DATA_PRESERVED (0x00000000UL)
1105#define LL_ADC_REG_OVR_DATA_OVERWRITTEN (ADC_CFGR_OVRMOD)
1114#define LL_ADC_REG_SEQ_SCAN_DISABLE (0x00000000UL)
1115#define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS ( ADC_SQR1_L_0)
1116#define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS ( ADC_SQR1_L_1 )
1117#define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS ( ADC_SQR1_L_1 | ADC_SQR1_L_0)
1118#define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS ( ADC_SQR1_L_2 )
1119#define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_0)
1120#define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 )
1121#define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0)
1122#define LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS (ADC_SQR1_L_3 )
1123#define LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_0)
1124#define LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 )
1125#define LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 | ADC_SQR1_L_0)
1126#define LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 )
1127#define LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_0)
1128#define LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 )
1129#define LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0)
1138#define LL_ADC_REG_SEQ_DISCONT_DISABLE (0x00000000UL)
1139#define LL_ADC_REG_SEQ_DISCONT_1RANK ( ADC_CFGR_DISCEN)
1140#define LL_ADC_REG_SEQ_DISCONT_2RANKS ( ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN)
1141#define LL_ADC_REG_SEQ_DISCONT_3RANKS ( ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCEN)
1142#define LL_ADC_REG_SEQ_DISCONT_4RANKS ( ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN)
1143#define LL_ADC_REG_SEQ_DISCONT_5RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCEN)
1144#define LL_ADC_REG_SEQ_DISCONT_6RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN)
1145#define LL_ADC_REG_SEQ_DISCONT_7RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCEN)
1146#define LL_ADC_REG_SEQ_DISCONT_8RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN)
1155#define LL_ADC_REG_RANK_1 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_1_SQRX_BITOFFSET_POS)
1156#define LL_ADC_REG_RANK_2 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_2_SQRX_BITOFFSET_POS)
1157#define LL_ADC_REG_RANK_3 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_3_SQRX_BITOFFSET_POS)
1158#define LL_ADC_REG_RANK_4 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_4_SQRX_BITOFFSET_POS)
1159#define LL_ADC_REG_RANK_5 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_5_SQRX_BITOFFSET_POS)
1160#define LL_ADC_REG_RANK_6 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_6_SQRX_BITOFFSET_POS)
1161#define LL_ADC_REG_RANK_7 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_7_SQRX_BITOFFSET_POS)
1162#define LL_ADC_REG_RANK_8 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_8_SQRX_BITOFFSET_POS)
1163#define LL_ADC_REG_RANK_9 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_9_SQRX_BITOFFSET_POS)
1164#define LL_ADC_REG_RANK_10 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_10_SQRX_BITOFFSET_POS)
1165#define LL_ADC_REG_RANK_11 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_11_SQRX_BITOFFSET_POS)
1166#define LL_ADC_REG_RANK_12 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_12_SQRX_BITOFFSET_POS)
1167#define LL_ADC_REG_RANK_13 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_13_SQRX_BITOFFSET_POS)
1168#define LL_ADC_REG_RANK_14 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_14_SQRX_BITOFFSET_POS)
1169#define LL_ADC_REG_RANK_15 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_15_SQRX_BITOFFSET_POS)
1170#define LL_ADC_REG_RANK_16 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_16_SQRX_BITOFFSET_POS)
1179#define LL_ADC_INJ_TRIG_SOFTWARE (0x00000000UL)
1180#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
1181#define LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
1182#define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
1183#define LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
1184#define LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
1185#define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
1186#define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
1187#define LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
1188#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
1189#define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
1190#define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
1191#define LL_ADC_INJ_TRIG_EXT_TIM3_CH3 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
1192#define LL_ADC_INJ_TRIG_EXT_TIM3_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
1193#define LL_ADC_INJ_TRIG_EXT_TIM3_CH1 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
1194#define LL_ADC_INJ_TRIG_EXT_TIM6_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
1195#define LL_ADC_INJ_TRIG_EXT_TIM15_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
1196#if defined(HRTIM1)
1197#define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2 (ADC_JSQR_JEXTSEL_4 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
1198#define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
1199#endif /* HRTIM1 */
1200#define LL_ADC_INJ_TRIG_EXT_LPTIM1_OUT (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
1201#define LL_ADC_INJ_TRIG_EXT_LPTIM2_OUT (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
1202#define LL_ADC_INJ_TRIG_EXT_LPTIM3_OUT (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
1203#define LL_ADC_INJ_TRIG_EXT_TIM23_TRGO (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
1204#define LL_ADC_INJ_TRIG_EXT_TIM24_TRGO (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
1213#define LL_ADC_INJ_TRIG_EXT_RISING ( ADC_JSQR_JEXTEN_0)
1214#define LL_ADC_INJ_TRIG_EXT_FALLING (ADC_JSQR_JEXTEN_1 )
1215#define LL_ADC_INJ_TRIG_EXT_RISINGFALLING (ADC_JSQR_JEXTEN_1 | ADC_JSQR_JEXTEN_0)
1224#define LL_ADC_INJ_TRIG_INDEPENDENT (0x00000000UL)
1225#define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR (ADC_CFGR_JAUTO)
1234#define LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE (0x00000000UL) /* Group injected sequence context queue is enabled and can contain up to 2 contexts. When all contexts have been processed, the queue maintains the last context active perpetually. */
1235#define LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY (ADC_CFGR_JQM) /* Group injected sequence context queue is enabled and can contain up to 2 contexts. When all contexts have been processed, the queue is empty and injected group triggers are disabled. */
1236#define LL_ADC_INJ_QUEUE_DISABLE (ADC_CFGR_JQDIS) /* Group injected sequence context queue is disabled: only 1 sequence can be configured and is active perpetually. */
1245#define LL_ADC_INJ_SEQ_SCAN_DISABLE (0x00000000UL)
1246#define LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS ( ADC_JSQR_JL_0)
1247#define LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS (ADC_JSQR_JL_1 )
1248#define LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS (ADC_JSQR_JL_1 | ADC_JSQR_JL_0)
1257#define LL_ADC_INJ_SEQ_DISCONT_DISABLE (0x00000000UL)
1258#define LL_ADC_INJ_SEQ_DISCONT_1RANK (ADC_CFGR_JDISCEN)
1267#define LL_ADC_INJ_RANK_1 (ADC_JDR1_REGOFFSET | ADC_INJ_RANK_1_JSQR_BITOFFSET_POS)
1268#define LL_ADC_INJ_RANK_2 (ADC_JDR2_REGOFFSET | ADC_INJ_RANK_2_JSQR_BITOFFSET_POS)
1269#define LL_ADC_INJ_RANK_3 (ADC_JDR3_REGOFFSET | ADC_INJ_RANK_3_JSQR_BITOFFSET_POS)
1270#define LL_ADC_INJ_RANK_4 (ADC_JDR4_REGOFFSET | ADC_INJ_RANK_4_JSQR_BITOFFSET_POS)
1279#define LL_ADC_SAMPLINGTIME_1CYCLE_5 (0x00000000UL)
1280#define LL_ADC_SAMPLINGTIME_2CYCLES_5 ( ADC_SMPR2_SMP10_0)
1281#define LL_ADC_SAMPLINGTIME_8CYCLES_5 ( ADC_SMPR2_SMP10_1 )
1282#define LL_ADC_SAMPLINGTIME_16CYCLES_5 ( ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0)
1283#define LL_ADC_SAMPLINGTIME_32CYCLES_5 (ADC_SMPR2_SMP10_2 )
1284#define LL_ADC_SAMPLINGTIME_64CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_0)
1285#define LL_ADC_SAMPLINGTIME_387CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1 )
1286#define LL_ADC_SAMPLINGTIME_810CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0)
1290#if defined(ADC_VER_V5_V90)
1295#define LL_ADC_SAMPLINGTIME_ADC3_2CYCLES_5 (0x00000000UL)
1296#define LL_ADC_SAMPLINGTIME_ADC3_6CYCLES_5 ( ADC_SMPR2_SMP10_0)
1297#define LL_ADC_SAMPLINGTIME_ADC3_12CYCLES_5 ( ADC_SMPR2_SMP10_1 )
1298#define LL_ADC_SAMPLINGTIME_ADC3_24CYCLES_5 ( ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0)
1299#define LL_ADC_SAMPLINGTIME_ADC3_47CYCLES_5 (ADC_SMPR2_SMP10_2 )
1300#define LL_ADC_SAMPLINGTIME_ADC3_92CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_0)
1301#define LL_ADC_SAMPLINGTIME_ADC3_247CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1 )
1302#define LL_ADC_SAMPLINGTIME_ADC3_640CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0)
1306#endif /* ADC_VER_V5_V90 */
1307
1312#define LL_ADC_SINGLE_ENDED ( ADC_CALFACT_CALFACT_S)
1313#define LL_ADC_DIFFERENTIAL_ENDED (ADC_CR_ADCALDIF | ADC_CALFACT_CALFACT_D)
1314#define LL_ADC_BOTH_SINGLE_DIFF_ENDED (LL_ADC_SINGLE_ENDED | LL_ADC_DIFFERENTIAL_ENDED)
1323#define LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR1_REGOFFSET)
1324#define LL_ADC_AWD2 (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR2_REGOFFSET)
1325#define LL_ADC_AWD3 (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR3_REGOFFSET)
1334#define LL_ADC_AWD_DISABLE (0x00000000UL)
1335#define LL_ADC_AWD_ALL_CHANNELS_REG (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_AWD1EN )
1336#define LL_ADC_AWD_ALL_CHANNELS_INJ (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_JAWD1EN )
1337#define LL_ADC_AWD_ALL_CHANNELS_REG_INJ (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN )
1338#define LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1339#define LL_ADC_AWD_CHANNEL_0_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
1340#define LL_ADC_AWD_CHANNEL_0_REG_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1341#define LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1342#define LL_ADC_AWD_CHANNEL_1_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
1343#define LL_ADC_AWD_CHANNEL_1_REG_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1344#define LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1345#define LL_ADC_AWD_CHANNEL_2_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
1346#define LL_ADC_AWD_CHANNEL_2_REG_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1347#define LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1348#define LL_ADC_AWD_CHANNEL_3_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
1349#define LL_ADC_AWD_CHANNEL_3_REG_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1350#define LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1351#define LL_ADC_AWD_CHANNEL_4_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
1352#define LL_ADC_AWD_CHANNEL_4_REG_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1353#define LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1354#define LL_ADC_AWD_CHANNEL_5_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
1355#define LL_ADC_AWD_CHANNEL_5_REG_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1356#define LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1357#define LL_ADC_AWD_CHANNEL_6_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
1358#define LL_ADC_AWD_CHANNEL_6_REG_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1359#define LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1360#define LL_ADC_AWD_CHANNEL_7_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
1361#define LL_ADC_AWD_CHANNEL_7_REG_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1362#define LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1363#define LL_ADC_AWD_CHANNEL_8_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
1364#define LL_ADC_AWD_CHANNEL_8_REG_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1365#define LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1366#define LL_ADC_AWD_CHANNEL_9_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
1367#define LL_ADC_AWD_CHANNEL_9_REG_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1368#define LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1369#define LL_ADC_AWD_CHANNEL_10_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
1370#define LL_ADC_AWD_CHANNEL_10_REG_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1371#define LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1372#define LL_ADC_AWD_CHANNEL_11_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
1373#define LL_ADC_AWD_CHANNEL_11_REG_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1374#define LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1375#define LL_ADC_AWD_CHANNEL_12_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
1376#define LL_ADC_AWD_CHANNEL_12_REG_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1377#define LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1378#define LL_ADC_AWD_CHANNEL_13_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
1379#define LL_ADC_AWD_CHANNEL_13_REG_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1380#define LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1381#define LL_ADC_AWD_CHANNEL_14_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
1382#define LL_ADC_AWD_CHANNEL_14_REG_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1383#define LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1384#define LL_ADC_AWD_CHANNEL_15_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
1385#define LL_ADC_AWD_CHANNEL_15_REG_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1386#define LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1387#define LL_ADC_AWD_CHANNEL_16_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
1388#define LL_ADC_AWD_CHANNEL_16_REG_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1389#define LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1390#define LL_ADC_AWD_CHANNEL_17_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
1391#define LL_ADC_AWD_CHANNEL_17_REG_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1392#define LL_ADC_AWD_CHANNEL_18_REG ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1393#define LL_ADC_AWD_CHANNEL_18_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
1394#define LL_ADC_AWD_CHANNEL_18_REG_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1395#define LL_ADC_AWD_CHANNEL_19_REG ((LL_ADC_CHANNEL_19 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1396#define LL_ADC_AWD_CHANNEL_19_INJ ((LL_ADC_CHANNEL_19 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
1397#define LL_ADC_AWD_CHANNEL_19_REG_INJ ((LL_ADC_CHANNEL_19 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1398#define LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1399#define LL_ADC_AWD_CH_VREFINT_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
1400#define LL_ADC_AWD_CH_VREFINT_REG_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1401#define LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1402#define LL_ADC_AWD_CH_TEMPSENSOR_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
1403#define LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1404#define LL_ADC_AWD_CH_VBAT_REG ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1405#define LL_ADC_AWD_CH_VBAT_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
1406#define LL_ADC_AWD_CH_VBAT_REG_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1407#define LL_ADC_AWD_CH_DAC1CH1_ADC2_REG ((LL_ADC_CHANNEL_DAC1CH1_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1408#define LL_ADC_AWD_CH_DAC1CH1_ADC2_INJ ((LL_ADC_CHANNEL_DAC1CH1_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
1409#define LL_ADC_AWD_CH_DAC1CH1_ADC2_REG_INJ ((LL_ADC_CHANNEL_DAC1CH1_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1410#define LL_ADC_AWD_CH_DAC1CH2_ADC2_REG ((LL_ADC_CHANNEL_DAC1CH2_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1411#define LL_ADC_AWD_CH_DAC1CH2_ADC2_INJ ((LL_ADC_CHANNEL_DAC1CH2_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
1412#define LL_ADC_AWD_CH_DAC1CH2_ADC2_REG_INJ ((LL_ADC_CHANNEL_DAC1CH2_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1421#define LL_ADC_AWD_THRESHOLD_HIGH (0x1UL)
1422#define LL_ADC_AWD_THRESHOLD_LOW (0x0UL)
1426#if defined(ADC_VER_V5_V90)
1431#define LL_ADC_AWD_FILTERING_NONE (0x00000000UL)
1432#define LL_ADC_AWD_FILTERING_2SAMPLES ( ADC3_TR1_AWDFILT_0)
1433#define LL_ADC_AWD_FILTERING_3SAMPLES ( ADC3_TR1_AWDFILT_1 )
1434#define LL_ADC_AWD_FILTERING_4SAMPLES ( ADC3_TR1_AWDFILT_1 | ADC3_TR1_AWDFILT_0)
1435#define LL_ADC_AWD_FILTERING_5SAMPLES (ADC3_TR1_AWDFILT_2 )
1436#define LL_ADC_AWD_FILTERING_6SAMPLES (ADC3_TR1_AWDFILT_2 | ADC3_TR1_AWDFILT_0)
1437#define LL_ADC_AWD_FILTERING_7SAMPLES (ADC3_TR1_AWDFILT_2 | ADC3_TR1_AWDFILT_1 )
1438#define LL_ADC_AWD_FILTERING_8SAMPLES (ADC3_TR1_AWDFILT_2 | ADC3_TR1_AWDFILT_1 | ADC3_TR1_AWDFILT_0)
1442#endif /* ADC_VER_V5_V90 */
1443
1448#define LL_ADC_OVS_DISABLE (0x00000000UL)
1449#define LL_ADC_OVS_GRP_REGULAR_CONTINUED ( ADC_CFGR2_ROVSE)
1450#define LL_ADC_OVS_GRP_REGULAR_RESUMED (ADC_CFGR2_ROVSM | ADC_CFGR2_ROVSE)
1451#define LL_ADC_OVS_GRP_INJECTED ( ADC_CFGR2_JOVSE )
1452#define LL_ADC_OVS_GRP_INJ_REG_RESUMED ( ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE)
1461#define LL_ADC_OVS_REG_CONT (0x00000000UL)
1462#define LL_ADC_OVS_REG_DISCONT (ADC_CFGR2_TROVS)
1466#if defined(ADC_VER_V5_V90)
1471#define LL_ADC_OVS_RATIO_2 (0x00000000UL)
1472#define LL_ADC_OVS_RATIO_4 ( ADC3_CFGR2_OVSR_0)
1473#define LL_ADC_OVS_RATIO_8 ( ADC3_CFGR2_OVSR_1 )
1474#define LL_ADC_OVS_RATIO_16 ( ADC3_CFGR2_OVSR_1 | ADC3_CFGR2_OVSR_0)
1475#define LL_ADC_OVS_RATIO_32 (ADC3_CFGR2_OVSR_2 )
1476#define LL_ADC_OVS_RATIO_64 (ADC3_CFGR2_OVSR_2 | ADC3_CFGR2_OVSR_0)
1477#define LL_ADC_OVS_RATIO_128 (ADC3_CFGR2_OVSR_2 | ADC3_CFGR2_OVSR_1 )
1478#define LL_ADC_OVS_RATIO_256 (ADC3_CFGR2_OVSR_2 | ADC3_CFGR2_OVSR_1 | ADC3_CFGR2_OVSR_0)
1482#endif /* ADC_VER_V5_V90 */
1483
1488#define LL_ADC_OVS_SHIFT_NONE (0x00000000UL)
1489#define LL_ADC_OVS_SHIFT_RIGHT_1 ( ADC_CFGR2_OVSS_0)
1490#define LL_ADC_OVS_SHIFT_RIGHT_2 ( ADC_CFGR2_OVSS_1 )
1491#define LL_ADC_OVS_SHIFT_RIGHT_3 ( ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0)
1492#define LL_ADC_OVS_SHIFT_RIGHT_4 ( ADC_CFGR2_OVSS_2 )
1493#define LL_ADC_OVS_SHIFT_RIGHT_5 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_0)
1494#define LL_ADC_OVS_SHIFT_RIGHT_6 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 )
1495#define LL_ADC_OVS_SHIFT_RIGHT_7 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0)
1496#define LL_ADC_OVS_SHIFT_RIGHT_8 (ADC_CFGR2_OVSS_3 )
1497#define LL_ADC_OVS_SHIFT_RIGHT_9 (ADC_CFGR2_OVSS_3 | ADC_CFGR2_OVSS_0)
1498#define LL_ADC_OVS_SHIFT_RIGHT_10 (ADC_CFGR2_OVSS_3 | ADC_CFGR2_OVSS_1 )
1499#define LL_ADC_OVS_SHIFT_RIGHT_11 (ADC_CFGR2_OVSS_3 | ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0)
1508#define LL_ADC_MULTI_INDEPENDENT (0x00000000UL)
1509#define LL_ADC_MULTI_DUAL_REG_SIMULT ( ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1 )
1510#define LL_ADC_MULTI_DUAL_REG_INTERL ( ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0)
1511#define LL_ADC_MULTI_DUAL_INJ_SIMULT ( ADC_CCR_DUAL_2 | ADC_CCR_DUAL_0)
1512#define LL_ADC_MULTI_DUAL_INJ_ALTERN (ADC_CCR_DUAL_3 | ADC_CCR_DUAL_0)
1513#define LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM ( ADC_CCR_DUAL_0)
1514#define LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT ( ADC_CCR_DUAL_1 )
1515#define LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM ( ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0)
1524#define LL_ADC_MULTI_REG_DMA_EACH_ADC (0x00000000UL)
1525#define LL_ADC_MULTI_REG_DMA_RES_32_10B (ADC_CCR_DAMDF_1 )
1526#define LL_ADC_MULTI_REG_DMA_RES_8B (ADC_CCR_DAMDF_1 | ADC_CCR_DAMDF_0)
1535#define LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE_5 (0x00000000UL)
1536#define LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES_5 ( ADC_CCR_DELAY_0)
1537#define LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES_5 ( ADC_CCR_DELAY_1 )
1538#define LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES_5 ( ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0)
1539#define LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES_5_8_BITS ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0)
1540#define LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES_5 ( ADC_CCR_DELAY_2 )
1541#define LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES_5_10_BITS ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0)
1542#define LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES (ADC_CCR_DELAY_3 )
1543#define LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES_5 ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0)
1544#define LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES_5_12_BITS ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0)
1545#define LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES_5 ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0)
1546#define LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES (ADC_CCR_DELAY_3 )
1547#define LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES (ADC_CCR_DELAY_3 )
1556#define LL_ADC_MULTI_MASTER ( ADC_CDR_RDATA_MST)
1557#define LL_ADC_MULTI_SLAVE (ADC_CDR_RDATA_SLV )
1558#define LL_ADC_MULTI_MASTER_SLAVE (ADC_CDR_RDATA_SLV | ADC_CDR_RDATA_MST)
1574/* Note: Only ADC peripheral HW delays are defined in ADC LL driver driver, */
1575/* not timeout values. */
1576/* Timeout values for ADC operations are dependent to device clock */
1577/* configuration (system clock versus ADC clock), */
1578/* and therefore must be defined in user application. */
1579/* Indications for estimation of ADC timeout delays, for this */
1580/* STM32 series: */
1581/* - ADC calibration time: maximum delay is 16384/fADC. */
1582/* (refer to device datasheet, parameter "tCAL") */
1583/* - ADC enable time: maximum delay is 1 conversion cycle. */
1584/* (refer to device datasheet, parameter "tSTAB") */
1585/* - ADC disable time: maximum delay should be a few ADC clock cycles */
1586/* - ADC stop conversion time: maximum delay should be a few ADC clock */
1587/* cycles */
1588/* - ADC conversion time: duration depending on ADC clock and ADC */
1589/* configuration. */
1590/* (refer to device reference manual, section "Timing") */
1591
1592/* Delay for ADC stabilization time (ADC voltage regulator start-up time) */
1593/* Delay set to maximum value (refer to device datasheet, */
1594/* parameter "tADCVREG_STUP"). */
1595/* Unit: us */
1596#define LL_ADC_DELAY_INTERNAL_REGUL_STAB_US ( 10UL)
1598/* Delay for internal voltage reference stabilization time. */
1599/* Delay set to maximum value (refer to device datasheet, */
1600/* parameter "ts_vrefint"). */
1601/* Unit: us */
1602#define LL_ADC_DELAY_VREFINT_STAB_US (5UL)
1604/* Delay for temperature sensor stabilization time. */
1605/* Literal set to maximum value (refer to device datasheet, */
1606/* parameter "tSTART_RUN"). */
1607/* Unit: us */
1608#define LL_ADC_DELAY_TEMPSENSOR_STAB_US ( 26UL)
1610/* Delay required between ADC end of calibration and ADC enable. */
1611/* Note: On this STM32 series, a minimum number of ADC clock cycles */
1612/* are required between ADC end of calibration and ADC enable. */
1613/* Wait time can be computed in user application by waiting for the */
1614/* equivalent number of CPU cycles, by taking into account */
1615/* ratio of CPU clock versus ADC clock prescalers. */
1616/* Unit: ADC clock cycles. */
1617#define LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES ( 4UL)
1619/* Fixed timeout value for ADC linearity word bit set/clear delay. */
1620/* Values defined to be higher than worst cases: low clock frequency, */
1621/* maximum prescalers. */
1622/* Ex of profile low frequency : f_ADC at 4,577 Khz (minimum value */
1623/* according to Data sheet), linearity set/clear bit delay MAX = 6 / f_ADC + 3 cycles AHB */
1624/* 6 / 4577 = 1,311ms */
1625/* At maximum CPU speed (400 MHz), this means */
1626/* 3.58 * 400 MHz = 524400 CPU cycles */
1627#define ADC_LINEARITY_BIT_TOGGLE_TIMEOUT (524400UL)
1638/* Exported macro ------------------------------------------------------------*/
1656#define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
1657
1664#define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
1674#if defined(ADC_VER_V5_V90)
1691#define __LL_ADC12_RESOLUTION_TO_ADC3(__ADC_RESOLUTION__) \
1692 ( \
1693 ((__ADC_RESOLUTION__) == LL_ADC_RESOLUTION_12B) \
1694 ?(0x00000000UL) \
1695 : \
1696 ((__ADC_RESOLUTION__) == LL_ADC_RESOLUTION_10B) \
1697 ?(ADC_CFGR_RES_0) \
1698 : \
1699 ((__ADC_RESOLUTION__) == LL_ADC_RESOLUTION_8B) \
1700 ?(ADC_CFGR_RES_1) \
1701 : \
1702 ((__ADC_RESOLUTION__) == LL_ADC_RESOLUTION_6B) \
1703 ?((ADC_CFGR_RES_2|ADC_CFGR_RES_1 | ADC_CFGR_RES_0)) \
1704 :(0x00000000UL) \
1705 )
1706
1707#endif /* ADC_VER_V5_V90 */
1708
1751#define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
1752 ((((__CHANNEL__) & ADC_CHANNEL_ID_BITFIELD_MASK) == 0UL) \
1753 ? ( \
1754 ((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS \
1755 ) \
1756 : \
1757 ( \
1758 (uint32_t)POSITION_VAL((__CHANNEL__)) \
1759 ) \
1760 )
1761
1804#define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
1805 (((__DECIMAL_NB__) <= 9UL) \
1806 ? ( \
1807 ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
1808 (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__)) | \
1809 (ADC_SMPR1_REGOFFSET | (((3UL * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
1810 ) \
1811 : \
1812 ( \
1813 ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
1814 (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__)) | \
1815 (ADC_SMPR2_REGOFFSET | (((3UL * ((__DECIMAL_NB__) - 10UL))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
1816 ) \
1817 )
1818
1870#define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \
1871 (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0UL)
1872
1939#define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \
1940 ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)
1941
1968#if defined(ADC3)
1969#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
1970 ((((__ADC_INSTANCE__) == ADC2) \
1971 &&( \
1972 ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH1_ADC2) || \
1973 ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH2_ADC2) \
1974 ) \
1975 ) \
1976 || \
1977 (((__ADC_INSTANCE__) == ADC3) \
1978 &&( \
1979 ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) || \
1980 ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \
1981 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) \
1982 ) \
1983 ) \
1984 )
1985#else
1986#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
1987 ((((__ADC_INSTANCE__) == ADC2) \
1988 &&( \
1989 ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH1_ADC2) || \
1990 ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH2_ADC2) || \
1991 ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) || \
1992 ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \
1993 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) \
1994 ) \
1995 ) \
1996 )
1997#endif
1998
2131#define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__) \
2132 (((__GROUP__) == LL_ADC_GROUP_REGULAR) \
2133 ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) \
2134 : \
2135 ((__GROUP__) == LL_ADC_GROUP_INJECTED) \
2136 ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) \
2137 : \
2138 (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) \
2139 )
2140
2161#define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) \
2162 ((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U )))
2163
2184#define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_16_BITS__) \
2185 ((__AWD_THRESHOLD_16_BITS__) >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U )))
2186
2200#define __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(__CALIB_FACTOR_SINGLE_ENDED__, __CALIB_FACTOR_DIFFERENTIAL__) \
2201 (((__CALIB_FACTOR_DIFFERENTIAL__) << ADC_CALFACT_CALFACT_D_Pos) | (__CALIB_FACTOR_SINGLE_ENDED__))
2202
2216#define __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \
2217 (((__ADC_MULTI_CONV_DATA__) >> ((ADC_CDR_RDATA_SLV_Pos) & ~(__ADC_MULTI_MASTER_SLAVE__))) & ADC_CDR_RDATA_MST)
2218
2231#define __LL_ADC_MULTI_INSTANCE_MASTER(__ADCx__) \
2232 ( ( ((__ADCx__) == ADC2) \
2233 )? \
2234 (ADC1) \
2235 : \
2236 (__ADCx__) \
2237 )
2238
2249#if defined(ADC3_COMMON)
2250#define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
2251 ((((__ADCx__) == ADC1) || ((__ADCx__) == ADC2)) \
2252 ? ( \
2253 (ADC12_COMMON) \
2254 ) \
2255 : \
2256 ( \
2257 (ADC3_COMMON) \
2258 ) \
2259 )
2260#else
2261#define __LL_ADC_COMMON_INSTANCE(__ADCx__) (ADC12_COMMON)
2262#endif
2263
2281#if defined(ADC3_COMMON)
2282#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
2283 (((__ADCXY_COMMON__) == ADC12_COMMON) \
2284 ? ( \
2285 (LL_ADC_IsEnabled(ADC1) | \
2286 LL_ADC_IsEnabled(ADC2) ) \
2287 ) \
2288 : \
2289 ( \
2290 (LL_ADC_IsEnabled(ADC3)) \
2291 ) \
2292 )
2293#else
2294#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
2295 (LL_ADC_IsEnabled(ADC1) | LL_ADC_IsEnabled(ADC2))
2296#endif
2297
2312#define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
2313 (0xFFFFUL >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)))
2314
2315#if defined(ADC_VER_V5_V90)
2329#define __LL_ADC3_DIGITAL_SCALE(__ADC_RESOLUTION__) \
2330 (0xFFFUL >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS_ADC3 - 1UL)))
2331#endif /* ADC_VER_V5_V90 */
2352#if defined(ADC_VER_V5_X) || defined(ADC_VER_V5_V90)
2353#define __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\
2354 __ADC_RESOLUTION_CURRENT__,\
2355 __ADC_RESOLUTION_TARGET__) \
2356( (__ADC_RESOLUTION_CURRENT__ == LL_ADC_RESOLUTION_8B) \
2357 ?( \
2358 ((__DATA__) \
2359 << (((__ADC_RESOLUTION_CURRENT__) & ~(ADC_CFGR_RES_1 | ADC_CFGR_RES_0) ) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL))) \
2360 >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)) \
2361 ) \
2362 : \
2363 ( \
2364 (__ADC_RESOLUTION_TARGET__ == LL_ADC_RESOLUTION_8B) \
2365 ? ( \
2366 ((__DATA__) \
2367 << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL))) \
2368 >> (((__ADC_RESOLUTION_TARGET__) & ~(ADC_CFGR_RES_1 | ADC_CFGR_RES_0) ) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)) \
2369 ) \
2370 :\
2371 (\
2372 ((__DATA__) \
2373 << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL))) \
2374 >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)) \
2375 ) \
2376 )\
2377 )
2378
2379
2380#else /* defined(ADC_VER_V5_3) */
2381#define __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\
2382 __ADC_RESOLUTION_CURRENT__,\
2383 __ADC_RESOLUTION_TARGET__) \
2384( (__ADC_RESOLUTION_CURRENT__ == LL_ADC_RESOLUTION_8B) \
2385 ?( \
2386 ((__DATA__) \
2387 << (((__ADC_RESOLUTION_CURRENT__) & ~(ADC_CFGR_RES_1 | ADC_CFGR_RES_0) ) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL))) \
2388 >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)) \
2389 ) \
2390 : \
2391 ( \
2392 (__ADC_RESOLUTION_TARGET__ == LL_ADC_RESOLUTION_8B) \
2393 ? ( \
2394 ((__DATA__) \
2395 << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL))) \
2396 >> (((__ADC_RESOLUTION_TARGET__) & ~(ADC_CFGR_RES_1 | ADC_CFGR_RES_0) ) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)) \
2397 ) \
2398 :\
2399 (\
2400 ((__DATA__) \
2401 << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL))) \
2402 >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)) \
2403 ) \
2404 )\
2405 )
2406
2407#endif
2408
2409#if defined(ADC_VER_V5_V90)
2428#define __LL_ADC_CONVERT_DATA_RESOLUTION_ADC3(__DATA__,\
2429 __ADC_RESOLUTION_CURRENT__,\
2430 __ADC_RESOLUTION_TARGET__) \
2431 (((__DATA__) \
2432 << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR_RES_BITOFFSET_POS_ADC3 - 1UL))) \
2433 >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR_RES_BITOFFSET_POS_ADC3 - 1UL)) \
2434 )
2435#endif /* ADC_VER_V5_V90 */
2453#define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
2454 __ADC_DATA__,\
2455 __ADC_RESOLUTION__) \
2456 ((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__) \
2457 / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
2458 )
2459
2486#define __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\
2487 __ADC_RESOLUTION__) \
2488 (((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF) \
2489 / __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__), \
2490 (__ADC_RESOLUTION__), \
2491 LL_ADC_RESOLUTION_16B) \
2492 )
2493
2540#define __LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\
2541 __TEMPSENSOR_ADC_DATA__,\
2542 __ADC_RESOLUTION__) \
2543 (((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__), \
2544 (__ADC_RESOLUTION__), \
2545 LL_ADC_RESOLUTION_16B) \
2546 * (__VREFANALOG_VOLTAGE__)) \
2547 / TEMPSENSOR_CAL_VREFANALOG) \
2548 - (int32_t) *TEMPSENSOR_CAL1_ADDR) \
2549 ) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP) \
2550 ) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) \
2551 ) + TEMPSENSOR_CAL1_TEMP \
2552 )
2553
2599#define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\
2600 __TEMPSENSOR_TYP_CALX_V__,\
2601 __TEMPSENSOR_CALX_TEMP__,\
2602 __VREFANALOG_VOLTAGE__,\
2603 __TEMPSENSOR_ADC_DATA__,\
2604 __ADC_RESOLUTION__) \
2605 ((( ( \
2606 (int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__)) \
2607 / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)) \
2608 * 1000UL) \
2609 - \
2610 (int32_t)(((__TEMPSENSOR_TYP_CALX_V__)) \
2611 * 1000UL) \
2612 ) \
2613 ) / (int32_t)(__TEMPSENSOR_TYP_AVGSLOPE__) \
2614 ) + (int32_t)(__TEMPSENSOR_CALX_TEMP__) \
2615 )
2616
2626/* Exported functions --------------------------------------------------------*/
2667__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register)
2668{
2669 uint32_t data_reg_addr;
2670
2671 if (Register == LL_ADC_DMA_REG_REGULAR_DATA)
2672 {
2673 /* Retrieve address of register DR */
2674 data_reg_addr = (uint32_t) & (ADCx->DR);
2675 }
2676 else /* (Register == LL_ADC_DMA_REG_REGULAR_DATA_MULTI) */
2677 {
2678 /* Retrieve address of register CDR */
2679 data_reg_addr = (uint32_t) & ((__LL_ADC_COMMON_INSTANCE(ADCx))->CDR);
2680 }
2681
2682 return data_reg_addr;
2683}
2684
2728__STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock)
2729{
2730 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC, CommonClock);
2731}
2732
2756__STATIC_INLINE uint32_t LL_ADC_GetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON)
2757{
2758 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC));
2759}
2760
2796__STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
2797{
2798 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN, PathInternal);
2799}
2800
2818__STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON)
2819{
2820 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN));
2821}
2822
2853__STATIC_INLINE void LL_ADC_SetCommonPathInternalChAdd(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
2854{
2855 SET_BIT(ADCxy_COMMON->CCR, PathInternal);
2856}
2857
2877__STATIC_INLINE void LL_ADC_SetCommonPathInternalChRem(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
2878{
2879 CLEAR_BIT(ADCxy_COMMON->CCR, PathInternal);
2880}
2881
2925__STATIC_INLINE void LL_ADC_SetCalibrationOffsetFactor(ADC_TypeDef *ADCx, uint32_t SingleDiff, uint32_t CalibrationFactor)
2926{
2927#if defined(ADC_VER_V5_V90)
2928 MODIFY_REG(ADCx->CALFACT_RES13,
2929 SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK,
2930 CalibrationFactor << (((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >> ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4) & ~(SingleDiff & ADC_CALFACT_CALFACT_S)));
2931#else
2932 MODIFY_REG(ADCx->CALFACT,
2933 SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK,
2934 CalibrationFactor << (((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >> ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4) & ~(SingleDiff & ADC_CALFACT_CALFACT_S)));
2935#endif /* ADC_VER_V5_V90 */
2936}
2937
2956__STATIC_INLINE uint32_t LL_ADC_GetCalibrationOffsetFactor(ADC_TypeDef *ADCx, uint32_t SingleDiff)
2957{
2958 /* Retrieve bits with position in register depending on parameter */
2959 /* "SingleDiff". */
2960 /* Parameter used with mask "ADC_SINGLEDIFF_CALIB_FACTOR_MASK" because */
2961 /* containing other bits reserved for other purpose. */
2962#if defined(ADC_VER_V5_V90)
2963 return (uint32_t)(READ_BIT(ADCx->CALFACT_RES13, (SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK)) >> ((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >> ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4));
2964#else
2965 return (uint32_t)(READ_BIT(ADCx->CALFACT, (SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK)) >> ((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >> ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4));
2966#endif /* ADC_VER_V5_V90 */
2967}
2968
2991__STATIC_INLINE void LL_ADC_SetCalibrationLinearFactor(ADC_TypeDef *ADCx, uint32_t LinearityWord, uint32_t CalibrationFactor)
2992{
2993#if defined(ADC_VER_V5_V90)
2994 if (ADCx != ADC3)
2995 {
2996 uint32_t timeout_cpu_cycles = ADC_LINEARITY_BIT_TOGGLE_TIMEOUT;
2997 MODIFY_REG(ADCx->CALFACT2_RES14, ADC_CALFACT2_LINCALFACT, CalibrationFactor);
2998 MODIFY_REG(ADCx->CR, ADC_CR_ADCALLIN, LinearityWord);
2999 while ((READ_BIT(ADCx->CR, LinearityWord) == 0UL) && (timeout_cpu_cycles > 0UL))
3000 {
3001 timeout_cpu_cycles--;
3002 }
3003 }
3004#else
3005 uint32_t timeout_cpu_cycles = ADC_LINEARITY_BIT_TOGGLE_TIMEOUT;
3006 MODIFY_REG(ADCx->CALFACT2, ADC_CALFACT2_LINCALFACT, CalibrationFactor);
3007 MODIFY_REG(ADCx->CR, ADC_CR_ADCALLIN, LinearityWord);
3008 while ((READ_BIT(ADCx->CR, LinearityWord) == 0UL) && (timeout_cpu_cycles > 0UL))
3009 {
3010 timeout_cpu_cycles--;
3011 }
3012#endif /* ADC_VER_V5_V90 */
3013}
3014
3031__STATIC_INLINE uint32_t LL_ADC_GetCalibrationLinearFactor(ADC_TypeDef *ADCx, uint32_t LinearityWord)
3032{
3033 uint32_t timeout_cpu_cycles = ADC_LINEARITY_BIT_TOGGLE_TIMEOUT;
3034 CLEAR_BIT(ADCx->CR, LinearityWord);
3035 while ((READ_BIT(ADCx->CR, LinearityWord) != 0UL) && (timeout_cpu_cycles > 0UL))
3036 {
3037 timeout_cpu_cycles--;
3038 }
3039#if defined(ADC_VER_V5_V90)
3040 return (uint32_t)(READ_BIT(ADCx->CALFACT2_RES14, ADC_CALFACT2_LINCALFACT));
3041#else
3042 return (uint32_t)(READ_BIT(ADCx->CALFACT2, ADC_CALFACT2_LINCALFACT));
3043#endif /* ADC_VER_V5_V90 */
3044}
3063__STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution)
3064{
3065#if defined(ADC_VER_V5_3)
3066
3067 MODIFY_REG(ADCx->CFGR, ADC_CFGR_RES, Resolution);
3068
3069#elif defined(ADC_VER_V5_V90)
3070 if (ADCx == ADC3)
3071 {
3072 MODIFY_REG(ADCx->CFGR, ADC3_CFGR_RES, ((__LL_ADC12_RESOLUTION_TO_ADC3(Resolution) & (ADC_CFGR_RES_1 | ADC_CFGR_RES_0)) << 1UL));
3073 }
3074 else
3075 {
3076 if ((DBGMCU->IDCODE & 0x30000000UL) == 0x10000000UL) /* Rev.Y */
3077 {
3078 MODIFY_REG(ADCx->CFGR, ADC_CFGR_RES, Resolution);
3079 }
3080 else /* Rev.V */
3081 {
3082 if (LL_ADC_RESOLUTION_8B == Resolution)
3083 {
3084 MODIFY_REG(ADCx->CFGR, ADC_CFGR_RES, Resolution | 0x0000000CUL);
3085 }
3086 else
3087 {
3088 MODIFY_REG(ADCx->CFGR, ADC_CFGR_RES, Resolution);
3089 }
3090 }
3091 }
3092#else /* ADC_VER_V5_V90 */
3093 if ((DBGMCU->IDCODE & 0x30000000UL) == 0x10000000UL) /* Rev.Y */
3094 {
3095 MODIFY_REG(ADCx->CFGR, ADC_CFGR_RES, Resolution);
3096 }
3097 else /* Rev.V */
3098 {
3099 if (LL_ADC_RESOLUTION_8B == Resolution)
3100 {
3101 MODIFY_REG(ADCx->CFGR, ADC_CFGR_RES, Resolution | 0x0000000CUL);
3102 }
3103 else
3104 {
3105 MODIFY_REG(ADCx->CFGR, ADC_CFGR_RES, Resolution);
3106 }
3107 }
3108
3109#endif /* ADC_VER_V5_X*/
3110}
3111
3128__STATIC_INLINE uint32_t LL_ADC_GetResolution(ADC_TypeDef *ADCx)
3129{
3130#if defined (ADC_VER_V5_3)
3131
3132 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_RES));
3133
3134#elif defined(ADC_VER_V5_V90)
3135 if (ADCx == ADC3)
3136 {
3137 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC3_CFGR_RES));
3138 }
3139 else
3140 {
3141 if ((uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_RES)) == 0x0000001CUL)
3142 {
3143 return (LL_ADC_RESOLUTION_8B);
3144 }
3145 else
3146 {
3147 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_RES));
3148 }
3149 }
3150
3151#else /* ADC_VER_V5_V90 */
3152 if ((DBGMCU->IDCODE & 0x30000000UL) == 0x10000000UL) /* Rev.Y */
3153 {
3154 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_RES));
3155 }
3156 else /* Rev.V */
3157 {
3158 if ((uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_RES)) == 0x0000001CUL)
3159 {
3160 return (LL_ADC_RESOLUTION_8B);
3161 }
3162 else
3163 {
3164 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_RES));
3165 }
3166 }
3167
3168#endif /* ADC_VER_V5_X */
3169}
3170
3222__STATIC_INLINE void LL_ADC_SetLowPowerMode(ADC_TypeDef *ADCx, uint32_t LowPowerMode)
3223{
3224 MODIFY_REG(ADCx->CFGR, ADC_CFGR_AUTDLY, LowPowerMode);
3225}
3226
3273__STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(ADC_TypeDef *ADCx)
3274{
3275 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_AUTDLY));
3276}
3277
3309__STATIC_INLINE void LL_ADC_SetChannelPreselection(ADC_TypeDef *ADCx, uint32_t Channel)
3310{
3311#if defined(ADC_VER_V5_V90)
3312 if (ADCx != ADC3)
3313 {
3314 /* ADC channels preselection */
3315 ADCx->PCSEL_RES0 |= (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(Channel) & 0x1FUL));
3316 }
3317#else
3318 /* ADC channels preselection */
3319 ADCx->PCSEL |= (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(Channel) & 0x1FUL));
3320#endif /* ADC_VER_V5_V90 */
3321}
3322
3354__STATIC_INLINE uint32_t LL_ADC_GetChannelPreselection(ADC_TypeDef *ADCx, uint32_t Channel)
3355{
3356#if defined(ADC_VER_V5_V90)
3357 if (ADCx != ADC3)
3358 {
3359 /* Gets preselected ADC channel */
3360 return (uint32_t)(READ_BIT(ADCx->PCSEL_RES0, 1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(Channel) & 0x1FUL)));
3361 }
3362 else
3363 {
3364 return 0UL;
3365 }
3366#else
3367 /* Gets preselected ADC channel */
3368 return (uint32_t)(READ_BIT(ADCx->PCSEL, 1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(Channel) & 0x1FUL)));
3369#endif /* ADC_VER_V5_V90 */
3370}
3371
3445__STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t Channel, uint32_t OffsetLevel)
3446{
3447 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3448#if defined(ADC_VER_V5_V90)
3449 if (ADCx == ADC3)
3450 {
3451 MODIFY_REG(*preg,
3452 ADC3_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1,
3453 ADC3_OFR1_OFFSET1_EN | (Channel & ADC_CHANNEL_ID_NUMBER_MASK) | OffsetLevel);
3454 }
3455 else
3456#endif /* ADC_VER_V5_V90 */
3457 {
3458 MODIFY_REG(*preg,
3459 ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1,
3460 (Channel & ADC_CHANNEL_ID_NUMBER_MASK) | OffsetLevel);
3461 }
3462}
3463
3527__STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(ADC_TypeDef *ADCx, uint32_t Offsety)
3528{
3529 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3530
3531 return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_CH);
3532}
3533
3553__STATIC_INLINE uint32_t LL_ADC_GetOffsetLevel(ADC_TypeDef *ADCx, uint32_t Offsety)
3554{
3555 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3556
3557 return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1);
3558}
3559
3560
3576__STATIC_INLINE void LL_ADC_SetDataRightShift(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t RigthShift)
3577{
3578 MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_RSHIFT1 | ADC_CFGR2_RSHIFT2 | ADC_CFGR2_RSHIFT3 | ADC_CFGR2_RSHIFT4), RigthShift << (Offsety & 0x1FUL));
3579}
3580
3595__STATIC_INLINE uint32_t LL_ADC_GetDataRightShift(ADC_TypeDef *ADCx, uint32_t Offsety)
3596{
3597 return (uint32_t)((READ_BIT(ADCx->CFGR2, (ADC_CFGR2_RSHIFT1 << (Offsety & 0x1FUL)))) >> (Offsety & 0x1FUL));
3598}
3599
3618__STATIC_INLINE void LL_ADC_SetOffsetSignedSaturation(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetSignedSaturation)
3619{
3620#if defined(ADC_VER_V5_V90)
3621 if (ADCx == ADC3)
3622 {
3623 /* Function not available on this instance */
3624 }
3625 else
3626#endif /* ADC_VER_V5_V90 */
3627 {
3628 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3629 MODIFY_REG(*preg, ADC_OFR1_SSATE, OffsetSignedSaturation);
3630 }
3631}
3632
3650__STATIC_INLINE uint32_t LL_ADC_GetOffsetSignedSaturation(ADC_TypeDef *ADCx, uint32_t Offsety)
3651{
3652#if defined(ADC_VER_V5_V90)
3653 if (ADCx == ADC3)
3654 {
3655 /* Function not available on this instance */
3656 return 0UL;
3657 }
3658 else
3659#endif /* ADC_VER_V5_V90 */
3660 {
3661 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3662 return (uint32_t) READ_BIT(*preg, ADC_OFR1_SSATE);
3663 }
3664}
3665
3666#if defined(ADC_VER_V5_V90)
3689__STATIC_INLINE void LL_ADC_SetOffsetSaturation(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetSaturation)
3690{
3691 if (ADCx == ADC3)
3692 {
3693 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3694
3695 MODIFY_REG(*preg,
3696 ADC3_OFR1_SATEN,
3697 OffsetSaturation);
3698 }
3699}
3700
3718__STATIC_INLINE uint32_t LL_ADC_GetOffsetSaturation(ADC_TypeDef *ADCx, uint32_t Offsety)
3719{
3720 if (ADCx == ADC3)
3721 {
3722 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3723
3724 return (uint32_t) READ_BIT(*preg, ADC3_OFR1_SATEN);
3725 }else
3726 {
3727 return 0UL;
3728 }
3729}
3730
3753__STATIC_INLINE void LL_ADC_SetOffsetSign(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetSign)
3754{
3755 if (ADCx == ADC3)
3756 {
3757 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3758
3759 MODIFY_REG(*preg,
3760 ADC3_OFR1_OFFSETPOS,
3761 OffsetSign);
3762 }
3763}
3764
3782__STATIC_INLINE uint32_t LL_ADC_GetOffsetSign(ADC_TypeDef *ADCx, uint32_t Offsety)
3783{
3784 if (ADCx == ADC3)
3785 {
3786 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3787
3788 return (uint32_t) READ_BIT(*preg, ADC3_OFR1_OFFSETPOS);
3789 }
3790 else
3791 {
3792 return 0UL;
3793 }
3794}
3795
3822__STATIC_INLINE void LL_ADC_SetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetState)
3823{
3824 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3825 if (ADCx == ADC3)
3826 {
3827 MODIFY_REG(*preg,
3828 ADC3_OFR1_OFFSET1_EN,
3829 OffsetState);
3830 }
3831 else
3832 {
3833 MODIFY_REG(*preg,
3834 ADC_OFR1_SSATE,
3835 OffsetState);
3836 }
3837}
3838
3856__STATIC_INLINE uint32_t LL_ADC_GetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety)
3857{
3858 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3859 if (ADCx == ADC3)
3860 {
3861 return (uint32_t) READ_BIT(*preg, ADC3_OFR1_OFFSET1_EN);
3862 }
3863 else
3864 {
3865 return (uint32_t) READ_BIT(*preg, ADC_OFR1_SSATE);
3866 }
3867}
3868
3869#endif /* ADC_VER_V5_V90 */
3870
3924__STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
3925{
3926 MODIFY_REG(ADCx->CFGR, ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL, TriggerSource);
3927}
3928
3968__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx)
3969{
3970 __IO uint32_t TriggerSource = READ_BIT(ADCx->CFGR, ADC_CFGR_EXTSEL | ADC_CFGR_EXTEN);
3971
3972 /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
3973 /* corresponding to ADC_CFGR_EXTEN {0; 1; 2; 3}. */
3974 uint32_t ShiftExten = ((TriggerSource & ADC_CFGR_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2UL));
3975
3976 /* Set bitfield corresponding to ADC_CFGR_EXTEN and ADC_CFGR_EXTSEL */
3977 /* to match with triggers literals definition. */
3978 return ((TriggerSource
3979 & (ADC_REG_TRIG_SOURCE_MASK >> ShiftExten) & ADC_CFGR_EXTSEL)
3980 | ((ADC_REG_TRIG_EDGE_MASK >> ShiftExten) & ADC_CFGR_EXTEN)
3981 );
3982}
3983
3995__STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
3996{
3997 return ((READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN)) ? 1UL : 0UL);
3998}
3999
4015__STATIC_INLINE void LL_ADC_REG_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
4016{
4017 MODIFY_REG(ADCx->CFGR, ADC_CFGR_EXTEN, ExternalTriggerEdge);
4018}
4019
4030__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(ADC_TypeDef *ADCx)
4031{
4032 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN));
4033}
4034
4035#if defined(ADC_VER_V5_V90)
4054__STATIC_INLINE void LL_ADC_REG_SetSamplingMode(ADC_TypeDef *ADCx, uint32_t SamplingMode)
4055{
4056 if (ADCx != ADC3)
4057 {
4058 /* Function not available on this instance */
4059 }
4060 else
4061 {
4062 MODIFY_REG(ADCx->CFGR2, ADC3_CFGR2_BULB | ADC3_CFGR2_SMPTRIG, SamplingMode);
4063 }
4064}
4065#endif /* ADC_VER_V5_V90 */
4066
4121__STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
4122{
4123 MODIFY_REG(ADCx->SQR1, ADC_SQR1_L, SequencerNbRanks);
4124}
4125
4175__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(ADC_TypeDef *ADCx)
4176{
4177 return (uint32_t)(READ_BIT(ADCx->SQR1, ADC_SQR1_L));
4178}
4179
4207__STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
4208{
4209 MODIFY_REG(ADCx->CFGR, ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM, SeqDiscont);
4210}
4211
4230__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx)
4231{
4232 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM));
4233}
4234
4322__STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
4323{
4324 /* Set bits with content of parameter "Channel" with bits position */
4325 /* in register and register position depending on parameter "Rank". */
4326 /* Parameters "Rank" and "Channel" are used with masks because containing */
4327 /* other bits reserved for other purpose. */
4328 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS));
4329
4330 MODIFY_REG(*preg,
4331 ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK),
4332 ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_REG_RANK_ID_SQRX_MASK));
4333}
4334
4424__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
4425{
4426 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS));
4427
4428 return (uint32_t)((READ_BIT(*preg,
4429 ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK))
4430 >> (Rank & ADC_REG_RANK_ID_SQRX_MASK)) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS
4431 );
4432}
4433
4453__STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous)
4454{
4455 MODIFY_REG(ADCx->CFGR, ADC_CFGR_CONT, Continuous);
4456}
4457
4470__STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(ADC_TypeDef *ADCx)
4471{
4472 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_CONT));
4473}
4486__STATIC_INLINE void LL_ADC_REG_SetDataTransferMode(ADC_TypeDef *ADCx, uint32_t DataTransferMode)
4487{
4488 MODIFY_REG(ADCx->CFGR, ADC_CFGR_DMNGT, DataTransferMode);
4489}
4490
4491#if defined(ADC_VER_V5_V90)
4498__STATIC_INLINE void LL_ADC_EnableDMAReq (ADC_TypeDef *ADCx)
4499{
4500 SET_BIT(ADCx->CFGR, ADC3_CFGR_DMAEN);
4501}
4502
4503__STATIC_INLINE void LL_ADC_DisableDMAReq(ADC_TypeDef *ADCx)
4504{
4505 CLEAR_BIT (ADCx->CFGR, ADC3_CFGR_DMAEN);
4506}
4507
4508__STATIC_INLINE uint32_t LL_ADC_IsEnabledDMAReq (ADC_TypeDef *ADCx)
4509{
4510 return ((READ_BIT(ADCx->CFGR, ADC3_CFGR_DMAEN) == (ADC3_CFGR_DMAEN)) ? 1UL : 0UL);
4511}
4547__STATIC_INLINE void LL_ADC_REG_SetDMATransferMode(ADC_TypeDef *ADCx, uint32_t DMATransfer)
4548{
4549 if (ADCx == ADC3)
4550 {
4551 MODIFY_REG(ADCx->CFGR, ADC3_CFGR_DMAEN | ADC3_CFGR_DMACFG, DMATransfer);
4552 }
4553}
4554
4585__STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransferMode(ADC_TypeDef *ADCx)
4586{
4587 if (ADCx == ADC3)
4588 {
4589 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC3_CFGR_DMAEN | ADC3_CFGR_DMACFG));
4590 }
4591 else
4592 {
4593 return 0UL;
4594 }
4595}
4596
4597#endif /* ADC_VER_V5_V90 */
4598
4614__STATIC_INLINE uint32_t LL_ADC_REG_GetDataTransferMode(ADC_TypeDef *ADCx)
4615{
4616 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DMNGT));
4617}
4618
4619
4640__STATIC_INLINE void LL_ADC_REG_SetOverrun(ADC_TypeDef *ADCx, uint32_t Overrun)
4641{
4642 MODIFY_REG(ADCx->CFGR, ADC_CFGR_OVRMOD, Overrun);
4643}
4644
4654__STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(ADC_TypeDef *ADCx)
4655{
4656 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_OVRMOD));
4657}
4658
4712__STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
4713{
4714 MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN, TriggerSource);
4715}
4716
4756__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(ADC_TypeDef *ADCx)
4757{
4758 __IO uint32_t TriggerSource = READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN);
4759
4760 /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
4761 /* corresponding to ADC_JSQR_JEXTEN {0; 1; 2; 3}. */
4762 uint32_t ShiftJexten = ((TriggerSource & ADC_JSQR_JEXTEN) >> (ADC_INJ_TRIG_EXTEN_BITOFFSET_POS - 2UL));
4763
4764 /* Set bitfield corresponding to ADC_JSQR_JEXTEN and ADC_JSQR_JEXTSEL */
4765 /* to match with triggers literals definition. */
4766 return ((TriggerSource
4767 & (ADC_INJ_TRIG_SOURCE_MASK >> ShiftJexten) & ADC_JSQR_JEXTSEL)
4768 | ((ADC_INJ_TRIG_EDGE_MASK >> ShiftJexten) & ADC_JSQR_JEXTEN)
4769 );
4770}
4771
4783__STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
4784{
4785 return ((READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN) == (LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN)) ? 1UL : 0UL);
4786}
4787
4803__STATIC_INLINE void LL_ADC_INJ_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
4804{
4805 MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTEN, ExternalTriggerEdge);
4806}
4807
4818__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerEdge(ADC_TypeDef *ADCx)
4819{
4820 return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN));
4821}
4822
4844__STATIC_INLINE void LL_ADC_INJ_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
4845{
4846 MODIFY_REG(ADCx->JSQR, ADC_JSQR_JL, SequencerNbRanks);
4847}
4848
4865__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerLength(ADC_TypeDef *ADCx)
4866{
4867 return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JL));
4868}
4869
4883__STATIC_INLINE void LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
4884{
4885 MODIFY_REG(ADCx->CFGR, ADC_CFGR_JDISCEN, SeqDiscont);
4886}
4887
4898__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef *ADCx)
4899{
4900 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JDISCEN));
4901}
4902
4961__STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
4962{
4963 /* Set bits with content of parameter "Channel" with bits position */
4964 /* in register depending on parameter "Rank". */
4965 /* Parameters "Rank" and "Channel" are used with masks because containing */
4966 /* other bits reserved for other purpose. */
4967 MODIFY_REG(ADCx->JSQR,
4968 (ADC_CHANNEL_ID_NUMBER_MASK >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK),
4969 ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK));
4970}
4971
5033__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
5034{
5035 return (uint32_t)((READ_BIT(ADCx->JSQR,
5036 (ADC_CHANNEL_ID_NUMBER_MASK >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK))
5037 >> (Rank & ADC_INJ_RANK_ID_JSQR_MASK)) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS
5038 );
5039}
5040
5071__STATIC_INLINE void LL_ADC_INJ_SetTrigAuto(ADC_TypeDef *ADCx, uint32_t TrigAuto)
5072{
5073 MODIFY_REG(ADCx->CFGR, ADC_CFGR_JAUTO, TrigAuto);
5074}
5075
5085__STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(ADC_TypeDef *ADCx)
5086{
5087 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JAUTO));
5088}
5089
5131__STATIC_INLINE void LL_ADC_INJ_SetQueueMode(ADC_TypeDef *ADCx, uint32_t QueueMode)
5132{
5133 MODIFY_REG(ADCx->CFGR, ADC_CFGR_JQM | ADC_CFGR_JQDIS, QueueMode);
5134}
5135
5146__STATIC_INLINE uint32_t LL_ADC_INJ_GetQueueMode(ADC_TypeDef *ADCx)
5147{
5148 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JQM | ADC_CFGR_JQDIS));
5149}
5150
5347__STATIC_INLINE void LL_ADC_INJ_ConfigQueueContext(ADC_TypeDef *ADCx,
5348 uint32_t TriggerSource,
5349 uint32_t ExternalTriggerEdge,
5350 uint32_t SequencerNbRanks,
5351 uint32_t Rank1_Channel,
5352 uint32_t Rank2_Channel,
5353 uint32_t Rank3_Channel,
5354 uint32_t Rank4_Channel)
5355{
5356 /* Set bits with content of parameter "Rankx_Channel" with bits position */
5357 /* in register depending on literal "LL_ADC_INJ_RANK_x". */
5358 /* Parameters "Rankx_Channel" and "LL_ADC_INJ_RANK_x" are used with masks */
5359 /* because containing other bits reserved for other purpose. */
5360 /* If parameter "TriggerSource" is set to SW start, then parameter */
5361 /* "ExternalTriggerEdge" is discarded. */
5362 uint32_t is_trigger_not_sw = (uint32_t)((TriggerSource != LL_ADC_INJ_TRIG_SOFTWARE) ? 1UL : 0UL);
5363 MODIFY_REG(ADCx->JSQR,
5364 ADC_JSQR_JEXTSEL |
5365 ADC_JSQR_JEXTEN |
5366 ADC_JSQR_JSQ4 |
5367 ADC_JSQR_JSQ3 |
5368 ADC_JSQR_JSQ2 |
5369 ADC_JSQR_JSQ1 |
5370 ADC_JSQR_JL,
5371 (TriggerSource & ADC_JSQR_JEXTSEL) |
5372 (ExternalTriggerEdge * (is_trigger_not_sw)) |
5373 (((Rank4_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_4 & ADC_INJ_RANK_ID_JSQR_MASK)) |
5374 (((Rank3_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_3 & ADC_INJ_RANK_ID_JSQR_MASK)) |
5375 (((Rank2_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_2 & ADC_INJ_RANK_ID_JSQR_MASK)) |
5376 (((Rank1_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_1 & ADC_INJ_RANK_ID_JSQR_MASK)) |
5377 SequencerNbRanks
5378 );
5379}
5380
5478__STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime)
5479{
5480 /* Set bits with content of parameter "SamplingTime" with bits position */
5481 /* in register and register position depending on parameter "Channel". */
5482 /* Parameter "Channel" is used with masks because containing */
5483 /* other bits reserved for other purpose. */
5484 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS));
5485
5486 MODIFY_REG(*preg,
5487 ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS),
5488 SamplingTime << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS));
5489}
5490
5563__STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel)
5564{
5565 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS));
5566
5567 return (uint32_t)(READ_BIT(*preg,
5568 ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS))
5569 >> ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS)
5570 );
5571}
5572
5624__STATIC_INLINE void LL_ADC_SetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SingleDiff)
5625{
5626#if defined(ADC_VER_V5_V90)
5627 /* Bits of channels in single or differential mode are set only for */
5628 /* differential mode (for single mode, mask of bits allowed to be set is */
5629 /* shifted out of range of bits of channels in single or differential mode. */
5630 if (ADCx == ADC3)
5631 {
5632 MODIFY_REG(ADCx->LTR2_DIFSEL,
5633 Channel & ADC_SINGLEDIFF_CHANNEL_MASK,
5634 (Channel & ADC_SINGLEDIFF_CHANNEL_MASK) & (ADC_DIFSEL_DIFSEL >> (SingleDiff & ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK)));
5635 }
5636 else
5637 {
5638 MODIFY_REG(ADCx->DIFSEL_RES12,
5639 Channel & ADC_SINGLEDIFF_CHANNEL_MASK,
5640 (Channel & ADC_SINGLEDIFF_CHANNEL_MASK) & (ADC_DIFSEL_DIFSEL >> (SingleDiff & ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK)));
5641 }
5642#else /* ADC_VER_V5_V90 */
5643 /* Bits of channels in single or differential mode are set only for */
5644 /* differential mode (for single mode, mask of bits allowed to be set is */
5645 /* shifted out of range of bits of channels in single or differential mode. */
5646 MODIFY_REG(ADCx->DIFSEL,
5647 Channel & ADC_SINGLEDIFF_CHANNEL_MASK,
5648 (Channel & ADC_SINGLEDIFF_CHANNEL_MASK) & (ADC_DIFSEL_DIFSEL >> (SingleDiff & ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK)));
5649#endif /* ADC_VER_V5_V90 */
5650}
5651
5695__STATIC_INLINE uint32_t LL_ADC_GetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel)
5696{
5697#if defined(ADC_VER_V5_V90)
5698 return (uint32_t)(READ_BIT(ADCx->DIFSEL_RES12, (Channel & ADC_SINGLEDIFF_CHANNEL_MASK)));
5699#else
5700 return (uint32_t)(READ_BIT(ADCx->DIFSEL, (Channel & ADC_SINGLEDIFF_CHANNEL_MASK)));
5701#endif /* ADC_VER_V5_V90 */
5702}
5703
5844__STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDChannelGroup)
5845{
5846 /* Set bits with content of parameter "AWDChannelGroup" with bits position */
5847 /* in register and register position depending on parameter "AWDy". */
5848 /* Parameters "AWDChannelGroup" and "AWDy" are used with masks because */
5849 /* containing other bits reserved for other purpose. */
5850 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS)
5851 + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL));
5852
5853 MODIFY_REG(*preg,
5854 (AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK),
5855 AWDChannelGroup & AWDy);
5856}
5857
5983__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy)
5984{
5985 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS)
5986 + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL));
5987
5988 uint32_t AnalogWDMonitChannels = (READ_BIT(*preg, AWDy) & AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK);
5989
5990 /* If "AnalogWDMonitChannels" == 0, then the selected AWD is disabled */
5991 /* (parameter value LL_ADC_AWD_DISABLE). */
5992 /* Else, the selected AWD is enabled and is monitoring a group of channels */
5993 /* or a single channel. */
5994 if (AnalogWDMonitChannels != 0UL)
5995 {
5996 if (AWDy == LL_ADC_AWD1)
5997 {
5998 if ((AnalogWDMonitChannels & ADC_CFGR_AWD1SGL) == 0UL)
5999 {
6000 /* AWD monitoring a group of channels */
6001 AnalogWDMonitChannels = ((AnalogWDMonitChannels
6002 | (ADC_AWD_CR23_CHANNEL_MASK)
6003 )
6004 & (~(ADC_CFGR_AWD1CH))
6005 );
6006 }
6007 else
6008 {
6009 /* AWD monitoring a single channel */
6010 AnalogWDMonitChannels = (AnalogWDMonitChannels
6011 | (ADC_AWD2CR_AWD2CH_0 << (AnalogWDMonitChannels >> ADC_CFGR_AWD1CH_Pos))
6012 );
6013 }
6014 }
6015 else
6016 {
6017 if ((AnalogWDMonitChannels & ADC_AWD_CR23_CHANNEL_MASK) == ADC_AWD_CR23_CHANNEL_MASK)
6018 {
6019 /* AWD monitoring a group of channels */
6020 AnalogWDMonitChannels = (ADC_AWD_CR23_CHANNEL_MASK
6021 | ((ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN))
6022 );
6023 }
6024 else
6025 {
6026 /* AWD monitoring a single channel */
6027 /* AWD monitoring a group of channels */
6028 AnalogWDMonitChannels = (AnalogWDMonitChannels
6029 | (ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
6030 | (__LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDMonitChannels) << ADC_CFGR_AWD1CH_Pos)
6031 );
6032 }
6033 }
6034 }
6035
6036 return AnalogWDMonitChannels;
6037}
6038
6092__STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue)
6093{
6094#if defined(ADC_VER_V5_V90)
6095 if (ADCx == ADC3)
6096 {
6097 /* Set bits with content of parameter "AWDThresholdValue" with bits */
6098 /* position in register and register position depending on parameters */
6099 /* "AWDThresholdsHighLow" and "AWDy". */
6100 /* Parameters "AWDy" and "AWDThresholdValue" are used with masks because */
6101 /* containing other bits reserved for other purpose. */
6102 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->LTR1_TR1, ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS));
6103
6104 MODIFY_REG(*preg,
6105 (ADC3_TR1_LT1 << (AWDThresholdsHighLow * ADC3_TR1_HT1_Pos)),
6106 AWDThresholdValue << (((AWDThresholdsHighLow * ADC3_TR1_HT1) & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4));
6107 }
6108 else
6109 {
6110 /* Set bits with content of parameter "AWDThresholdValue" with bits */
6111 /* position in register and register position depending on parameters */
6112 /* "AWDThresholdsHighLow" and "AWDy". */
6113 /* Parameters "AWDy" and "AWDThresholdValue" are used with masks because */
6114 /* containing other bits reserved for other purpose. */
6115 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->LTR1_TR1, (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS) * 2UL)
6116 + ((AWDy & ADC_AWD_TR12_REGOFFSETGAP_MASK) * ADC_AWD_TR12_REGOFFSETGAP_VAL)
6117 + (AWDThresholdsHighLow));
6118
6119 MODIFY_REG(*preg, ADC_LTR_LT, AWDThresholdValue);
6120 }
6121#else
6122 /* Set bits with content of parameter "AWDThresholdValue" with bits */
6123 /* position in register and register position depending on parameters */
6124 /* "AWDThresholdsHighLow" and "AWDy". */
6125 /* Parameters "AWDy" and "AWDThresholdValue" are used with masks because */
6126 /* containing other bits reserved for other purpose. */
6127 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->LTR1, (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS) * 2UL)
6128 + ((AWDy & ADC_AWD_TR12_REGOFFSETGAP_MASK) * ADC_AWD_TR12_REGOFFSETGAP_VAL)
6129 + (AWDThresholdsHighLow));
6130
6131 MODIFY_REG(*preg, ADC_LTR_LT, AWDThresholdValue);
6132#endif /* ADC_VER_V5_V90 */
6133}
6134
6158__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow)
6159{
6160#if defined(ADC_VER_V5_V90)
6161 if (ADCx == ADC3)
6162 {
6163 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->LTR1_TR1,
6164 ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS));
6165
6166 return (uint32_t)(READ_BIT(*preg,
6167 (ADC3_TR1_LT1 << (AWDThresholdsHighLow * ADC3_TR1_HT1_Pos)))
6168 >> (((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4)
6169 & ~(AWDThresholdsHighLow & ADC3_TR1_LT1)));
6170 }
6171 else
6172 {
6173 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->LTR1_TR1, (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS) * 2UL)
6174 + ((AWDy & ADC_AWD_TR12_REGOFFSETGAP_MASK) * ADC_AWD_TR12_REGOFFSETGAP_VAL)
6175 + (AWDThresholdsHighLow));
6176
6177 return (uint32_t)(READ_BIT(*preg, ADC_LTR_LT));
6178 }
6179#else
6180 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->LTR1, (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS) * 2UL)
6181 + ((AWDy & ADC_AWD_TR12_REGOFFSETGAP_MASK) * ADC_AWD_TR12_REGOFFSETGAP_VAL)
6182 + (AWDThresholdsHighLow));
6183
6184 return (uint32_t)(READ_BIT(*preg, ADC_LTR_LT));
6185#endif /* ADC_VER_V5_V90 */
6186}
6187
6188#if defined(ADC_VER_V5_V90)
6189
6234__STATIC_INLINE void LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdHighValue, uint32_t AWDThresholdLowValue)
6235{
6236 /* Set bits with content of parameter "AWDThresholdxxxValue" with bits */
6237 /* position in register and register position depending on parameter */
6238 /* "AWDy". */
6239 /* Parameters "AWDy" and "AWDThresholdxxxValue" are used with masks because */
6240 /* containing other bits reserved for other purpose. */
6241 if (ADCx == ADC3)
6242 {
6243 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->LTR1_TR1,
6244 ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS));
6245
6246 MODIFY_REG(*preg,
6247 ADC3_TR1_HT1 | ADC3_TR1_LT1,
6248 (AWDThresholdHighValue << ADC3_TR1_HT1_Pos) | AWDThresholdLowValue);
6249 }
6250 else
6251 {
6252 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->LTR1_TR1, (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS) * 2UL)
6253 + ((AWDy & ADC_AWD_TR12_REGOFFSETGAP_MASK) * ADC_AWD_TR12_REGOFFSETGAP_VAL)
6254 + (LL_ADC_AWD_THRESHOLD_LOW));
6255 __IO uint32_t *preg2 = __ADC_PTR_REG_OFFSET(ADCx->LTR1_TR1, (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS) * 2UL)
6256 + ((AWDy & ADC_AWD_TR12_REGOFFSETGAP_MASK) * ADC_AWD_TR12_REGOFFSETGAP_VAL)
6257 + (LL_ADC_AWD_THRESHOLD_HIGH));
6258
6259 MODIFY_REG(*preg, ADC_LTR_LT, AWDThresholdLowValue);
6260 MODIFY_REG(*preg2, ADC_HTR_HT, AWDThresholdHighValue);
6261 }
6262}
6263
6264
6289__STATIC_INLINE void LL_ADC_SetAWDFilteringConfiguration(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t FilteringConfig)
6290{
6291 if (ADCx == ADC3)
6292 {
6293 /* Prevent unused argument(s) compilation warning */
6294 (void)(AWDy);
6295 MODIFY_REG(ADCx->LTR1_TR1, ADC3_TR1_AWDFILT, FilteringConfig);
6296 }
6297}
6298
6318__STATIC_INLINE uint32_t LL_ADC_GetAWDFilteringConfiguration(ADC_TypeDef *ADCx, uint32_t AWDy)
6319{
6320 if (ADCx == ADC3)
6321 {
6322 /* Prevent unused argument(s) compilation warning */
6323 (void)(AWDy);
6324 return (uint32_t)(READ_BIT(ADCx->LTR1_TR1, ADC3_TR1_AWDFILT));
6325 }
6326 else
6327 {
6328 /* Function not available on this instance, return 0 */
6329 return 0UL;
6330 }
6331}
6332#endif /* ADC_VER_V5_V90 */
6367__STATIC_INLINE void LL_ADC_SetOverSamplingScope(ADC_TypeDef *ADCx, uint32_t OvsScope)
6368{
6369 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM, OvsScope);
6370}
6371
6392__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingScope(ADC_TypeDef *ADCx)
6393{
6394 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM));
6395}
6396
6419__STATIC_INLINE void LL_ADC_SetOverSamplingDiscont(ADC_TypeDef *ADCx, uint32_t OverSamplingDiscont)
6420{
6421 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_TROVS, OverSamplingDiscont);
6422}
6423
6438__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingDiscont(ADC_TypeDef *ADCx)
6439{
6440 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_TROVS));
6441}
6442
6481__STATIC_INLINE void LL_ADC_ConfigOverSamplingRatioShift(ADC_TypeDef *ADCx, uint32_t Ratio, uint32_t Shift)
6482{
6483#if defined(ADC_VER_V5_V90)
6484 if(ADCx==ADC3)
6485 {
6486 MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_OVSS | ADC3_CFGR2_OVSR), (Shift | Ratio));
6487 }
6488 else
6489 {
6490 MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_OVSS | ADC_CFGR2_OVSR), (Shift | (((Ratio - 1UL) << ADC_CFGR2_OVSR_Pos))));
6491 }
6492#else
6493
6494 MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_OVSS | ADC_CFGR2_OVSR), (Shift | (((Ratio - 1UL) << ADC_CFGR2_OVSR_Pos))));
6495
6496#endif /* ADC_VER_V5_V90 */
6497}
6498
6515__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingRatio(ADC_TypeDef *ADCx)
6516{
6517#if defined(ADC_VER_V5_V90)
6518 if(ADCx==ADC3)
6519 {
6520 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC3_CFGR2_OVSR));
6521 }
6522 else
6523 {
6524 return (((uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSR)) + (1UL << ADC_CFGR2_OVSR_Pos)) >> ADC_CFGR2_OVSR_Pos);
6525 }
6526#else
6527
6528 return (((uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSR)) + (1UL << ADC_CFGR2_OVSR_Pos)) >> ADC_CFGR2_OVSR_Pos);
6529
6530#endif /* ADC_VER_V5_V90 */
6531}
6532
6552__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingShift(ADC_TypeDef *ADCx)
6553{
6554 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSS));
6555}
6556
6581__STATIC_INLINE void LL_ADC_SetBoostMode(ADC_TypeDef *ADCx, uint32_t BoostMode)
6582{
6583#if defined(ADC_VER_V5_V90)
6584 if (ADCx != ADC3)
6585 {
6586 MODIFY_REG(ADCx->CR, ADC_CR_BOOST, (BoostMode & ADC_CR_BOOST));
6587 }
6588#else /* ADC_VER_V5_V90 */
6589 if ((DBGMCU->IDCODE & 0x30000000UL) == 0x10000000UL) /* Cut 1.x */
6590 {
6591 MODIFY_REG(ADCx->CR, ADC_CR_BOOST_0, (BoostMode >> 2UL));
6592 }
6593 else /* Cut 2.x */
6594 {
6595 MODIFY_REG(ADCx->CR, ADC_CR_BOOST, (BoostMode & ADC_CR_BOOST));
6596 }
6597#endif /* ADC_VER_V5_V90 */
6598}
6599
6600
6611__STATIC_INLINE uint32_t LL_ADC_GetBoostMode(ADC_TypeDef *ADCx)
6612{
6613 if ((DBGMCU->IDCODE & 0x30000000UL) == 0x10000000UL) /* Cut 1.x */
6614 {
6615 return (uint32_t)READ_BIT(ADCx->CR, ADC_CR_BOOST_0);
6616 }
6617 else /* Cut 2.x */
6618 {
6619 return ((READ_BIT(ADCx->CR, ADC_CR_BOOST) == (ADC_CR_BOOST)) ? 1UL : 0UL);
6620 }
6621}
6622
6649__STATIC_INLINE void LL_ADC_SetMultimode(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t Multimode)
6650{
6651 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DUAL, Multimode);
6652}
6653
6673__STATIC_INLINE uint32_t LL_ADC_GetMultimode(ADC_Common_TypeDef *ADCxy_COMMON)
6674{
6675 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DUAL));
6676}
6677
6721__STATIC_INLINE void LL_ADC_SetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiDMATransfer)
6722{
6723 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DAMDF, MultiDMATransfer);
6724}
6725
6764__STATIC_INLINE uint32_t LL_ADC_GetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON)
6765{
6766 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DAMDF));
6767}
6768
6809__STATIC_INLINE void LL_ADC_SetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiTwoSamplingDelay)
6810{
6811 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DELAY, MultiTwoSamplingDelay);
6812}
6813
6842__STATIC_INLINE uint32_t LL_ADC_GetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON)
6843{
6844 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DELAY));
6845}
6846
6868__STATIC_INLINE void LL_ADC_EnableDeepPowerDown(ADC_TypeDef *ADCx)
6869{
6870 /* Note: Write register with some additional bits forced to state reset */
6871 /* instead of modifying only the selected bit for this function, */
6872 /* to not interfere with bits with HW property "rs". */
6873 MODIFY_REG(ADCx->CR,
6874 ADC_CR_BITS_PROPERTY_RS,
6875 ADC_CR_DEEPPWD);
6876}
6877
6891__STATIC_INLINE void LL_ADC_DisableDeepPowerDown(ADC_TypeDef *ADCx)
6892{
6893 /* Note: Write register with some additional bits forced to state reset */
6894 /* instead of modifying only the selected bit for this function, */
6895 /* to not interfere with bits with HW property "rs". */
6896 CLEAR_BIT(ADCx->CR, (ADC_CR_DEEPPWD | ADC_CR_BITS_PROPERTY_RS));
6897}
6898
6905__STATIC_INLINE uint32_t LL_ADC_IsDeepPowerDownEnabled(ADC_TypeDef *ADCx)
6906{
6907 return ((READ_BIT(ADCx->CR, ADC_CR_DEEPPWD) == (ADC_CR_DEEPPWD)) ? 1UL : 0UL);
6908}
6909
6924__STATIC_INLINE void LL_ADC_EnableInternalRegulator(ADC_TypeDef *ADCx)
6925{
6926 /* Note: Write register with some additional bits forced to state reset */
6927 /* instead of modifying only the selected bit for this function, */
6928 /* to not interfere with bits with HW property "rs". */
6929 MODIFY_REG(ADCx->CR,
6930 ADC_CR_BITS_PROPERTY_RS,
6931 ADC_CR_ADVREGEN);
6932}
6933
6943__STATIC_INLINE void LL_ADC_DisableInternalRegulator(ADC_TypeDef *ADCx)
6944{
6945 CLEAR_BIT(ADCx->CR, (ADC_CR_ADVREGEN | ADC_CR_BITS_PROPERTY_RS));
6946}
6947
6954__STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(ADC_TypeDef *ADCx)
6955{
6956 return ((READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)) ? 1UL : 0UL);
6957}
6958
6975__STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx)
6976{
6977 /* Note: Write register with some additional bits forced to state reset */
6978 /* instead of modifying only the selected bit for this function, */
6979 /* to not interfere with bits with HW property "rs". */
6980 MODIFY_REG(ADCx->CR,
6981 ADC_CR_BITS_PROPERTY_RS,
6982 ADC_CR_ADEN);
6983}
6984
6995__STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx)
6996{
6997 /* Note: Write register with some additional bits forced to state reset */
6998 /* instead of modifying only the selected bit for this function, */
6999 /* to not interfere with bits with HW property "rs". */
7000 MODIFY_REG(ADCx->CR,
7001 ADC_CR_BITS_PROPERTY_RS,
7002 ADC_CR_ADDIS);
7003}
7004
7014__STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx)
7015{
7016 return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL);
7017}
7018
7025__STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(ADC_TypeDef *ADCx)
7026{
7027 return ((READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS)) ? 1UL : 0UL);
7028}
7029
7063__STATIC_INLINE void LL_ADC_StartCalibration(ADC_TypeDef *ADCx, uint32_t CalibrationMode, uint32_t SingleDiff)
7064{
7065 /* Note: Write register with some additional bits forced to state reset */
7066 /* instead of modifying only the selected bit for this function, */
7067 /* to not interfere with bits with HW property "rs". */
7068 MODIFY_REG(ADCx->CR,
7069 ADC_CR_ADCALLIN | ADC_CR_ADCALDIF | ADC_CR_BITS_PROPERTY_RS,
7070 ADC_CR_ADCAL | (CalibrationMode & ADC_CALIB_MODE_MASK) | (SingleDiff & ADC_SINGLEDIFF_CALIB_START_MASK));
7071}
7072
7079__STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(ADC_TypeDef *ADCx)
7080{
7081 return ((READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL)) ? 1UL : 0UL);
7082}
7083
7111__STATIC_INLINE void LL_ADC_REG_StartConversion(ADC_TypeDef *ADCx)
7112{
7113 /* Note: Write register with some additional bits forced to state reset */
7114 /* instead of modifying only the selected bit for this function, */
7115 /* to not interfere with bits with HW property "rs". */
7116 MODIFY_REG(ADCx->CR,
7117 ADC_CR_BITS_PROPERTY_RS,
7118 ADC_CR_ADSTART);
7119}
7120
7131__STATIC_INLINE void LL_ADC_REG_StopConversion(ADC_TypeDef *ADCx)
7132{
7133 /* Note: Write register with some additional bits forced to state reset */
7134 /* instead of modifying only the selected bit for this function, */
7135 /* to not interfere with bits with HW property "rs". */
7136 MODIFY_REG(ADCx->CR,
7137 ADC_CR_BITS_PROPERTY_RS,
7138 ADC_CR_ADSTP);
7139}
7140
7147__STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(ADC_TypeDef *ADCx)
7148{
7149 return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL);
7150}
7151
7158__STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing(ADC_TypeDef *ADCx)
7159{
7160 return ((READ_BIT(ADCx->CR, ADC_CR_ADSTP) == (ADC_CR_ADSTP)) ? 1UL : 0UL);
7161}
7162
7172__STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(ADC_TypeDef *ADCx)
7173{
7174 return (uint32_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
7175}
7176
7187__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData16(ADC_TypeDef *ADCx)
7188{
7189 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
7190}
7191
7202__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData14(ADC_TypeDef *ADCx)
7203{
7204 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
7205}
7206
7217__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(ADC_TypeDef *ADCx)
7218{
7219 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
7220}
7221
7232__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(ADC_TypeDef *ADCx)
7233{
7234 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
7235}
7236
7247__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(ADC_TypeDef *ADCx)
7248{
7249 return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
7250}
7272__STATIC_INLINE uint32_t LL_ADC_REG_ReadMultiConversionData32(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t ConversionData)
7273{
7274 return (uint32_t)(READ_BIT(ADCxy_COMMON->CDR,
7275 ConversionData)
7276 >> (POSITION_VAL(ConversionData) & 0x1FUL)
7277 );
7278}
7279
7307__STATIC_INLINE void LL_ADC_INJ_StartConversion(ADC_TypeDef *ADCx)
7308{
7309 /* Note: Write register with some additional bits forced to state reset */
7310 /* instead of modifying only the selected bit for this function, */
7311 /* to not interfere with bits with HW property "rs". */
7312 MODIFY_REG(ADCx->CR,
7313 ADC_CR_BITS_PROPERTY_RS,
7314 ADC_CR_JADSTART);
7315}
7316
7327__STATIC_INLINE void LL_ADC_INJ_StopConversion(ADC_TypeDef *ADCx)
7328{
7329 /* Note: Write register with some additional bits forced to state reset */
7330 /* instead of modifying only the selected bit for this function, */
7331 /* to not interfere with bits with HW property "rs". */
7332 MODIFY_REG(ADCx->CR,
7333 ADC_CR_BITS_PROPERTY_RS,
7334 ADC_CR_JADSTP);
7335}
7336
7343__STATIC_INLINE uint32_t LL_ADC_INJ_IsConversionOngoing(ADC_TypeDef *ADCx)
7344{
7345 return ((READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART)) ? 1UL : 0UL);
7346}
7347
7354__STATIC_INLINE uint32_t LL_ADC_INJ_IsStopConversionOngoing(ADC_TypeDef *ADCx)
7355{
7356 return ((READ_BIT(ADCx->CR, ADC_CR_JADSTP) == (ADC_CR_JADSTP)) ? 1UL : 0UL);
7357}
7358
7376__STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint32_t Rank)
7377{
7378 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
7379
7380 return (uint32_t)(READ_BIT(*preg,
7381 ADC_JDR1_JDATA)
7382 );
7383}
7384
7403__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData16(ADC_TypeDef *ADCx, uint32_t Rank)
7404{
7405 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
7406
7407 return (uint16_t)(READ_BIT(*preg,
7408 ADC_JDR1_JDATA)
7409 );
7410}
7411
7430__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData14(ADC_TypeDef *ADCx, uint32_t Rank)
7431{
7432 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
7433
7434 return (uint16_t)(READ_BIT(*preg,
7435 ADC_JDR1_JDATA)
7436 );
7437}
7438
7457__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint32_t Rank)
7458{
7459 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
7460
7461 return (uint16_t)(READ_BIT(*preg,
7462 ADC_JDR1_JDATA)
7463 );
7464}
7465
7484__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(ADC_TypeDef *ADCx, uint32_t Rank)
7485{
7486 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
7487
7488 return (uint16_t)(READ_BIT(*preg,
7489 ADC_JDR1_JDATA)
7490 );
7491}
7492
7511__STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(ADC_TypeDef *ADCx, uint32_t Rank)
7512{
7513 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
7514
7515 return (uint8_t)(READ_BIT(*preg,
7516 ADC_JDR1_JDATA)
7517 );
7518}
7519
7538__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(ADC_TypeDef *ADCx)
7539{
7540 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_ADRDY) == (LL_ADC_FLAG_ADRDY)) ? 1UL : 0UL);
7541}
7542
7549__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC(ADC_TypeDef *ADCx)
7550{
7551 return ((READ_BIT(ADCx->ISR, ADC_ISR_EOC) == (ADC_ISR_EOC)) ? 1UL : 0UL);
7552}
7553
7560__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(ADC_TypeDef *ADCx)
7561{
7562 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOS) == (LL_ADC_FLAG_EOS)) ? 1UL : 0UL);
7563}
7564
7571__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(ADC_TypeDef *ADCx)
7572{
7573 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR)) ? 1UL : 0UL);
7574}
7575
7582__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP(ADC_TypeDef *ADCx)
7583{
7584 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOSMP) == (LL_ADC_FLAG_EOSMP)) ? 1UL : 0UL);
7585}
7586
7593__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOC(ADC_TypeDef *ADCx)
7594{
7595 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOC) == (LL_ADC_FLAG_JEOC)) ? 1UL : 0UL);
7596}
7597
7604__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(ADC_TypeDef *ADCx)
7605{
7606 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOS) == (LL_ADC_FLAG_JEOS)) ? 1UL : 0UL);
7607}
7608
7615__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JQOVF(ADC_TypeDef *ADCx)
7616{
7617 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JQOVF) == (LL_ADC_FLAG_JQOVF)) ? 1UL : 0UL);
7618}
7619
7626__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_LDORDY(ADC_TypeDef *ADCx)
7627{
7628 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_LDORDY) == (LL_ADC_FLAG_LDORDY)) ? 1UL : 0UL);
7629}
7630
7637__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef *ADCx)
7638{
7639 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1)) ? 1UL : 0UL);
7640}
7641
7648__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD2(ADC_TypeDef *ADCx)
7649{
7650 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD2) == (LL_ADC_FLAG_AWD2)) ? 1UL : 0UL);
7651}
7652
7659__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD3(ADC_TypeDef *ADCx)
7660{
7661 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD3) == (LL_ADC_FLAG_AWD3)) ? 1UL : 0UL);
7662}
7663
7673__STATIC_INLINE void LL_ADC_ClearFlag_ADRDY(ADC_TypeDef *ADCx)
7674{
7675 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_ADRDY);
7676}
7677
7684__STATIC_INLINE void LL_ADC_ClearFlag_EOC(ADC_TypeDef *ADCx)
7685{
7686 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOC);
7687}
7688
7695__STATIC_INLINE void LL_ADC_ClearFlag_EOS(ADC_TypeDef *ADCx)
7696{
7697 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOS);
7698}
7699
7706__STATIC_INLINE void LL_ADC_ClearFlag_OVR(ADC_TypeDef *ADCx)
7707{
7708 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_OVR);
7709}
7710
7717__STATIC_INLINE void LL_ADC_ClearFlag_EOSMP(ADC_TypeDef *ADCx)
7718{
7719 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOSMP);
7720}
7721
7728__STATIC_INLINE void LL_ADC_ClearFlag_JEOC(ADC_TypeDef *ADCx)
7729{
7730 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JEOC);
7731}
7732
7739__STATIC_INLINE void LL_ADC_ClearFlag_JEOS(ADC_TypeDef *ADCx)
7740{
7741 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JEOS);
7742}
7743
7750__STATIC_INLINE void LL_ADC_ClearFlag_JQOVF(ADC_TypeDef *ADCx)
7751{
7752 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JQOVF);
7753}
7754
7761__STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx)
7762{
7763 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD1);
7764}
7765
7772__STATIC_INLINE void LL_ADC_ClearFlag_AWD2(ADC_TypeDef *ADCx)
7773{
7774 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD2);
7775}
7776
7783__STATIC_INLINE void LL_ADC_ClearFlag_AWD3(ADC_TypeDef *ADCx)
7784{
7785 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD3);
7786}
7787
7795__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_ADRDY(ADC_Common_TypeDef *ADCxy_COMMON)
7796{
7797 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_ADRDY_MST) == (LL_ADC_FLAG_ADRDY_MST)) ? 1UL : 0UL);
7798}
7799
7807__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_ADRDY(ADC_Common_TypeDef *ADCxy_COMMON)
7808{
7809 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_ADRDY_SLV) == (LL_ADC_FLAG_ADRDY_SLV)) ? 1UL : 0UL);
7810}
7811
7819__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOC(ADC_Common_TypeDef *ADCxy_COMMON)
7820{
7821 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOC_SLV) == (LL_ADC_FLAG_EOC_SLV)) ? 1UL : 0UL);
7822}
7823
7831__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOC(ADC_Common_TypeDef *ADCxy_COMMON)
7832{
7833 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOC_SLV) == (LL_ADC_FLAG_EOC_SLV)) ? 1UL : 0UL);
7834}
7835
7843__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOS(ADC_Common_TypeDef *ADCxy_COMMON)
7844{
7845 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOS_MST) == (LL_ADC_FLAG_EOS_MST)) ? 1UL : 0UL);
7846}
7847
7855__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOS(ADC_Common_TypeDef *ADCxy_COMMON)
7856{
7857 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOS_SLV) == (LL_ADC_FLAG_EOS_SLV)) ? 1UL : 0UL);
7858}
7859
7867__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_OVR(ADC_Common_TypeDef *ADCxy_COMMON)
7868{
7869 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_MST) == (LL_ADC_FLAG_OVR_MST)) ? 1UL : 0UL);
7870}
7871
7879__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_OVR(ADC_Common_TypeDef *ADCxy_COMMON)
7880{
7881 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_SLV) == (LL_ADC_FLAG_OVR_SLV)) ? 1UL : 0UL);
7882}
7883
7891__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOSMP(ADC_Common_TypeDef *ADCxy_COMMON)
7892{
7893 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOSMP_MST) == (LL_ADC_FLAG_EOSMP_MST)) ? 1UL : 0UL);
7894}
7895
7903__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOSMP(ADC_Common_TypeDef *ADCxy_COMMON)
7904{
7905 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOSMP_SLV) == (LL_ADC_FLAG_EOSMP_SLV)) ? 1UL : 0UL);
7906}
7907
7915__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOC(ADC_Common_TypeDef *ADCxy_COMMON)
7916{
7917 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOC_MST) == (LL_ADC_FLAG_JEOC_MST)) ? 1UL : 0UL);
7918}
7919
7927__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOC(ADC_Common_TypeDef *ADCxy_COMMON)
7928{
7929 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOC_SLV) == (LL_ADC_FLAG_JEOC_SLV)) ? 1UL : 0UL);
7930}
7931
7939__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)
7940{
7941 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOS_MST) == (LL_ADC_FLAG_JEOS_MST)) ? 1UL : 0UL);
7942}
7943
7951__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)
7952{
7953 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOS_SLV) == (LL_ADC_FLAG_JEOS_SLV)) ? 1UL : 0UL);
7954}
7955
7963__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JQOVF(ADC_Common_TypeDef *ADCxy_COMMON)
7964{
7965 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JQOVF_MST) == (LL_ADC_FLAG_JQOVF_MST)) ? 1UL : 0UL);
7966}
7967
7975__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JQOVF(ADC_Common_TypeDef *ADCxy_COMMON)
7976{
7977 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JQOVF_SLV) == (LL_ADC_FLAG_JQOVF_SLV)) ? 1UL : 0UL);
7978}
7979
7987__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD1(ADC_Common_TypeDef *ADCxy_COMMON)
7988{
7989 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_MST) == (LL_ADC_FLAG_AWD1_MST)) ? 1UL : 0UL);
7990}
7991
7999__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD1(ADC_Common_TypeDef *ADCxy_COMMON)
8000{
8001 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_SLV) == (LL_ADC_FLAG_AWD1_SLV)) ? 1UL : 0UL);
8002}
8003
8011__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD2(ADC_Common_TypeDef *ADCxy_COMMON)
8012{
8013 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD2_MST) == (LL_ADC_FLAG_AWD2_MST)) ? 1UL : 0UL);
8014}
8015
8023__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD2(ADC_Common_TypeDef *ADCxy_COMMON)
8024{
8025 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD2_SLV) == (LL_ADC_FLAG_AWD2_SLV)) ? 1UL : 0UL);
8026}
8027
8035__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD3(ADC_Common_TypeDef *ADCxy_COMMON)
8036{
8037 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD3_MST) == (LL_ADC_FLAG_AWD3_MST)) ? 1UL : 0UL);
8038}
8039
8047__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD3(ADC_Common_TypeDef *ADCxy_COMMON)
8048{
8049 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD3_SLV) == (LL_ADC_FLAG_AWD3_SLV)) ? 1UL : 0UL);
8050}
8051
8067__STATIC_INLINE void LL_ADC_EnableIT_ADRDY(ADC_TypeDef *ADCx)
8068{
8069 SET_BIT(ADCx->IER, LL_ADC_IT_ADRDY);
8070}
8071
8078__STATIC_INLINE void LL_ADC_EnableIT_EOC(ADC_TypeDef *ADCx)
8079{
8080 SET_BIT(ADCx->IER, LL_ADC_IT_EOC);
8081}
8082
8089__STATIC_INLINE void LL_ADC_EnableIT_EOS(ADC_TypeDef *ADCx)
8090{
8091 SET_BIT(ADCx->IER, LL_ADC_IT_EOS);
8092}
8093
8100__STATIC_INLINE void LL_ADC_EnableIT_OVR(ADC_TypeDef *ADCx)
8101{
8102 SET_BIT(ADCx->IER, LL_ADC_IT_OVR);
8103}
8104
8111__STATIC_INLINE void LL_ADC_EnableIT_EOSMP(ADC_TypeDef *ADCx)
8112{
8113 SET_BIT(ADCx->IER, LL_ADC_IT_EOSMP);
8114}
8115
8122__STATIC_INLINE void LL_ADC_EnableIT_JEOC(ADC_TypeDef *ADCx)
8123{
8124 SET_BIT(ADCx->IER, LL_ADC_IT_JEOC);
8125}
8126
8133__STATIC_INLINE void LL_ADC_EnableIT_JEOS(ADC_TypeDef *ADCx)
8134{
8135 SET_BIT(ADCx->IER, LL_ADC_IT_JEOS);
8136}
8137
8144__STATIC_INLINE void LL_ADC_EnableIT_JQOVF(ADC_TypeDef *ADCx)
8145{
8146 SET_BIT(ADCx->IER, LL_ADC_IT_JQOVF);
8147}
8148
8155__STATIC_INLINE void LL_ADC_EnableIT_AWD1(ADC_TypeDef *ADCx)
8156{
8157 SET_BIT(ADCx->IER, LL_ADC_IT_AWD1);
8158}
8159
8166__STATIC_INLINE void LL_ADC_EnableIT_AWD2(ADC_TypeDef *ADCx)
8167{
8168 SET_BIT(ADCx->IER, LL_ADC_IT_AWD2);
8169}
8170
8177__STATIC_INLINE void LL_ADC_EnableIT_AWD3(ADC_TypeDef *ADCx)
8178{
8179 SET_BIT(ADCx->IER, LL_ADC_IT_AWD3);
8180}
8181
8188__STATIC_INLINE void LL_ADC_DisableIT_ADRDY(ADC_TypeDef *ADCx)
8189{
8190 CLEAR_BIT(ADCx->IER, LL_ADC_IT_ADRDY);
8191}
8192
8199__STATIC_INLINE void LL_ADC_DisableIT_EOC(ADC_TypeDef *ADCx)
8200{
8201 CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOC);
8202}
8203
8210__STATIC_INLINE void LL_ADC_DisableIT_EOS(ADC_TypeDef *ADCx)
8211{
8212 CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOS);
8213}
8214
8221__STATIC_INLINE void LL_ADC_DisableIT_OVR(ADC_TypeDef *ADCx)
8222{
8223 CLEAR_BIT(ADCx->IER, LL_ADC_IT_OVR);
8224}
8225
8232__STATIC_INLINE void LL_ADC_DisableIT_EOSMP(ADC_TypeDef *ADCx)
8233{
8234 CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOSMP);
8235}
8236
8243__STATIC_INLINE void LL_ADC_DisableIT_JEOC(ADC_TypeDef *ADCx)
8244{
8245 CLEAR_BIT(ADCx->IER, LL_ADC_IT_JEOC);
8246}
8247
8254__STATIC_INLINE void LL_ADC_DisableIT_JEOS(ADC_TypeDef *ADCx)
8255{
8256 CLEAR_BIT(ADCx->IER, LL_ADC_IT_JEOS);
8257}
8258
8265__STATIC_INLINE void LL_ADC_DisableIT_JQOVF(ADC_TypeDef *ADCx)
8266{
8267 CLEAR_BIT(ADCx->IER, LL_ADC_IT_JQOVF);
8268}
8269
8276__STATIC_INLINE void LL_ADC_DisableIT_AWD1(ADC_TypeDef *ADCx)
8277{
8278 CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD1);
8279}
8280
8287__STATIC_INLINE void LL_ADC_DisableIT_AWD2(ADC_TypeDef *ADCx)
8288{
8289 CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD2);
8290}
8291
8298__STATIC_INLINE void LL_ADC_DisableIT_AWD3(ADC_TypeDef *ADCx)
8299{
8300 CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD3);
8301}
8302
8310__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY(ADC_TypeDef *ADCx)
8311{
8312 return ((READ_BIT(ADCx->IER, LL_ADC_IT_ADRDY) == (LL_ADC_IT_ADRDY)) ? 1UL : 0UL);
8313}
8314
8322__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC(ADC_TypeDef *ADCx)
8323{
8324 return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOC) == (LL_ADC_IT_EOC)) ? 1UL : 0UL);
8325}
8326
8334__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(ADC_TypeDef *ADCx)
8335{
8336 return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOS) == (LL_ADC_IT_EOS)) ? 1UL : 0UL);
8337}
8338
8346__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(ADC_TypeDef *ADCx)
8347{
8348 return ((READ_BIT(ADCx->IER, LL_ADC_IT_OVR) == (LL_ADC_IT_OVR)) ? 1UL : 0UL);
8349}
8350
8358__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP(ADC_TypeDef *ADCx)
8359{
8360 return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOSMP) == (LL_ADC_IT_EOSMP)) ? 1UL : 0UL);
8361}
8362
8370__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOC(ADC_TypeDef *ADCx)
8371{
8372 return ((READ_BIT(ADCx->IER, LL_ADC_IT_JEOC) == (LL_ADC_IT_JEOC)) ? 1UL : 0UL);
8373}
8374
8382__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(ADC_TypeDef *ADCx)
8383{
8384 return ((READ_BIT(ADCx->IER, LL_ADC_IT_JEOS) == (LL_ADC_IT_JEOS)) ? 1UL : 0UL);
8385}
8386
8394__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JQOVF(ADC_TypeDef *ADCx)
8395{
8396 return ((READ_BIT(ADCx->IER, LL_ADC_IT_JQOVF) == (LL_ADC_IT_JQOVF)) ? 1UL : 0UL);
8397}
8398
8406__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef *ADCx)
8407{
8408 return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1)) ? 1UL : 0UL);
8409}
8410
8418__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD2(ADC_TypeDef *ADCx)
8419{
8420 return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD2) == (LL_ADC_IT_AWD2)) ? 1UL : 0UL);
8421}
8422
8430__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD3(ADC_TypeDef *ADCx)
8431{
8432 return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD3) == (LL_ADC_IT_AWD3)) ? 1UL : 0UL);
8433}
8434
8439#if defined(USE_FULL_LL_DRIVER) || defined(__rtems__)
8445/* Initialization of some features of ADC common parameters and multimode */
8446ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON);
8447ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);
8448void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);
8449
8450/* De-initialization of ADC instance, ADC group regular and ADC group injected */
8451/* (availability of ADC group injected depends on STM32 families) */
8452ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx);
8453
8454/* Initialization of some features of ADC instance */
8455ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct);
8456void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct);
8457
8458/* Initialization of some features of ADC instance and ADC group regular */
8459ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
8460void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
8461
8462/* Initialization of some features of ADC instance and ADC group injected */
8463ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);
8464void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);
8465
8469#endif /* USE_FULL_LL_DRIVER */
8470
8479#endif /* ADC1 || ADC2 || ADC3 */
8480
8485#ifdef __cplusplus
8486}
8487#endif
8488
8489#endif /* STM32H7xx_LL_ADC_H */
8490
__IO
#define __IO
Definition: core_cm4.h:239
ADC_SMPR1_SMP0
#define ADC_SMPR1_SMP0
Definition: stm32h723xx.h:3032
ADC3_CFGR_DMAEN
#define ADC3_CFGR_DMAEN
Definition: stm32h723xx.h:2941
ADC_CCR_CKMODE
#define ADC_CCR_CKMODE
Definition: stm32h723xx.h:4086
ADC_CALFACT_CALFACT_S
#define ADC_CALFACT_CALFACT_S
Definition: stm32h723xx.h:3928
ADC_CCR_PRESC
#define ADC_CCR_PRESC
Definition: stm32h723xx.h:4092
ADC_CFGR_JAUTO
#define ADC_CFGR_JAUTO
Definition: stm32h723xx.h:2924
ADC_OFR1_OFFSET1_CH
#define ADC_OFR1_OFFSET1_CH
Definition: stm32h723xx.h:3491
ADC_CFGR_DISCEN
#define ADC_CFGR_DISCEN
Definition: stm32h723xx.h:2898
ADC_CALFACT2_LINCALFACT
#define ADC_CALFACT2_LINCALFACT
Definition: stm32h723xx.h:3958
ADC_CR_ADSTART
#define ADC_CR_ADSTART
Definition: stm32h723xx.h:2808
ADC_CR_ADEN
#define ADC_CR_ADEN
Definition: stm32h723xx.h:2802
ADC_CR_JADSTART
#define ADC_CR_JADSTART
Definition: stm32h723xx.h:2811
ADC_CR_ADCALLIN
#define ADC_CR_ADCALLIN
Definition: stm32h723xx.h:2825
ADC3_OFR1_OFFSETPOS
#define ADC3_OFR1_OFFSETPOS
Definition: stm32h723xx.h:3508
ADC_JSQR_JSQ4
#define ADC_JSQR_JSQ4
Definition: stm32h723xx.h:3451
ADC_CFGR2_TROVS
#define ADC_CFGR2_TROVS
Definition: stm32h723xx.h:2973
ADC_JSQR_JSQ2
#define ADC_JSQR_JSQ2
Definition: stm32h723xx.h:3433
ADC3_CFGR2_BULB
#define ADC3_CFGR2_BULB
Definition: stm32h723xx.h:3025
ADC3_CFGR2_OVSR
#define ADC3_CFGR2_OVSR
Definition: stm32h723xx.h:3015
ADC3_TR1_AWDFILT
#define ADC3_TR1_AWDFILT
Definition: stm32h723xx.h:3213
ADC_CFGR_DISCNUM
#define ADC_CFGR_DISCNUM
Definition: stm32h723xx.h:2902
ADC_DIFSEL_DIFSEL
#define ADC_DIFSEL_DIFSEL
Definition: stm32h723xx.h:3903
ADC_CFGR_DMNGT
#define ADC_CFGR_DMNGT
Definition: stm32h723xx.h:2860
ADC3_TR1_LT1
#define ADC3_TR1_LT1
Definition: stm32h723xx.h:3209
ADC_CR_ADSTP
#define ADC_CR_ADSTP
Definition: stm32h723xx.h:2814
ADC_CFGR_RES_0
#define ADC_CFGR_RES_0
Definition: stm32h723xx.h:2867
ADC_CR_ADVREGEN
#define ADC_CR_ADVREGEN
Definition: stm32h723xx.h:2846
ADC3_CFGR_DMACFG
#define ADC3_CFGR_DMACFG
Definition: stm32h723xx.h:2944
ADC_CR_ADCALDIF
#define ADC_CR_ADCALDIF
Definition: stm32h723xx.h:2852
ADC_CFGR2_OVSS
#define ADC_CFGR2_OVSS
Definition: stm32h723xx.h:2965
ADC_CR_DEEPPWD
#define ADC_CR_DEEPPWD
Definition: stm32h723xx.h:2849
ADC_CFGR2_ROVSE
#define ADC_CFGR2_ROVSE
Definition: stm32h723xx.h:2958
ADC_CFGR2_JOVSE
#define ADC_CFGR2_JOVSE
Definition: stm32h723xx.h:2961
ADC_OFR1_SSATE
#define ADC_OFR1_SSATE
Definition: stm32h723xx.h:3500
ADC_CFGR2_OVSR
#define ADC_CFGR2_OVSR
Definition: stm32h723xx.h:2993
ADC_CFGR_AUTDLY
#define ADC_CFGR_AUTDLY
Definition: stm32h723xx.h:2894
ADC_CFGR2_RSHIFT4
#define ADC_CFGR2_RSHIFT4
Definition: stm32h723xx.h:2989
ADC_OFR1_OFFSET1
#define ADC_OFR1_OFFSET1
Definition: stm32h723xx.h:3461
ADC_CFGR_JAWD1EN
#define ADC_CFGR_JAWD1EN
Definition: stm32h723xx.h:2921
ADC_CFGR_JQDIS
#define ADC_CFGR_JQDIS
Definition: stm32h723xx.h:2937
ADC_CFGR2_RSHIFT3
#define ADC_CFGR2_RSHIFT3
Definition: stm32h723xx.h:2986
ADC_CFGR2_RSHIFT1
#define ADC_CFGR2_RSHIFT1
Definition: stm32h723xx.h:2980
ADC_JSQR_JEXTSEL
#define ADC_JSQR_JEXTSEL
Definition: stm32h723xx.h:3409
ADC3_OFR1_OFFSET1_EN
#define ADC3_OFR1_OFFSET1_EN
Definition: stm32h723xx.h:3515
ADC_CFGR_CONT
#define ADC_CFGR_CONT
Definition: stm32h723xx.h:2891
ADC3_CFGR2_SMPTRIG
#define ADC3_CFGR2_SMPTRIG
Definition: stm32h723xx.h:3028
ADC_CR_ADCAL
#define ADC_CR_ADCAL
Definition: stm32h723xx.h:2855
ADC_CFGR_RES_1
#define ADC_CFGR_RES_1
Definition: stm32h723xx.h:2868
ADC_ISR_EOC
#define ADC_ISR_EOC
Definition: stm32h723xx.h:2735
ADC_CFGR_AWD1CH
#define ADC_CFGR_AWD1CH
Definition: stm32h723xx.h:2928
ADC3_TR1_HT1
#define ADC3_TR1_HT1
Definition: stm32h723xx.h:3220
ADC_CCR_DELAY
#define ADC_CCR_DELAY
Definition: stm32h723xx.h:4071
ADC_CCR_DAMDF
#define ADC_CCR_DAMDF
Definition: stm32h723xx.h:4080
ADC_JSQR_JL
#define ADC_JSQR_JL
Definition: stm32h723xx.h:3403
ADC_CFGR_AWD1EN
#define ADC_CFGR_AWD1EN
Definition: stm32h723xx.h:2918
ADC3_OFR1_SATEN
#define ADC3_OFR1_SATEN
Definition: stm32h723xx.h:3511
ADC_CCR_VBATEN
#define ADC_CCR_VBATEN
Definition: stm32h723xx.h:4106
ADC_CFGR_EXTSEL
#define ADC_CFGR_EXTSEL
Definition: stm32h723xx.h:2873
ADC_DR_RDATA
#define ADC_DR_RDATA
Definition: stm32h723xx.h:3398
ADC_CFGR2_ROVSM
#define ADC_CFGR2_ROVSM
Definition: stm32h723xx.h:2976
ADC_LTR_LT
#define ADC_LTR_LT
Definition: stm32h723xx.h:3199
ADC_CR_JADSTP
#define ADC_CR_JADSTP
Definition: stm32h723xx.h:2817
ADC_JDR1_JDATA
#define ADC_JDR1_JDATA
Definition: stm32h723xx.h:3697
ADC_JSQR_JEXTEN
#define ADC_JSQR_JEXTEN
Definition: stm32h723xx.h:3418
ADC_CFGR2_RSHIFT2
#define ADC_CFGR2_RSHIFT2
Definition: stm32h723xx.h:2983
ADC_HTR_HT
#define ADC_HTR_HT
Definition: stm32h723xx.h:3204
ADC_JSQR_JSQ1
#define ADC_JSQR_JSQ1
Definition: stm32h723xx.h:3424
ADC_CR_ADDIS
#define ADC_CR_ADDIS
Definition: stm32h723xx.h:2805
ADC_CFGR_AWD1SGL
#define ADC_CFGR_AWD1SGL
Definition: stm32h723xx.h:2915
ADC_CFGR_JQM
#define ADC_CFGR_JQM
Definition: stm32h723xx.h:2912
ADC_CCR_DUAL
#define ADC_CCR_DUAL
Definition: stm32h723xx.h:4062
ADC_JSQR_JSQ3
#define ADC_JSQR_JSQ3
Definition: stm32h723xx.h:3442
ADC_CR_BOOST
#define ADC_CR_BOOST
Definition: stm32h723xx.h:2820
ADC_SQR1_L
#define ADC_SQR1_L
Definition: stm32h723xx.h:3243
ADC_CR_BOOST_0
#define ADC_CR_BOOST_0
Definition: stm32h723xx.h:2821
ADC3_CFGR_RES
#define ADC3_CFGR_RES
Definition: stm32h723xx.h:2948
ADC_CFGR_JDISCEN
#define ADC_CFGR_JDISCEN
Definition: stm32h723xx.h:2909
ADC_CFGR_RES
#define ADC_CFGR_RES
Definition: stm32h723xx.h:2866
ADC_CCR_TSEN
#define ADC_CCR_TSEN
Definition: stm32h723xx.h:4103
ADC_CCR_VREFEN
#define ADC_CCR_VREFEN
Definition: stm32h723xx.h:4100
ADC_CFGR_OVRMOD
#define ADC_CFGR_OVRMOD
Definition: stm32h723xx.h:2888
ADC_CFGR_EXTEN
#define ADC_CFGR_EXTEN
Definition: stm32h723xx.h:2882
ADC_AWD2CR_AWD2CH_0
#define ADC_AWD2CR_AWD2CH_0
Definition: stm32h723xx.h:3846
stm32h7xx.h
CMSIS STM32H7xx Device Peripheral Access Layer Header File.
ADC_Common_TypeDef
Definition: stm32h723xx.h:289
ADC_Common_TypeDef::CDR
__IO uint32_t CDR
Definition: stm32h723xx.h:293
ADC_Common_TypeDef::CSR
__IO uint32_t CSR
Definition: stm32h723xx.h:290
ADC_Common_TypeDef::CCR
__IO uint32_t CCR
Definition: stm32h723xx.h:292
ADC_TypeDef
Analog to Digital Converter.
Definition: stm32h723xx.h:242
ADC_TypeDef::SQR1
__IO uint32_t SQR1
Definition: stm32h723xx.h:255
ADC_TypeDef::CFGR2
__IO uint32_t CFGR2
Definition: stm32h723xx.h:247
ADC_TypeDef::CFGR
__IO uint32_t CFGR
Definition: stm32h723xx.h:246
ADC_TypeDef::JSQR
__IO uint32_t JSQR
Definition: stm32h723xx.h:262
ADC_TypeDef::CR
__IO uint32_t CR
Definition: stm32h723xx.h:245
ADC_TypeDef::LTR1
__IO uint32_t LTR1
Definition: stm32h742xx.h:249
ADC_TypeDef::CALFACT
__IO uint32_t CALFACT
Definition: stm32h742xx.h:281
ADC_TypeDef::DIFSEL
__IO uint32_t DIFSEL
Definition: stm32h742xx.h:280
ADC_TypeDef::SMPR1
__IO uint32_t SMPR1
Definition: stm32h723xx.h:248
ADC_TypeDef::IER
__IO uint32_t IER
Definition: stm32h723xx.h:244
ADC_TypeDef::CALFACT2
__IO uint32_t CALFACT2
Definition: stm32h742xx.h:282
ADC_TypeDef::DR
__IO uint32_t DR
Definition: stm32h723xx.h:259
ADC_TypeDef::DIFSEL_RES12
__IO uint32_t DIFSEL_RES12
Definition: stm32h723xx.h:282
ADC_TypeDef::OFR1
__IO uint32_t OFR1
Definition: stm32h723xx.h:264
ADC_TypeDef::JDR1
__IO uint32_t JDR1
Definition: stm32h723xx.h:269
ADC_TypeDef::LTR2_DIFSEL
__IO uint32_t LTR2_DIFSEL
Definition: stm32h723xx.h:278
ADC_TypeDef::PCSEL_RES0
__IO uint32_t PCSEL_RES0
Definition: stm32h723xx.h:250
ADC_TypeDef::CALFACT_RES13
__IO uint32_t CALFACT_RES13
Definition: stm32h723xx.h:283
ADC_TypeDef::ISR
__IO uint32_t ISR
Definition: stm32h723xx.h:243
ADC_TypeDef::CALFACT2_RES14
__IO uint32_t CALFACT2_RES14
Definition: stm32h723xx.h:284
ADC_TypeDef::PCSEL
__IO uint32_t PCSEL
Definition: stm32h742xx.h:248
ADC_TypeDef::LTR1_TR1
__IO uint32_t LTR1_TR1
Definition: stm32h723xx.h:251
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